Wafer packaging body, chip packaging body, working assembly and computing equipment

Abstract

The embodiment of the utility model provides a wafer packaging body, a chip packaging body, a working assembly and computing equipment, the wafer packaging body is arranged on one side of a printed circuit board, the wafer packaging body comprises at least one memory module, the memory module comprises a memory wafer, a logic processing wafer and a circuit element wafer which are stacked, the circuit element wafer is a digital adjustable capacitor wafer, or the circuit element wafer is a resistor-inductor-capacitor wafer. According to the technical scheme of the embodiment of the invention, a wafer-level 3D packaging solution is provided, so that ultra-large computing power and ultra-high storage bandwidth can be realized.

Description

Technical Field

[0001] The present application relates to the field of packaging technology, and in particular to a wafer package, a chip package, a working component and a computing device. Background Art

[0002] Traditional 2D chip packaging can reduce package size and improve production efficiency. However, with the increase in integration and performance requirements, 2D packaging has gradually failed to meet the needs of modern high-performance computing and storage systems. 3D packaging technology improves integration and performance by vertically stacking and interconnecting multiple chip layers, such as increasing computing power and storage bandwidth. However, traditional packaging technology is usually limited to the packaging of a single chip or chipset. Utility Model Content

[0003] The embodiments of the present application provide a wafer package, a chip package, a working component and a computing device to solve or alleviate one or more technical problems in the prior art.

[0004] As one aspect of an embodiment of the present application, an embodiment of the present application provides a wafer package for being arranged on one side of a printed circuit board, wherein the wafer package includes at least one memory module, wherein the memory module includes stacked memory wafers, logic processing wafers, and circuit element wafers, wherein the circuit element wafer is a digitally adjustable capacitor wafer, or the circuit element wafer is a resistor-inductor-capacitor wafer.

[0005] In one embodiment, the non-top wafer of the memory module is provided with through silicon vias, and the wafers of the memory module are connected by hybrid bonding or by micro bumps.

[0006] In one embodiment, in the memory module, the circuit element wafer is located between the memory wafer and the logic processing wafer.

[0007] In one embodiment, a controllable collapse chip connection C4 bump or solder ball is provided on a side of the memory module facing the printed circuit board, so that the wafer package is connected to the printed circuit board through the C4 bump or the solder ball.

[0008] In one embodiment, the memory module further includes a redistribution interposer located on a side of the C4 bump or the solder ball facing away from the printed circuit board, and the memory module is connected to the C4 bump or the solder ball through the redistribution interposer.

[0009] In one embodiment, the package further includes a substrate, located between the memory module and the printed circuit board, and used for supporting the memory module.

[0010] In one embodiment, a C4 bump is disposed on a side of the memory module facing the substrate, the C4 bump is connected to the substrate, a redistribution interposer is disposed between the memory module and the C4 bump, and the redistribution interposer is connected to the C4 bump.

[0011] As one aspect of an embodiment of the present application, an embodiment of the present application provides a chip package for being arranged on one side of a printed circuit board, the package comprising at least one memory module, the memory module comprising stacked memory dies, logic processing dies and circuit element dies, the circuit element dies being digitally adjustable capacitor dies, or the circuit element dies being resistor-inductor-capacitor dies.

[0012] As one aspect of an embodiment of the present application, the embodiment of the present application provides a working component, including a package body in any one implementation manner of the embodiment of the present application, and a printed circuit board, wherein the package body is arranged on one side of the printed circuit board.

[0013] As one aspect of an embodiment of the present application, an embodiment of the present application provides a computing device, including a working component and a power supply module in any implementation manner of the embodiment of the present application.

[0014] The technical solution of the embodiment of the present application provides a 3D packaging method for a memory layer, a logic processing layer, and a circuit element layer. This 3D packaging can be a whole wafer-level packaging or a bare chip-level packaging, which can achieve ultra-large computing power and ultra-high storage bandwidth. The circuit element layer is directly packaged together with the memory layer and the logic processing layer, and special circuit functions can be added to the packaged chip, such as filtering or noise elimination.

[0015] The above summary is for illustrative purposes only and is not intended to be limiting in any way. In addition to the illustrative aspects, embodiments and features described above, further aspects, embodiments and features of the present application will be readily apparent by reference to the accompanying drawings and the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the multiple drawings represent the same or similar parts or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings only depict some embodiments disclosed in the present application and should not be regarded as limiting the scope of the present application.

[0017] Figure 1A , Figure 1B , Figure 2A and Figure 2B A structural diagram showing a working component according to Embodiment 1 of the present application;

[0018] Figure 3A , Figure 3B , Figure 4A and Figure 4B A structural diagram showing a working component according to Embodiment 2 of the present application;

[0019] Figure 5A , Figure 5B , Fig. 6A and Figure 6B A structural diagram showing a working component according to Embodiment 3 of the present application;

[0020] Fig. 7A , Figure 7B , Fig. 8A , Figure 8B , Fig. 9A and Fig. 9B A structural diagram of the working components according to the fourth embodiment of the present application is shown.

[0021] Description of reference numerals:

[0022] 30: PCB board; 100, 200: memory module;

[0023] 101: memory wafer; 102: logic processing wafer; 103: circuit component wafer;

[0024] 201: memory die; 202: logic processing die; 203: circuit element die;

[0025] 104: C4 bump; 105: micro bump;

[0026] 110: redistribution interposer; 106: RDL medium; 107: RDL wiring layer;

[0027] 109: solder ball; 204: TSV; 20: substrate. DETAILED DESCRIPTION

[0028] In the following, only some exemplary embodiments are briefly described. As those skilled in the art will appreciate, the described embodiments may be modified in various ways without departing from the spirit or scope of the present application. Therefore, the drawings and descriptions are considered to be exemplary and non-restrictive in nature.

[0029] As technology develops, the integration of chips becomes higher and higher, and the performance is constantly improving. However, as technology further develops, it becomes more and more challenging to integrate more functions and components on a single chip, which also increases the cost and complexity of manufacturing.

[0030] In order to overcome these challenges, the concept of chiplet began to emerge in the field of semiconductor manufacturing technology. A chiplet can be understood as a small, independent chip module, which usually contains a specific functional unit or processing unit. Unlike traditional single chips, chiplets split the entire system into multiple smaller and more focused parts. These chiplets can be designed, manufactured and tested independently, and then combined together in a package to form a complete functional system or processing system to achieve higher flexibility, performance optimization and cost reduction design and manufacturing methods. Chiplet is an innovative solution to the challenges of complexity and cost in the context of continuous improvement of chip technology and performance.

[0031] Under the technical concept of chiplet, 2.5D packaging solutions have emerged, such as chip-on-wafer-on-substrate (CoWoS). In an exemplary CoWoS solution, the logic processing die and high bandwidth memory (HBM) stack are integrated together, usually by laying out multiple HBM stacks around the Logic die to provide excellent computing and memory performance. The CoWoS solution allows multiple chips with different functions to be integrated into a single package, thereby providing higher performance and efficiency. However, compared with other packaging solutions with the same computing power and the same bandwidth, the chip packaging area of ​​its CoWoS solution will also be larger, and the power consumption and cost will be higher.

[0032] Therefore, mature 3D packaging technology is urgently needed in the field of memory packaging to achieve ultra-large computing power and ultra-high storage bandwidth. The present application aims to provide a 3D packaging solution, which forms a memory module by stacking a memory layer, a logic processing layer and a circuit element layer, and packages one or more memory modules together to form a 3D package. Among them, the memory layer is a memory wafer, the logic processing layer is a logic processing wafer, and the circuit element layer is a circuit element wafer; or, the memory layer is a memory die, the logic processing layer is a logic processing die, and the circuit element layer is a circuit element die. In other words, the 3D package in the present application can be a whole layer of wafer-level packaging or a die-level packaging, so as to achieve ultra-large computing power and ultra-high storage bandwidth while meeting a variety of application scenarios, and the circuit element layer is directly packaged with the memory layer and the logic processing layer, which can add special circuit functions to the packaged chip, such as filtering or noise elimination.

[0033] Among them, wafer refers to the round silicon wafer used in the semiconductor manufacturing process, usually a wafer made of silicon material. In the field of traditional packaging, first, on the wafer, a multi-layer structure is established on the surface through a series of process steps, including an insulating layer, a conductor layer and a semiconductor layer, which constitute the components of an integrated circuit or other semiconductor device; after manufacturing, the wafer is cut into individual dies, and then the dies are packaged.

[0034] In the embodiment of the present application, the memory layer can be any type of memory, such as: dynamic random access memory (DRAM), static random access memory (SRAM), non-volatile random access memory (NVRAM), flash memory or electrically erasable programmable read-only memory (EEPROM), etc. Exemplarily, the memory can be a customized memory or a standardized memory, which is not limited in the embodiment of the present application.

[0035] The logic processing layer may be responsible for the logic processing function. Exemplarily, the logic processing layer may include a memory control unit, may include a processor unit, or may include a memory control unit and a processor unit. Among them, the processor unit is, for example, a central processing unit (CPU), a graphics processing unit (GPU), a data processor (DPU), or a knowledge processor (KPU), a tensor processor (TPU), an intelligent processor (IPU), a reconfigurable dataflow unit (Reconfigurable Dataflow Unit), a neural network processor (NPU) or other types of processors (Any type Processing Unit, xPU), responsible for executing instructions and performing various calculations and data processing tasks, including simple arithmetic operations and complex logical operations, so as to realize functions such as calculation, control, and decision-making. The memory control unit is responsible for managing and coordinating part of the memory access, such as converting the memory operation requested by the processor into the operation of the memory, and ensuring the correct transmission and storage of data to achieve efficient memory access and data transmission.

[0036] The circuit element layer can be used as a digitally adjustable capacitor (Deep Trench Capacitor, DTC) or resistance-inductance-capacitance (Resistance-Inductance-Capacitance, RLC). Among them, DTC is a capacitor whose capacitance value can be controlled by a digital signal, and is widely used in the circuit design of radio frequency and microwave frequency, such as high-frequency filters, oscillators, etc. RLC is an RLC circuit realized by semiconductor technology, which can be used for filters, tuning circuits, oscillators, impedance matching, power management, noise elimination, etc.

[0037] In one packaging form, the memory layer is a memory wafer, the logic processing layer is a logic processing wafer, and the circuit element layer is a circuit element wafer, that is, the memory module is composed of multiple wafers stacked. In another packaging form, the memory layer is a memory die, the logic processing layer is a logic processing die, and the circuit element layer is a circuit element die, that is, the memory module is composed of multiple die stacked.

[0038] Exemplarily, the package provided in the embodiment of the present application can be used for high-performance computing semiconductor working components, sensor semiconductor working components, micro-electro-mechanical systems (MEMS), optical communication semiconductor working components, etc. It should be noted that the above application scenarios or application examples provided in the embodiment of the present application are for ease of understanding, and the embodiment of the present application does not specifically limit the application of the package.

[0039] The following is a detailed description of the technical solution of the present application and how the technical solution of the present application solves the above-mentioned technical problems with specific embodiments. The listed specific embodiments may be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments.

[0040] Embodiment 1

[0041] Figure 1A and Figure 1B The following is an architecture diagram of the working components provided by the embodiment of the present application. Figure 1A and Figure 1B As shown, the working component includes at least one package and a printed circuit board (PCB) 30, wherein the package includes at least one memory module 100. When the package is used in the working component, the memory module 100 is arranged on one side of the PCB 30 of the working component.

[0042] The memory module 100 includes a memory wafer 101, a logic processing wafer 102, and a circuit element wafer 103 stacked in a direction perpendicular to the PCB board 30. In the embodiment of the present application, the circuit element wafer 103 is arranged inside the memory module 100, that is, in one package, the circuit element wafer 103 can be arranged close to the memory wafer 101 and the logic processing wafer 102, thereby shortening the transmission distance and making the loop inductance smaller. Compared with the traditional package, the decoupling effect is much better.

[0043] It should be noted that in a memory module 100, the stacking order and quantity of the memory wafer 101, the logic processing wafer 102 and the circuit element wafer 103 are not limited in the present embodiment. Figure 1A As shown, in a memory module 100, the number of memory wafer 101, logic processing wafer 102 and circuit element wafer 103 is one respectively, and the stacking order can be Figure 1AAs shown, the memory wafer 101, the logic processing wafer 102 and the circuit element wafer 103 are stacked in sequence in the up and down direction, or the logic processing wafer 102, the circuit element wafer 103 and the memory wafer 101 are stacked in sequence, or the circuit element wafer 103, the memory wafer 101 and the logic processing wafer 102 are stacked in sequence; as Figure 1B As shown, in a memory module 100, the number of memory wafers 101, logic processing wafers 102 and circuit element wafers 103 are multiple, and the stacking order between the multiple memory wafers 101, the multiple logic processing wafers 102 and the multiple circuit element wafers 103 can be set arbitrarily. In addition, the connection between adjacent wafers can be face to face (face to face) or face to back (face to back), which is not limited in the embodiment of the present application.

[0044] In one embodiment, Figure 1A and 1B As shown, in a memory module 100, the circuit element wafer 103 is located between the memory wafer 101 and the logic processing wafer 102. Based on this, the circuit element wafer 103 can be close to both the memory wafer 101 and the logic processing wafer 102, thereby further improving the decoupling effect of the memory module 100. In other words, in the memory module, the circuit element layer can be located between the memory layer and the logic processing layer, so that the circuit element layer can be close to both the memory layer and the logic processing layer to improve the decoupling effect of the memory module.

[0045] In a memory module 100, the connection mode between adjacent wafers can be configured according to actual needs, and the embodiment of the present application does not limit this. It should be noted that in the embodiment of the present application, connection (Interconnection) refers to the electrical connection between electronic components, chips, bare chips, circuit boards, wafers, etc., so as to transmit power and signals. For example, transistors on a wafer are connected to other transistors, resistors, capacitors and other components to form a complete circuit to achieve the desired function. At the same time, the wafer also needs to be connected to a circuit board, other wafers or systems to receive power and input signals and send output signals.

[0046] In one embodiment, the non-top wafer of the memory module 100 (which may be the memory wafer 101, the logic processing wafer 102, or the circuit element wafer 103) is provided with a through silicon via (TSV) (not shown in the figure due to the display ratio), that is, a vertical guide hole is formed inside the wafer to achieve interconnection and communication of chips at different levels. Each TSV is a tiny metal guide hole that passes through the thickness of the wafer and connects circuits at different levels, thereby achieving high-speed signal transmission, low-latency interconnection, and higher performance and more compact packaging solutions.

[0047] As an example, the wafers of the memory module 100 are connected by hybrid bonding. Specifically, surface chemical reactions can be used to create a very strong atomic-level connection between the two wafers, so that the chip wafers can be precisely aligned and connected at the micron scale on the wafer. Hybrid bonding is generally able to achieve the transmission of electrical signals and data without the use of solder or conductive materials, so signal transmission losses can be reduced in some applications. Because the connection is very close, high-density wafer stacking can be achieved through hybrid bonding, thereby achieving more functions in a smaller package size.

[0048] Based on this, a shorter interconnection (interconnection) distance and a higher interconnection density between wafers inside the memory module 100 can be achieved, which greatly improves the interconnection efficiency and performance.

[0049] As another example, the wafers inside the memory module 100 are connected via microbumps 105. Specifically, ubumps are tiny protruding structures, usually made of metal materials, so as to form interconnections and communications between wafers. Moreover, such structures are usually manufactured by microelectronic processes, and their size, position, and arrangement can be precisely controlled to achieve high-density connections.

[0050] In one connection mode, such as Figure 1A and Figure 1B As shown, a controlled collapse chip connection (Controlled Collapse Chip Connection, C4 bump or C4 bump for short) 104 is provided on one side of the memory module 100 facing the PCB board 30 , and the memory module 100 is connected to the PCB board 30 via the C4 bump 104 .

[0051] Specifically, the bottom wafer (such as memory wafer 101) of the memory module 100 may be provided with C4 bumps 104 on one side facing the PCB board 30, and the bottom wafer (memory wafer 101) is connected to the PCB board 30 via the C4 bumps 104. Other wafers in the memory module 100 may also be connected to the PCB board 30 via the bottom wafer and the C4 bumps 104.

[0052] Among them, the C4 bump 104 is made by a bumping process, and the core process flow is metal deposition, and the most common metal deposition steps include the deposition of the under bump metallization layer (UBM) and the deposition of the bump itself. The deposition of the under bump metallization layer (UBM) is usually achieved by sputtering, electroless plating, electroplating, etc.; the deposition of the bump itself is usually achieved by electroplating, ball planting, and printing. In the embodiment of the present application, the C4 bump 104 is used to achieve the connection between the memory module 100 and the PCB board 30. Since the C4 bump can be arranged at a smaller pitch, this connection method can achieve high-density and precise connection between the memory module 100 and the PCB board 30.

[0053] In one connection method, the C4 bump can be replaced with a solder ball, that is, a solder ball is provided on the side of the PCB board 30 facing the memory module 100, and the memory module 100 is connected to the PCB board 30 through the solder ball. The solder ball is also called a solder bead, which is usually made of tin or other alloys and is spherical in shape. As a traditional connection method, the solder ball has a simple process and low cost. The use of the solder ball to achieve the connection between the memory module 100 and the PCB board 30 can simplify the process, reduce costs, and improve the yield rate while ensuring the connection performance.

[0054] In one connection mode, such as Figure 2A and Figure 2B As shown, the memory module 100 also includes a redistribution layer (RDL) interposer 110, which is located on the side of the C4 bump 104 away from the PCB board 30. The memory module 100 is connected to the C4 bump 104 through the redistribution interposer 110, and then connected to the PCB board 30 through the C4 bump 104.

[0055] In one connection method, the memory module 100 is connected to the solder balls through the redistribution interposer 110 , and then connected to the PCB board 30 through the solder balls.

[0056] The redistribution layer interposer 110 generally includes an RDL medium 106 and an RDL wiring layer 107 in the RDL medium 106. The RDL medium 106 is generally made of an organic material; the common material of the RDL wiring layer 107 is electroplated copper (Plated Cu) supplemented with a titanium and copper sputtering layer as a primer; the surface of the copper layer is then covered with a corresponding protective layer ink as needed. In other words, the connection between the memory module 100 and the C4 bump 104 or solder ball can be realized based on the RDL wiring layer 107 in the redistribution interposer 110, thereby realizing the connection between the memory module 100 and the PCB board 30. In this embodiment, a high-density connection between the memory module 100 and the PCB board 30 can be realized based on the redistribution layer interposer 110, and the connection accuracy can be improved.

[0057] According to the package of the embodiment of the present application, by directly packaging a whole layer of memory wafers and a whole layer of logic processing wafers as a memory module, no cutting is required, so that ultra-large computing power and ultra-high storage bandwidth can be achieved. At the same time, the circuit element wafer is packaged together with the memory wafer and the logic processing wafer as part of the memory module, which can add some special circuit functions to the memory module, shorten the transmission distance, and increase the connection density.

[0058] The embodiment of the present application also provides a working component, including a PCB board 30 and at least one package, which can be any of the packages described above. It should be noted that the working component can include one package, or multiple packages, for example, including both the package provided by the embodiment of the present application and conventional packages known to those skilled in the art. The embodiment of the present application does not specifically limit the type, quantity and connection topology of the package. In addition, there can be a connection relationship between at least some of the packages.

[0059] Exemplarily, the package body may be directly arranged on one side of the PCB board 30 without molding the package body, that is, without plastic sealing the wafer on the PCB board 30 .

[0060] According to the working components provided in the embodiments of the present application, the disadvantages of small storage bandwidth and small computing power of traditional packaging solutions can be avoided, and advanced packaging technology can be provided to increase storage bandwidth, thereby improving chip computing power.

[0061] It should be noted that in the first embodiment of the present application, for the solution in which the memory module 100 is formed by stacking wafers, the PCB board 30 as a packaging board needs to carry the wafers, so its size is larger than that of a conventional PCB board, that is, larger than the size of the wafer it carries.

[0062] Other components of the package or working components of the above-mentioned embodiments may adopt various technical solutions known to ordinary technicians in the field now and in the future, and will not be described in detail here.

[0063] Embodiment 2

[0064] This embodiment provides a package body, in which a substrate is added on the basis of the first embodiment. Therefore, all or part of the implementation methods and corresponding technical effects of the first embodiment can be referenced to this embodiment.

[0065] like Figure 3A and Figure 3B As shown, the package of this embodiment further includes a substrate 20. Specifically, the substrate 20 is disposed between the memory module 100 and the PCB board 30, and the memory module 100 is connected to the PCB board 30 through the substrate 20.

[0066] In order to facilitate the horizontal expansion of the memory module 100, multiple memory modules 100 can be arranged horizontally on the substrate 20, so as to realize the horizontal connection of the memory module 100 on the substrate 20. Then, the memory module 100 is connected to the PCB board 30 through the substrate 20, which can improve the connection reliability and realize ultra-large computing power and ultra-high storage bandwidth.

[0067] In one embodiment, Figure 3A and Figure 3B As shown, a C4 bump 104 is disposed on one side of the memory module 100 facing the substrate 20, and the memory module 100 is connected to the substrate 20 via the C4 bump 104. Based on this, a high-density connection and a precise connection between the substrate 20 and the memory module 100 can be achieved.

[0068] In one embodiment, Figure 4A and Figure 4B As shown, a redistribution interposer 110 is disposed between the memory module 100 and the C4 bump 104, and the memory module 100 is connected to the C4 bump 104 via the redistribution interposer 110. Based on this, a high-density connection between the substrate 20 and the memory module 100 can be achieved, and the connection accuracy can be improved.

[0069] The embodiment of the present application also provides a working component, including a PCB board 30 and at least one package, which can be any of the packages described above. It should be noted that the working component can include one package, or multiple packages, for example, including both the package provided by the embodiment of the present application and conventional packages known to those skilled in the art. The embodiment of the present application does not specifically limit the type, quantity and connection topology of the package. In addition, there can be a connection relationship between at least some of the packages.

[0070] Exemplarily, the package body may be directly arranged on one side of the PCB board 30 without molding the package body, that is, without plastic sealing the wafer on the PCB board 30 .

[0071] According to the working components provided in the embodiment of the present application, the disadvantages of small storage bandwidth and small computing power of the traditional packaging solution can be avoided, and advanced packaging technology can be provided to increase the storage bandwidth, thereby improving the chip computing power. It should be noted that in the second embodiment of the present application, for the solution in which the memory module 100 is formed by stacking wafers, the substrate 20 as a packaging board needs to carry the wafer, so its size is larger than the conventional substrate size, that is, larger than the size of the wafer carried.

[0072] Other components of the package or working components of the above-mentioned embodiments may adopt various technical solutions known to ordinary technicians in the field now and in the future, and will not be described in detail here.

[0073] Embodiment 3

[0074] Figure 5A and Figure 5B The following is an architecture diagram of the working components provided by the embodiment of the present application. Figure 5A and Figure 5B As shown, the working component includes at least one package and a PCB board 30, wherein the package includes at least one memory module 200. When the package is used in the working component, the memory module 200 is arranged on one side of the PCB board 30 of the working component.

[0075] The memory module 200 includes a memory die 201, a logic processing die 202, and a circuit element die 203 stacked in a direction perpendicular to the PCB board 30. In the embodiment of the present application, the circuit element die 203 is arranged inside the memory module 200, that is, in one package, the circuit element die 203 is closer to the memory die 201 and the logic processing die 202, so that the transmission distance can be shortened, the loop inductance is smaller, and the decoupling effect is much better than that of the traditional package.

[0076] It should be noted that in a memory module 200, the stacking order and quantity of the memory die 201, the logic processing die 202 and the circuit element die 203 are not limited in the present embodiment. Figure 5AAs shown, in a memory module 200, the number of memory die 201, logic processing die 202 and circuit element die 203 is one respectively, and the stacking order may be that the memory die 201, the logic processing die 202 and the circuit element die 203 are stacked in sequence, or that the logic processing die 202, the circuit element die 203 and the memory die 201 are stacked in sequence, or that the circuit element die 203, the memory die 201 and the logic processing die 202 are stacked in sequence; as shown in FIG. Figure 5B As shown, in a memory module 200, the number of memory dies 201, logic processing dies 202 and circuit element dies 203 are multiple, and the stacking order between the multiple memory dies 201, the multiple logic processing dies 202 and the multiple circuit element dies 203 can be set arbitrarily. In addition, the connection mode between adjacent dies can be face-to-face or face-to-back, which is not limited in the embodiment of the present application.

[0077] In one embodiment, Figure 5A and 5B As shown, in a memory module 200, the circuit element die 203 is located between the memory die 201 and the logic processing die 202. Based on this, the circuit element die 203 can be close to both the memory die 201 and the logic processing die 202, thereby further improving the decoupling effect of the memory module 200. In other words, in the memory module, the circuit element layer can be located between the memory layer and the logic processing layer, so that the circuit element layer can be close to both the memory layer and the logic processing layer, thereby improving the decoupling effect of the memory module.

[0078] In a memory module 200 , the connection method between adjacent bare chips can be configured according to actual needs, and the embodiment of the present application is not limited to this.

[0079] In one embodiment, a non-top-level die of the memory module 200 (which may be a memory die 201, a logic processing die 202, or a circuit element die 203) is provided with TSV 204 to achieve interconnection and communication between dies at different levels, thereby achieving high-speed signal transmission, low-latency interconnection, and a higher performance, more compact packaging solution.

[0080] As an example, the bare chips of the memory module 200 are connected by hybrid bonding, which can reduce the loss of signal transmission. Since the connection is very close, high-density bare chip stacking can be achieved through hybrid bonding, thereby realizing more functions in a smaller package size.

[0081] Based on this, a shorter interconnection (interconnection) distance and a higher interconnection density between the bare chips inside the memory module 200 can be achieved, which greatly improves the interconnection efficiency and performance.

[0082] As another example, the bare chips within the memory module 200 are connected via micro bumps 105, whose size, position and arrangement can be precisely controlled to achieve high-density connection.

[0083] In one connection mode, such as Figure 5A and Figure 5B As shown, a C4 bump 04 is provided on the side of the memory module 200 facing the PCB board 30 , and the memory module 200 is connected to the PCB board 30 via the C4 bump 104 .

[0084] Specifically, the bottom die (such as the memory die 201) of the memory module 200 may be provided with a C4 bump 104 on one side facing the PCB board 30, and the bottom die (memory die 201) is connected to the PCB board 30 via the C4 bump 104. Other die in the memory module 200 may also be connected to the PCB board 30 via the bottom die and the C4 bump 104. Since the C4 bumps can be arranged at a smaller pitch, this connection method can achieve high-density connection and precise connection between the memory module 200 and the PCB board 30.

[0085] In one connection method, the C4 bump can be replaced with a solder ball, that is, a solder ball is provided on the side of the PCB board 30 facing the memory module 200, and the memory module 200 is connected to the PCB board 30 through the solder ball. Under the premise of ensuring the connection performance, the process can be simplified, the cost can be reduced, and the yield can be improved.

[0086] In one connection mode, such as Fig. 6A and Figure 6B As shown, the memory module 200 further includes a redistribution layer interposer 110 located on the side of the C4 bump 104 away from the PCB board 30 . The memory module 200 is connected to the C4 bump 104 through the redistribution interposer 110 , and further connected to the PCB board 30 through the C4 bump 104 .

[0087] In one connection method, the memory module 200 is connected to the solder balls through the redistribution interposer 110 , and then connected to the PCB board 30 through the solder balls.

[0088] The redistribution layer interposer 110 generally includes an RDL medium 106 and an RDL wiring layer 107 in the RDL medium 106. The RDL wiring layer 107 in the redistribution layer 110 can be used to connect the memory module 200 to the C4 bumps 104 or solder balls, thereby connecting the memory module 200 to the PCB board 30. In this embodiment, a high-density connection between the memory module 200 and the PCB board 30 can be achieved based on the redistribution layer interposer 110, and the connection accuracy can be improved.

[0089] It should be noted that the package provided in the embodiment of the present application may include multiple memory modules 200, and the multiple memory modules 200 may be connected in a direction parallel to the PCB, that is, the multiple memory modules 200 may be horizontally expanded, and the embodiment of the present application does not limit the horizontal expansion method and the horizontal connection method.

[0090] For example, based on the TSV 204 in the circuit element die 203, the TSV 204 in the memory die 201, the C4 bump 104 and the substrate 20, a plurality of logic processing dies 202 can be connected to each other, such as Fig. 7A Alternatively, based on the TSV204 in the circuit element die 203, the TSV204 in the memory die 201, the redistribution interposer 110, the C4 bump 104 and the substrate 20, multiple logic processing dies 202 can be connected to each other, such as Fig. 8A shown.

[0091] For example, based on the C4 bumps 104 and the substrate 20, a plurality of logic processing dies 202 can be connected to each other, such as Fig. 9A Alternatively, based on the redistribution interposer 110, the C4 bumps 104 and the substrate 20, a plurality of logic processing dies 202 may be interconnected, such as Fig. 9B shown.

[0092] The embodiment of the present application also provides a working component, including a PCB board 30 and at least one package, which can be any of the packages described above, for example, including the package provided by the embodiment of the present application, and can also include a conventional package known to those skilled in the art. It should be noted that the working component can include one package or multiple packages, and the embodiment of the present application does not specifically limit the type, quantity and connection topology of the package. In addition, at least some of the packages can be connected.

[0093] Exemplarily, the package body may be directly arranged on one side of the PCB board 30 without molding the package body, that is, without plastic sealing the wafer on the PCB board 30 .

[0094] According to the working components provided in the embodiments of the present application, the disadvantages of small storage bandwidth and small computing power of traditional packaging solutions can be avoided, and advanced packaging technology can be provided to increase storage bandwidth, thereby improving chip computing power.

[0095] Other components of the package or working components of the above-mentioned embodiments may adopt various technical solutions known to ordinary technicians in the field now and in the future, and will not be described in detail here.

[0096] Embodiment 4

[0097] This embodiment provides a package body, in which a substrate is added on the basis of the third embodiment. Therefore, all or part of the implementation methods and corresponding technical effects of the third embodiment can be referenced to this embodiment.

[0098] like Fig. 7A and Figure 7B As shown, the package of this embodiment further includes a substrate 20. Specifically, the substrate 20 is disposed between the memory module 200 and the PCB board 30, and the memory module 200 is connected to the PCB board 30 through the substrate 20.

[0099] In order to facilitate the horizontal expansion of the memory module 200, multiple memory modules 200 can be horizontally arranged on the substrate 20, and then the multiple memory modules 200 can be horizontally connected on the substrate 20. Then, the memory module 200 is connected to the PCB board 30 through the substrate 20, which can improve the connection reliability and achieve ultra-large computing power and ultra-high storage bandwidth.

[0100] In one embodiment, Fig. 7A and Figure 7B As shown, a C4 bump 104 is disposed on one side of the memory module 200 facing the substrate 20, and the memory module 200 is connected to the substrate 20 via the C4 bump 104. Based on this, a high-density connection and a precise connection between the substrate 20 and the memory module 200 can be achieved.

[0101] In one embodiment, Fig. 8A and Figure 8B As shown, a redistribution interposer 110 is disposed between the memory module 200 and the C4 bump 104, and the memory module 200 is connected to the C4 bump 104 via the redistribution interposer 110. Based on this, a high-density connection between the substrate 20 and the memory module 200 can be achieved, and the connection accuracy can be improved.

[0102] The embodiment of the present application also provides a working component, including a PCB board 30 and at least one package, which can be any of the packages described above. It should be noted that the working component can include one package, or multiple packages, for example, including both the package provided by the embodiment of the present application and conventional packages known to those skilled in the art. The embodiment of the present application does not specifically limit the type, quantity and connection topology of the package. In addition, there can be a connection relationship between at least some of the packages.

[0103] Exemplarily, the package body may be directly arranged on one side of the PCB board 30 without molding the package body, that is, without plastic sealing the wafer on the PCB board 30 .

[0104] According to the working components provided in the embodiments of the present application, the disadvantages of small storage bandwidth and small computing power of traditional packaging solutions can be avoided, and advanced packaging technology can be provided to increase storage bandwidth, thereby improving chip computing power.

[0105] Other components of the package or working components of the above-mentioned embodiments may adopt various technical solutions known to ordinary technicians in the field now and in the future, and will not be described in detail here.

[0106] Embodiment 5

[0107] The embodiment of the present application further provides a computing device, including any working component of the above embodiment and a power supply module, wherein the power supply module is used to provide power to the working component, and the number of the working components can be one or more, which is not limited in the embodiment of the present application. Exemplarily, at least some of the multiple working components are interconnected, which can be electrically connected or physically connected, which is not limited in the embodiment of the present application.

[0108] Illustratively, the computing device provided in the embodiments of the present application can be used in devices and systems that require a large amount of computing power, such as supercomputers, servers in data centers, high-performance workstations, scientific research equipment, etc., and can be applied in the fields of artificial intelligence, deep learning, big data analysis, etc.

[0109] Illustratively, the computing device provided in the embodiments of the present application can be used in various devices that need to monitor and measure physical or chemical changes, such as smart phones, automobiles, industrial automation equipment, medical equipment, and other fields that require high-performance sensor chips.

[0110] Illustratively, the computing device provided in the embodiments of the present application can be used in micro-electromechanical systems, such as gyroscopes and accelerometers of smartphones, airbag triggering systems of cars, micro-lens arrays of projectors, etc.

[0111] Illustratively, the computing device provided in the embodiments of the present application can be used in fiber-optic communication systems, such as fiber-optic network equipment, optical interconnection in data centers, long-distance fiber-optic transmission systems, and other fields that require high-speed data transmission.

[0112] When the computing device is used in different systems or fields, other components of the computing device may be different. Other components of the computing device in the above embodiment may adopt various technical solutions known to ordinary technicians in this field now and in the future, which will not be described in detail here.

[0113] In the description of this specification, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0114] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features.

[0115] In this application, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or a communication; it can be a direct connection, or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0116] In the present application, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may include that the first and second features are in direct contact, or may include that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, a first feature being "above", "above" and "above" a second feature includes that the first feature is directly above and obliquely above the second feature, or simply indicates that the first feature is higher in level than the second feature. A first feature being "below", "below" and "below" a second feature includes that the first feature is directly above and obliquely above the second feature, or simply indicates that the first feature is lower in level than the second feature.

[0117] The disclosure above provides many different embodiments or examples to realize the different structures of the present application. In order to simplify the disclosure of the present application, the parts and settings of specific examples are described above. Of course, they are only examples, and the purpose is not to limit the present application. In addition, the present application can repeat reference numerals and / or reference letters in different examples, and this repetition is for the purpose of simplification and clarity, and does not indicate the relationship between the various embodiments and / or settings discussed in itself.

[0118] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of various changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A wafer package, characterized in that: Used to be arranged on one side of a printed circuit board, the wafer package includes at least one memory module, the memory module includes stacked memory wafers, logic processing wafers and circuit element wafers, the circuit element wafer is a digitally adjustable capacitor wafer, or the circuit element wafer is a resistor-inductor-capacitor wafer.

2. The wafer package according to claim 1, wherein: The non-top wafer of the memory module is provided with silicon through-holes, and the wafers of the memory module are connected by hybrid bonding or by micro-bumps.

3. The wafer package according to claim 1, wherein: In the memory module, the circuit element wafer is located between the memory wafer and the logic processing wafer.

4. The wafer package according to any one of claims 1 to 3, characterized in that: A controllable collapse chip connection C4 bump or solder ball is arranged on one side of the memory module facing the printed circuit board, so that the wafer package is connected to the printed circuit board through the C4 bump or the solder ball.

5. The wafer package according to claim 4, characterized in that: The memory module further comprises a redistribution interposer located at a side of the C4 bump or the solder ball away from the printed circuit board, and the memory module is connected to the C4 bump or the solder ball through the redistribution interposer.

6. The wafer package according to any one of claims 1 to 3, characterized in that: It also includes a substrate, which is located between the memory module and the printed circuit board and is used to support the memory module.

7. The wafer package according to claim 6, wherein: A C4 bump is arranged on the side of the memory module facing the substrate, and the C4 bump is connected to the substrate. A redistribution intermediary layer is arranged between the memory module and the C4 bump, and the redistribution intermediary layer is connected to the C4 bump.

8. A chip package, characterized in that: Used to be arranged on one side of a printed circuit board, the package includes at least one memory module, the memory module includes stacked memory chips, logic processing chips and circuit element chips, the circuit element chips are digitally adjustable capacitor chips, or the circuit element chips are resistor-inductor-capacitor chips.

9. A working component, characterized in that: include: The package according to any one of claims 1 to 8; A printed circuit board is provided with the package body on one side of the printed circuit board.

10. A computing device, characterized in that: It comprises the working component and the power supply module as described in claim 9.

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