Electronic device

Abstract

The utility model relates to an electronic device. There is provided an electronic device including: a semiconductor body of SiC having an upper surface and a lower surface opposite to each other along a first axis, and including: a drain substrate extending into the semiconductor body from the bottom surface and having a first conductivity type; a drift layer extending from the upper surface into the semiconductor body and having a first conductivity type and a second dopant concentration; a body region housed in the drift layer; and a source region housed in the body region. The electronic device further includes a gate structure on the upper surface. The semiconductor body further includes at least one doped pocket region buried in the drift layer, having a second conductivity type and aligned with the source region and / or the gate structure along the first axis.

Description

Technical Field

[0001] The present disclosure relates to a power electronic device with improved electrical performance. Specifically, it relates to a silicon carbide electronic device, which includes one or more power MOSFETs with improved electrical operation and reliability. In addition, it also relates to an apparatus including the power electronic device. Background Art

[0002] As is known, power devices are electronic devices used to operate at high voltage and / or current (e.g., voltages up to 1700V and currents up to tens / hundreds of amperes in a suppressed state), and are used in a variety of application fields. For example, power devices are generally used in audio amplifiers, motor control devices, power supplies or power switches, and power devices include power diodes, power transistors, thyristors, insulated gate bipolar transistors (IGBTs), metal oxide semiconductor field effect transistors (MOSFETs).

[0003] In power devices, a wide bandgap (for example, a bandgap energy value Eg greater than 1.1 eV), a low on-state resistance (R ON ), high thermal conductivity values, high operating frequencies and high charge carrier saturation velocity. A material having these properties and designed for the manufacture of electronic components is silicon carbide (SiC). In particular, silicon carbide (in its different polytypes (e.g., 3C-SiC, 4H-SiC, 6H-SiC)) is preferred over silicon with respect to the properties listed above.

[0004] Electronic devices formed starting from silicon carbide substrates have many advantages over similar devices provided on silicon substrates, such as low output resistance when on, low leakage current, high operating temperature, and high operating frequency.

[0005] In particular, SiC MOSFETs have demonstrated enhanced switching performance, which makes these SiC power devices particularly beneficial for high-frequency applications.

[0006] In particular, a power MOSFET in saturation mode (operating in the active region) is sometimes used as a constant current source by varying the gate-source voltage V GS In fact, in saturation mode, the drain-source current I DS Almost the same as the drain-source voltage V DS is irrelevant, but will depend on the gate-source voltage V GS change.

[0007] In different applications, the power MOSFET operates in the linear mode of switching (also called ohmic or triode region), switching from the ON state to the OFF state and vice versa. The linear mode is characterized by the current I DS and voltage V DS The linear relationship between the drain-source on-resistance R DSon (hereinafter also referred to as on-resistance R DSon ). In this mode of operation, the switching speed between the off and on states affects the characteristics of the power MOSFET device. In fact, the slower the transition from the on state to the off state, the greater the power dissipation during switching and the threshold voltage V TH The greater the probability of thermal drift.

[0008] Therefore, SiC power MOSFETs are designed to minimize switching times, thereby reducing the probability that these disadvantages will occur. However, reducing the switching time leads to the known "ringing" phenomenon of the MOSFET current and voltage during the switching phase in the dynamic and transient domain (i.e., the phenomenon of substantially sinusoidal oscillations in the current and voltage, which start at the time of switching and decrease in amplitude over time until it ends after the transient period starting from the switching moment). The ringing phenomenon causes current and voltage "overshoots" (i.e., current and voltage oscillation peaks with significant amplitudes), which usually exceed the current and voltage that the MOSFET is designed to safely withstand. Therefore, overshoots may damage the MOSFET, increase power losses, and introduce electromagnetic interference and noise of non-negligible importance.

[0009] Furthermore, a common trend in SiC power MOSFETs is to continually reduce the size of SiC power MOSFETs to allow for a higher density of MOSFETs in the same area unit, thereby improving the computing performance of devices with MOSFETs without having to increase the size of the device accordingly. In particular, in vertical structure MOSFETs, this is achieved by reducing the distance between the body regions of each MOSFET unit below the gate structure. This reduces the size of the MOSFET, but because the contact surface between the gate structure of the MOSFET and the drift layer is reduced, this also leads to a reduction in the gate-drain capacitance. The reduction in gate-drain capacitance makes the drain region less capacitively coupled to the gate structure dynamically, and therefore makes the drain region more susceptible to sudden changes in the drain voltage. This negative consequence is therefore the cause of MOSFET overshoot and, more generally, the cause of the ringing phenomenon.

[0010] The reduction of the gate-drain capacitance reduces the "parasitic turn-on" (PTO) phenomenon of the MOSFET, i.e., the conduction channel of the MOSFET is turned on when the MOSFET is controlled to operate in the reverse mode but there are oscillations of the drain voltage, which, due to the dynamic capacitive coupling between the gate structure and the drain region, produce corresponding oscillations of the gate voltage, thereby activating the conduction of the MOSFET in any case. Although PTO is generally undesirable because it makes the MOSFET less reliable and more susceptible to failure, PTO also has the positive effect of reducing ringing phenomena because it reduces the maximum amplitude of the MOSFET overshoot. However, since reducing the size of the MOSFET will reduce the PTO, this phenomenon cannot be effectively used in scaling down the MOSFET to reduce the ringing phenomenon.

[0011] Some solutions to the MOSFET ringing problem are known.

[0012] For example, it is known to increase the gate resistance by adding an additional series resistor to the gate structure, such as a resistor integrated in the MOSFET or a resistor external to the MOSFET. It has been shown that this reduces the risk of ringing of the MOSFET. However, it is generally difficult to properly select the resistor to be added to the gate structure without excessively degrading the electrical performance of the MOSFET. In fact, an increase in the gate resistance usually leads to a significant increase in the switching time of the MOSFET, resulting in a deterioration of the MOSFET operation when used in linear mode.

[0013] Furthermore, it is known to use external electronic circuits (e.g., "buffer" or "damping" circuits based on RC circuits) to improve the electrical control of the gate structure and thus reduce the overshoot of the MOSFET. However, the presence of these electronic circuits external to the MOSFET complicates the design of the device including the MOSFET and increases its cost and power consumption.

[0014] Furthermore, another common problem, particularly in high power MOSFETs (ie, in MOSFETs configured to operate at drain-source voltages greater than about 1200 V), is the "snappy" behavior of the MOSFET.

[0015] In particular, this behavior is identified by a sudden change in the slope of the drain-source voltage and drain-source current curves, which occurs, for example, when a high-power MOSFET is operated at an operating voltage of about 1200 V, at a drain-source voltage equal to about 850 V, at a temperature of 175° C. / 200° C. and at a value of the rate of change of the recovery current di / dt greater than about 2.5 A / ns. This causes an overshoot of the drain-source voltage to occur, which may lead to instability and failure of the MOSFET, degradation of the electrical performance of the MOSFET and ringing phenomena that cause noise and electromagnetic interference disturbances. In extreme cases, the amplitude of this overshoot may reach or even exceed the avalanche breakdown voltage, resulting in an avalanche breakdown of the MOSFET.

[0016] It has been demonstrated that the active behavior occurs due to the abrupt recombination of minority charge carriers at the interface between the drift layer and the drain layer.

[0017] In fact, to ensure proper electrical operation, high power MOSFETs have a low dopant concentration in the drift layer (e.g., less than about 1·10 16 at / cm 3 ), and therefore has a large number of minority carriers in the depletion region of the drift layer. If the MOSFET is operated at a high temperature (e.g., greater than about 170°C), the lifetime of these minority carriers (which is known to be proportional to the temperature of the MOSFET) may increase to the point where complete recombination is not possible before reaching the drain region. In this case, a portion of the minority carriers do not recombine in the drift layer (where recombination would otherwise occur) and simply disappear at the interface between the drift layer and the drain layer. For a specific time interval starting from the moment when the minority carriers begin to recombine at the interface between the drift layer and the drain layer, this recombination generates an output parasitic capacitance C of the MOSFET. oss (equal to the sum of the drain-source capacitance and the gate-source capacitance, the output parasitic capacitance is constant) and therefore results in an active behavior of the MOSFET during this time interval.

[0018] In contrast, this problem is less of a concern in low-power MOSFETs (i.e., in MOSFETs configured to operate at a drain-source voltage below about 1200 V (e.g., equal to about 650 V), which have a higher dopant concentration in the drift layer and thus a higher recombination rate of minority carriers, thereby reducing the average lifetime of minority carriers), and in MOSFETs that do not operate at high temperatures (e.g., operating at temperatures below about 170°C (e.g., equal to about 30-100°C), which thus have a shorter average lifetime of minority carriers).

[0019] Known solutions to this problem are similar to those previously proposed to counteract MOSFET ringing and therefore include increasing the resistance of the gate structure or using external electronic circuits coupled to the MOSFET. Therefore, the same disadvantages previously described apply to these solutions.

[0020] The purpose of the present disclosure is to provide a power electronic device and a corresponding apparatus that overcome the defects of the prior art. Utility Model Content

[0021] Embodiments of the present disclosure provide a power electronic device and a corresponding apparatus that at least partially overcome the deficiencies of the prior art.

[0022] In one embodiment, an electronic device includes a semiconductor body of silicon carbide, the semiconductor body of silicon carbide having an upper surface and a lower surface opposite to each other along a first axis. The semiconductor body includes a drain substrate, which extends from the lower surface of the semiconductor body into the semiconductor body and has a first conductivity type and a first dopant concentration. The semiconductor body includes a drift layer, which extends from the upper surface of the semiconductor body into the semiconductor body and extends to the drain substrate, and has a first conductivity type and a second dopant concentration lower than the first dopant concentration. The semiconductor body includes at least one first body region, which extends from the upper surface of the semiconductor body into the semiconductor body and is accommodated in the drift layer at a certain distance from the drain substrate, and has a second conductivity type opposite to the first conductivity type. The semiconductor body includes at least one first source region, which extends from the upper surface of the semiconductor body into the semiconductor body, is accommodated in the first body region to be spaced apart from the drift layer, and has a first conductivity type. The electronic device includes at least one first gate structure extending on the upper surface of the semiconductor body and superimposed on the first body region along the first axis to form a first MOSFET portion of a first MOSFET with the first source region, the first body region, the drift layer and the drain substrate. The semiconductor body further includes at least one first doped pocket region, the at least one first doped pocket region buried in the drift layer, having a second conductivity type and at least partially aligned with the first source region and / or with the first gate structure along the first axis.

[0023] In one embodiment, an electronic device includes a semiconductor body of silicon carbide. The semiconductor body includes: a drain substrate having a first conductivity type and a first dopant concentration; a drift layer located above the drain substrate and having the first conductivity type and a second dopant concentration lower than the first dopant concentration; a body region having a top surface coplanar with a top surface of the drift layer, which is separated from the drain substrate by the drift layer and has a second conductivity type opposite to the first conductivity type. The semiconductor body includes a source region, which is embedded in the body region and separated from the drift layer by the body region and has a first conductivity type; and a first doped pocket region, which has a second conductivity type, is embedded in the drift layer and has a top surface lower than the bottom surface of the body region and a bottom surface higher than the top surface of the drain substrate. The electronic device includes a gate structure, which is located directly above at least a portion of the first body region and at least a portion of the first doped pocket region. The source region, the body region, the drift layer, and the drain substrate form a MOSFET.

[0024] In one embodiment, a method includes: forming a semiconductor body of silicon carbide, forming a drain substrate of a MOSFET having a first conductivity type and a first dopant concentration in the semiconductor body, and forming a drift layer of the MOSFET above the drain substrate in the semiconductor body, the drift layer having the first conductivity type and a second dopant concentration lower than the first dopant concentration. The method includes forming a body region of the MOSFET in the semiconductor body, the body region having a top surface coplanar with a top surface of the drift layer, which is separated from the drain substrate by the drift layer, and having a second conductivity type opposite to the first conductivity type. The method includes: forming a source region of the MOSFET, the source region being embedded in the body region and separated from the drift layer by the body region, and having the first conductivity type; forming a first doped pocket region having the second conductivity type, the first doped pocket region being embedded in the drift layer and having a top surface lower than the bottom surface of the body region and a bottom surface higher than the top surface of the drain substrate; and forming a gate structure of the MOSFET directly above at least a portion of the first body region and at least a portion of the first doped pocket region. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] For a better understanding of the present disclosure, preferred embodiments will now be described by way of non-limiting examples only, with reference to the accompanying drawings, in which:

[0026] Figure 1-Figure 5 is a cross-sectional view of a corresponding embodiment of an electronic device;

[0027] Figure 6A-6F The cross-sectional view shows Figure 1-Figure 5 A depletion region of a portion of a MOSFET of an electronic device changes as electrical control conditions of the MOSFET change;

[0028] Fig. 7A and 7B It is shown Figure 1-Figure 5 A graph of corresponding electrical signals of an electronic device;

[0029] Figure 8 and Fig. 9 are cross-sectional views of corresponding and further embodiments of electronic devices;

[0030] Fig. 10A and Fig. 10B is a top view with hidden portions of a corresponding embodiment of an electronic device; and

[0031] Fig.11 is a cross-sectional view of another embodiment of an electronic device.

[0032] In particular, the figures are shown with reference to a three-axis Cartesian system defined by an axis X, an axis Y and an axis Z that are orthogonal to one another.

[0033] In the subsequent description, elements common to different embodiments are indicated by the same reference numerals. DETAILED DESCRIPTION

[0034] Figure 1 An exemplary embodiment of a power electronic device 10 is shown in a transverse cross-sectional view.

[0035] In particular, Figure 1 , a power electronic device 10 (hereinafter also referred to as electronic device 10 or more simply as device 10) is shown in a plane XZ (defined by axes X and Z). The device 10 has a main extension parallel to the axis Y, Figure 1 A cross section perpendicular to the main extension is shown.

[0036] The device 10 is for example in a device (not shown, a device of the electrical / electronic type, such as a laptop, a mobile phone, a server, a TV, a car, a car charging station or a conversion system for photovoltaic panels).

[0037] The device 10 has an active region (not shown) in which one or more MOSFETs 10' are housed, particularly vertical structure MOSFETs (e.g., enhancement type). Figure 1 In the exemplary and non-limiting embodiment of , three MOSFETs 10′ are shown arranged laterally to each other along the axis X to form a MOSFET array; however, the number of MOSFETs 10′ may vary in a manner which is obvious in itself and may be, for example, higher (e.g., ten or a hundred) or lower (e.g., only one MOSFET).

[0038] The device 10 includes a substrate (or drain substrate) 16 of silicon carbide (ie, SiC, such as 4H-SiC). The substrate 16 forms the drain region of the MOSFET 10'.

[0039] The substrate 16 has a first conductivity type (hereinafter considered N-type conductivity) and a first dopant concentration (or a first conductivity value), for example, at about 10 18 at / cm 3 order of magnitude.

[0040] Substrate 16 has an upper surface 16a and a lower surface 16b opposite one another along axis Z. For example, substrate 16 has a thickness along axis Z between surfaces 16a and 16b of between about 50 and 350 μm, more particularly between about 160 and 200 μm, for example equal to about 180 μm.

[0041] The device 10 includes a drift layer 17 of SiC (such as 4H-SiC) extending over a substrate 16. In particular, the drift layer 17 is grown on the substrate 16 in an epitaxial manner.

[0042] The drift layer 17 has a first conductivity type (here, N-type) and a second dopant concentration lower than the first dopant concentration (for example, lower than about 2.5·10 16 at / cm 3 ).

[0043] The drift layer 17 has an upper surface 17 a and a lower surface 17 b opposite to each other along the axis Z, wherein the lower surface 17 b of the drift layer 17 is in contact with the upper surface 16 a of the substrate 16 .

[0044] For example, the thickness of the drift layer 17 along the axis Z between the surface 17 a and the surface 17 b is between about 4 μm and about 15 μm, for example equal to about 6.5 μm.

[0045] The device 10 further includes a drain ohmic contact region or layer (not shown, for example made of nickel silicide) that extends and forms an ohmic contact at the bottom surface 16b of the substrate 16. For example, in a manner known per se, the drain ohmic contact region may extend above the lower surface 16b of the substrate 16, or may extend into the substrate 16 so as to be exposed by the substrate 16 at the substrate lower surface 16b.

[0046] The device 10 further comprises a drain metallization 18 extending over the drain ohmic contact region to make direct electrical contact with the substrate 16 and thus form a drain electrical terminal. The drain metallization 18 is made of a conductive material and is formed, for example, of a stack of metal layers such as Ti / NiV / Ag or Ti / NiV / Au.

[0047] The device 10 further includes a plurality of body regions 19 that are accommodated in the drift layer 17 and extend from the upper surface 17 a of the drift layer 17 toward the substrate 16 (without reaching the substrate 16 ).

[0048] In detail, each body region 19 has a respective upper surface 19 a that is exposed by the drift layer 17 and is substantially aligned with the upper surface 17 a of the drift layer 17 along the axis Z.

[0049] The body regions 19 are spaced apart from one another along the axis X by the drift layer 17 and are arranged laterally to one another along the axis X. The body regions 19 each have a main extension parallel to the axis Y.

[0050] The body region 19 has a second conductivity type opposite to the first conductivity type (here, the body region is a P type). The body region 19 has a third dopant concentration (for example, about 3·10 17 at / cm 3 About 3.10 18 at / cm 3 between).

[0051] In particular, two body regions 19 are pre-set for each MOSFET 10 ′, and each body region 19 is shared between two MOSFETs 10 ′ that are consecutive to each other in the MOSFET array, as described in more detail below.

[0052] For each body region 19 , the device 10 further comprises two corresponding source regions 20 , which are accommodated in the body region 19 and extend from an upper surface 19 a of the body region 19 towards the drift layer 17 (without reaching the drift layer).

[0053] In detail, each source region 20 has a respective upper surface 20 a , which is exposed by the body region 19 and is substantially aligned with the upper surface 19 a of the body region along the axis Z.

[0054] The source regions 20 are spaced apart from one another along the axis X by the body region 19 . The source regions 20 each have a main extension parallel to the axis Y.

[0055] The source region 20 has a first conductivity type (here, N-type) and has a fourth dopant concentration greater than the first dopant concentration (eg, about 1·10 19 at / cm 3 About 1.10 21 at / cm 3 between, for example, equal to about 1·10 20 at / cm 3 ).

[0056] In particular, there are two source regions 20 for each body region 19 , and each of these two source regions 20 belongs to a respective one of the two MOSFETs 10 ′ that share the body region 19 under consideration.

[0057] The portion of each body region 19 between the source region 20 and the drift layer 17 along the axis X defines a respective channel region 19 ′ of the MOSFET 10 ′ through which electrical conduction occurs when the MOSFET 10 ′ is appropriately biased.

[0058] The substrate 16, the drift layer 17, the body region 19 and the source region 20 together form the semiconductor body 15 of SiC of the device 10, and the semiconductor body 15 has an upper surface 15a (defined by the upper surface 17a of the drift layer 17, the upper surface 19a of the body region 19 and the upper surface 20a of the source region 20) and a lower surface 15b (defined by the lower surface 16b of the substrate 16) which are opposite to each other along the axis Z.

[0059] The device 10 further includes a corresponding gate structure 21 of each MOSFET 10 ′.

[0060] Each gate structure 21 extends over two respective channel regions 19 ′ which are opposite to each other through the drift layer 17 and are part of two body structures 19 which are successive to each other along the axis X. In other words, each gate structure 21 extends over the channel region 19 ′ of the respective MOSFET 10 ′. The gate structure 21 also has a main extension parallel to the axis Y.

[0061] In particular, each gate structure 21 extends over a respective channel region 19 ′, over a portion of the drift layer 17 interposed along the axis X between these channel regions 19 ′, and possibly over a portion of the respective source region 20 .

[0062] Each gate structure 21 includes a gate insulating layer 22 on the upper surface 15 a of the semiconductor body 15 and a gate region 23 surrounded by the gate insulating layer 22 in the plane XZ.

[0063] The gate insulating layer 22 is made of silicon dioxide (SiO 2 ) is made of an insulating material, and the gate region 23 is made of a conductive material such as metal or doped polysilicon. In this way, the gate region 23 is physically and electrically isolated from the semiconductor body 15 (more specifically, the channel region 19' on which the gate region is stacked) by the gate insulating layer 22.

[0064] The gate region 23 is also electrically connected to a gate metallization (not shown) of the device 10 in a manner known per se to those skilled in the art. The gate metallization defines a gate terminal of the device 10.

[0065] like Figure 1 As shown, each MOSFET 10' having a vertical structure includes a first MOSFET portion 10' a and the second MOSFET portion 10' b The first MOSFET portion 10' a The second MOSFET portion 10′ is defined by the gate structure 21, the source region 20 on the left side of the drift layer 17, the corresponding body region 19 on the left side of the drift layer 17 (specifically, the channel region 19′ on the left side of the drift layer 17), and the drift layer 17 and the substrate 16. b It is defined by the gate structure 21 , the source region 20 on the right side of the drift layer 17 , the corresponding body region 19 on the right side of the drift layer 17 (specifically, the channel region 19 ′ on the right side of the drift layer 17 ), and the drift layer 17 and the substrate 16 .

[0066] Furthermore, the device 10 comprises a respective source ohmic contact region or layer (not shown, for example made of nickel silicide) for each source region 20. The source ohmic contact region extends at the upper surface 20a of the respective source region 20 and forms a respective ohmic contact. For example, in a manner known per se, each source ohmic contact region may extend above the upper surface 20a of the source region 20, or may extend into the source region 20, thereby being exposed by the source region 20 at the upper surface 20a.

[0067] The device 10 further comprises a source metallization 24 extending over the source ohmic contact region to be in direct electrical contact with the source region 20, thereby forming a source electrical terminal. In practice, the source metallization 24 extends over the gate structure 21 and onto a region of the upper surface 15a of the semiconductor body 15 not covered by the gate structure 21, thereby being in direct electrical contact with the source region 20. The source metallization 24 is made of an electrically conductive material and is, for example, formed by a stack of metal layers, such as Ti / AlSiCu or Ni / AlSiCu.

[0068] The device 10 may further include a passivation layer (not shown) extending over the source metallization 24 to protect the source metallization 24 .

[0069] For example, in a manner not shown and known per se, the active area of ​​the device 10 is delimited from the outside in a plane XY (defined by the axes X and Y and substantially parallel to the upper surface 15a of the semiconductor body 15) by an edge termination region or a guard ring which completely surrounds the MOSFET 10' in the plane XY. For example, the edge termination region is a P-type implant region. Optionally, the device 10 may also include an edge insulation layer (not shown) which extends over the upper surface 15a of the semiconductor body 15 to overlap the edge termination region along the axis Z, completely surrounds the MOSFET 10' and laterally delimits the source metallization 24.

[0070] Additionally, device 10 includes one or more doped pocket regions 25 .

[0071] exist Figure 1 In an exemplary and non-limiting embodiment, there are two doped pocket regions 25 for each MOSFET 10′, specifically, for each MOSFET portion 10′ a and 10′ b There are corresponding doping pockets 25. Nevertheless, as better discussed below, the number of doping pockets 25 may vary and may be, for example, higher or lower than previously described (eg, only one doping pocket per MOSFET 10').

[0072] exist Figure 1 In an exemplary and non-limiting embodiment, the doping pocket region 25 has a substantially rectangular cross-section (e.g., a rectangle with rounded corners) in the plane XZ. However, other closed polygonal shapes of the cross-section of the doping pocket region 25 in the plane XZ, such as a trapezoid, a T-shape, a mushroom-like shape, etc., can similarly be considered.

[0073] The doped pocket region 25 is buried in the drift layer 17 and is at least partially aligned with the source region 20 and / or the gate structure 21 of the respective MOSFET 10 ′ along the axis Z. In particular, the doped pocket region 25 extends at a distance from the body region 19 and the upper surface 15 of the semiconductor body 15 .

[0074] In detail, the doped pocket regions 25 are spaced apart from each other along the axis X by the drift layer 17 .

[0075] The doped pocket region 25 may have a main extension parallel to the axis Y. For example, the doped pocket region 25 may have a strip shape parallel to the axis Y, such as Fig. 10A For example, the doped pocket region 25 has a length measured parallel to the axis Y that is approximately equal to the length of the body region 19 measured parallel to the axis Y.

[0076] The doped pocket region 25 has a second conductivity type (here, P type) and has a doped pocket dopant concentration higher than the second dopant concentration of the drift layer 17. For example, the doped pocket region 25 is doped with boron or aluminum.

[0077] In particular, the doping pocket dopant concentration is about 1·10 17 at / cm 3 About 5.10 17 at / cm 3 (ie, between about 10 times and about 50 times the second dopant concentration of the drift layer 17), for example, equal to about 3·10 17 at / cm 3 , so that the doped pocket region 25 can be depleted at the breakdown voltage of the MOSFET 10 ′.

[0078] According to an embodiment, the doping pockets 25 are arranged laterally to each other along the axis X, substantially at the same level along the axis Z. In other words, the doping pockets 25 are arranged one after the other along the axis X, at the same height relative to the substrate 16 .

[0079] Considering that each of the body regions 19 has a minimum distance (or minimum body distance) D from the substrate 16 b , and each of the doping pocket regions 25 has a minimum distance (or minimum doping pocket distance) D from the substrate 16 s , minimum distance D s Below the minimum distance D b .

[0080] In particular, as better described below, the minimum distance D s and the minimum distance D b The ratio between (or the first ratio) D s / D b is between 0% and about 70% (inclusive of the boundaries).

[0081] Considering that each MOSFET 10' has an average width (or average MOSFET width) L along axis X m , and each doping pocket region 25 has a maximum width (or maximum doping pocket width) L along the axis X s , maximum width L s Below average width L m , and in particular, the maximum width L s With average width L m The ratio (or second ratio) L s / L m is between about 15% and about 30% (including the boundary values). For example, the average width L of each MOSFET 10 ′ is mIt is measured between the central axes of the two body regions 19 of the MOSFET 10′ under consideration, each of which is parallel to the axis Z; in other words, the average width is measured parallel to the axis X between two points on the upper surface 19a of the corresponding body region 19, each of which is equidistant from the two source regions 20 present in the corresponding body region 19.

[0082] Furthermore, considering that the doping pocket regions 25 each have a maximum thickness (or maximum doping pocket thickness) S along the axis Z s , maximum thickness S s With the minimum distance D b The ratio between (or the third ratio) S s / D b It may be between about 10% and about 30%, inclusive.

[0083] In more detail, each body region 19 has a lower surface 19b opposite to the upper surface 19a along the axis Z. Furthermore, each doped pocket region 25 has an upper surface 25a and a lower surface 25b opposite to each other along the axis Z, and has a first side surface 25c and a second side surface 25d opposite to each other along the axis X and joined and transverse to the surfaces 25a and 25b. The minimum distance D b is defined between the lower surface 19b of each body region 19 and the upper surface 16a of the substrate 16 along the axis Z. The minimum distance D s The maximum width L is defined between the lower surface 25b of each doped pocket region 25 and the upper surface 16a of the substrate 16 along the axis Z. s The maximum thickness S is defined between the first lateral surface 25a and the second lateral surface 25d of each doping pocket region 25 along the axis X. s It is defined along the axis Z between the upper surface 25 a and the lower surface 25 b of each doping pocket region 25 .

[0084] According to an exemplary and non-limiting embodiment, the minimum distance D b Between about 5.2 μm and about 5.7 μm, the minimum distance D s Between about 0 μm and about 0.5 μm, the average width L m Between about 4.5 μm and about 5 μm, the maximum width L s Between about 0.9 μm and about 1.5 μm, and with a maximum thickness S s Between about 0.5 μm and about 1.2 μm.

[0085] According to an embodiment of the device 10 (eg Figure 1As shown, two doping pocket regions 25 are pre-set for each MOSFET 10′, and each source region 20 is at least partially aligned vertically (i.e., parallel to the axis Z) with a corresponding one of the doping pocket regions 25. The doping pocket region 25 can be vertically aligned with the gate structure 21 of the corresponding MOSFET 10′, or the doping pocket region 25 can be vertically offset relative to it (i.e., vertically misaligned relative to it).

[0086] According to a different embodiment of the device 10 (eg Figure 2 As shown, where there is only one doping pocket region 25 for each MOSFET 10 ′, each gate structure 21 is at least partially vertically aligned with a corresponding one of the doping pocket regions, which in turn may be vertically offset relative to the source region 20 .

[0087] These embodiments may also be combined with each other. For example, according to another embodiment of the device 10 (eg Figure 3 As shown, there are three doping pocket regions 25 for each MOSFET 10′, the gate structure 21 is at least partially vertically aligned with some of the doping pocket regions, some of the doping pocket regions are vertically offset relative to the source region 20, and the source region 20 is at least partially vertically aligned with other doping pocket regions.

[0088] As an alternative to the previously described approach, for example Figure 4 As shown, the doping pocket regions 25 can be arranged laterally to each other along the axis X, but at different levels with respect to each other along the axis Z. In other words, the doping pocket regions 25 can be arranged one after another along the axis X, but at different heights relative to the substrate 16. In this case, there will be different minimum distances D s (exist Figure 4 In the example, the first minimum distance D s1 and the second minimum distance D s2 ), and each of the minimum distances satisfies the ratio D s / D b Describe the condition.

[0089] Furthermore, there may also be a plurality of doping pocket regions 25, which are stacked on top of each other and spaced apart from each other in a direction parallel to the axis Z, such as Figure 5 As shown. In other words, the doping pocket regions 25 may also be at least partially aligned vertically with each other. For example, there may be groups of doping pocket regions 25 lateral to each other along the axis X, and wherein each group comprises two or more corresponding doping pocket regions 25 superimposed on each other parallel to the axis Z. For example, the doping pocket regions 25 superimposed on each other parallel to the axis Z have a corresponding mutual distance D parallel to the axis Z. r, the distance may be, for example, greater than 0.5 μm. This embodiment may be combined with any embodiment described herein.

[0090] In a known manner, during use, by applying a source voltage V S to the source metallization 24 and thus to the source region 20 (eg, a ground reference voltage GND, i.e., at 0V) to bias the device 10, while the drain voltage V D (eg, between 30 V and 1700 V) is applied to the drain metallization 18 and thus to the substrate 16. In other words, the drain-source voltage V DS is applied between the source terminal and the drain terminal of the MOSFET 10'.

[0091] In addition, when the gate region 23 is biased to a voltage greater than the gate threshold voltage V G,th The gate voltage V G When a corresponding flow of charge carriers (here electrons) through the channel region 19' of the MOSFET 10' is generated, the device 10 is in the on state. Conversely, when the gate voltage V applied to the gate region 23 is G Below the gate threshold voltage V G,th And when the generation of charge carrier flow through the channel region 19' of the MOSFET 10' is thereby inhibited, the device 10 is in an inhibition state.

[0092] Therefore, the overall conduction of the device 10 is determined based on all of the MOSFETs 10', and in particular, based on each MOSFET 10' (each corresponding to a respective MOSFET portion 10'). a , 10′ b ) depends on both the electron flow. Therefore, when properly biased, the device 10 generates a drain-source current I between the source terminal and the drain terminal of the MOSFET 10′. DS .

[0093] It has been demonstrated that the doped pocket region 25 reduces the ringing of the device 10, for example, during switching of the MOSFET 10', it also reduces the drain-source voltage V DS and the drain-source current I DS The overshoot amplitude is reduced by 70-80%. It has been confirmed that this beneficial effect is not due to the establishment of PTO in MOSFET 10' and is independent of this phenomenon.

[0094] In fact, the doped pocket region 25 increases the dynamic capacitive coupling of the source terminal to the drain terminal, thus allowing to reduce the drain-source voltage V during switching of the MOSFET 10 ′. DSoscillation.

[0095] In particular, Figure 6A-6F shows that during the dynamic phase, as the drain-source voltage V DS As an example, the behavior of the depletion region 27 of one of the MOSFETs 10' increases. Figure 6A-6F Only a first MOSFET portion 10 ′ of one of the MOSFETs 10 ′ is shown. a , although similar considerations apply to the second MOSFET portion 10′ b And applicable to all MOSFETs 10'.

[0096] like Figure 6A-6F It can be seen that when the drain-source voltage V DS Increase (in which Fig. 6A Corresponding to the drain-source voltage V DS For the minimum value, Fig. 6F Corresponding to the drain-source voltage V DS is the maximum value), the depletion region 27 also expands, which starts from the source region 20 and advances towards the substrate 16. In other words, the depletion region 27 has a lower delimiting surface 27′ (corresponding to the lower boundary of the depletion region 27 along the axis Z, and therefore at the lower boundary of the region of the drift layer 17 where the minority charge carriers (here holes) are greater than the majority charge carriers (here electrons)), and the more the lower delimiting surface 27′ extends towards the substrate 16, the greater the drain-source voltage V DS The more it increases.

[0097] exist Fig. 6A and Figure 6B In the embodiment, the lower delimiting surface 27′ of the depletion region 27 has not yet reached the doped pocket region 25 below, and therefore has no effect on the electric field distribution and hole distribution in the considered MOSFET 10′. In other words, the lower delimiting surface 27′ of the depletion region 27 extends above the doped pocket region 25.

[0098] exist Figure 6C , the depletion region 27 just reaches and contacts the doping pocket region 25. In this case, the lower bounding surface 27′ of the depletion region 27 is immediately below the doping pocket region 25, moving along the axis Z. In other words, the depletion region 27 extends through both the portion of the drift layer 17 located above the doping pocket region 25 and through the doping pocket region. In this case, it has been confirmed that a hole flow having a substantially vertical direction is established between the source region 20 and the doping pocket region 25.

[0099] exist Figure 6D-6FIn the embodiment of the present invention, the depletion region 27 expands more and more below the doping pocket region 25 and toward the substrate 16. In other words, the lower bounding surface 27′ of the depletion region 27 (which is between the doping pocket region 25 and the substrate 16 along the axis Z) separates from the doping pocket region 25 and moves more and more toward the substrate 16. At the same time, the hole flow between the source region 20 and the doping pocket region 25 is enhanced, which increases the electrical coupling between the source region 20 and the doping pocket region 25.

[0100] It has been confirmed that when the depletion region 27 begins to extend through the doped pocket region 25, the drain-source voltage V DS and the drain-source current I DS The rate of change of the drain-source voltage V with time is reduced, while the other electrical and physical parameters of the MOSFET 10 ′ are the same. This results in a decrease in the drain-source voltage V relative to the case where the doped pocket region 25 is not present. DS and the drain-source current I DS Oscillates over time with a smaller maximum amplitude, thus reducing ringing effects.

[0101] Fig. 7A and Figure 7B 1 and 1 , respectively, for one of the MOSFETs 10 ′, when the MOSFET 10 ′ switches from the on state to the off state (indicated as at about t=t*=0.1 μs or less). DS and the drain-source current I DS The respective trends over time. In particular, both one of the MOSFETs 10' and a known MOSFET in which the doped pocket region 25 is not present are shown to compare their respective electrical properties.

[0102] After switching at t = t* = 0.1 μs, there is a transient time interval in which the drain-source voltage V DS and the drain-source current I DS oscillate around their respective mean values ​​in a damped manner and then move towards their respective mean values ​​(at Fig. 7A and Figure 7B In the example, they converge to about 400 V and about 0 A, respectively.

[0103] During this transient time interval, in the presence of the doped pocket region 25, the drain-source voltage V DS and the drain-source current I DS The oscillation amplitude is smaller.

[0104] In addition, it has been confirmed that the presence of the doped pocket region 25 does not significantly change other electrical and operating characteristics of the device 10 (e.g., the breakdown voltage, drain-source on-resistance, body diode current of the MOSFET 10′).

[0105] When the minimum distance D between the doped pocket region 25 and the substrate 16 s is zero (i.e., D s = 0 μm), and thus when the doped pocket region 25 is in contact with the upper surface 16a of the substrate 16, the effectiveness of the ringing reduction is generally maximum.

[0106] In addition, generally speaking, the vertical position of the doped pocket region 25 in the drift layer 17 depends on the rate of change of the recovery current di / dt of the MOSFET 10′ (the MOSFET is designed and electrically controlled to operate at this rate of change). Specifically, the recovery current is the reverse drain-source current that flows in the MOSFET 10′ during the rising stage of the drain-source voltage (where the drain-source current changes sign after the DC current flow) in a transient time interval. The rate of change of the recovery current di / dt also indicates the static or dynamic regime of the MOSFET 10′ (e.g., the static regime for di / dt < 1 A / ns and the dynamic regime for larger di / dt values).

[0107] In other words, the first ratio D s between the minimum distance D b and the minimum distance D s / D b varies (especially its upper limit) depending on the rate of change of the recovery current di / dt of the MOSFET 10′. This is due to the fact that when the rate of change of the recovery current di / dt increases, the doped pocket region 25 will be closer to the substrate 16 to continue to ensure that the dynamic capacitive coupling between the source region 20 and the substrate 16 is sufficient to have high damping for the ringing.

[0108] According to one embodiment, if the MOSFET 10′ is configured to operate at 0 A / ns < di / dt ≤ 1 A / ns, then the first ratio D s / D b is between 0% and about 70% (in particular, between about 50% and about 70%).

[0109] According to one embodiment, if the MOSFET 10′ is configured to operate at 1 A / ns < di / dt ≤ 2 A / ns, then the first ratio D s / D b is between 0% and about 60% (in particular, between about 40% and about 60%).

[0110] According to one embodiment, if the MOSFET 10′ is configured to operate at 2 A / ns < di / dt ≤ 3 A / ns, then the first ratio D s / D b is between 0% and about 50% (specifically, between about 30% and about 50%).

[0111] According to one embodiment, if the MOSFET 10′ is configured to operate at 3 A / ns < di / dt ≤ 4 A / ns, then the first ratio D s / D b is between 0% and about 40% (specifically, between about 20% and about 40%).

[0112] According to one embodiment, if the MOSFET 10′ is configured to operate at 4 A / ns < di / dt ≤ 5 A / ns, then the first ratio D s / D b is between 0% and about 30% (specifically, between about 10% and about 30%).

[0113] According to one embodiment, if the MOSFET 10′ is configured to operate at 5 A / ns < di / dt ≤ 6 A / ns, then the first ratio D s / D b is between 0% and about 20%.

[0114] According to one embodiment, if the MOSFET 10′ is configured to operate at 6 A / ns < di / dt ≤ 7 A / ns, then the first ratio D s / D b is between 0% and about 10%.

[0115] According to one embodiment, if the MOSFET 10′ is configured to operate at di / dt > 7 A / ns, then the first ratio D s / D b is equal to about 0%.

[0116] Figure 8 Shows another embodiment of the device 10. Specifically, Figure 8 the device 10 is a high-power device, i.e., it is designed and configured to operate at a drain-source voltage V, for example, higher than about 1200 V DS thereof.

[0117] In Figure 8 the example of, the device 10 is similar to Figure 1An embodiment in which for each MOSFET 10' there are two doped pocket regions 25 lateral to each other along axis X and at the same level along axis Z. Nevertheless, the device 10 may similarly be based on any of the previously described embodiments, so the subsequent following considerations also apply in a similar manner to the other embodiments.

[0118] In particular, with Figure 1 The entire drift layer 17 has a second dopant concentration different in Figure 8 In the embodiment, the drift layer 17 includes a main drift region 17′ having a first conductivity type (here, N-type) and a second dopant concentration, and a drift buffer region 17″ having a first conductivity type (here, N-type) and a buffer dopant concentration (greater than the second dopant concentration). In other words, in Figure 1 In the embodiment, the drift layer 17 is formed only by the drift main region 17′, while in Figure 8 In the embodiment, the drift layer 17 is formed by a drift main region 17 ′ and a drift buffer region 17 ″.

[0119] Specifically, the buffer dopant concentration of the drift buffer region 17″ is about 25% higher than the second dopant concentration (ie, the sum of the second dopant concentration and about 25% of the second dopant concentration) and about 3·10 16 at / cm 3 For example, it is equal to about 1.3·10 16 at / cm 3 Thus, the buffer dopant concentration is at least about 25% higher than the second dopant concentration.

[0120] The drift buffer region 17 ″ extends over the substrate 16 , and the drift main region 17 ′ extends over the drift buffer region 17 ″. Therefore, along the axis Z, the drift buffer region 17 ″ is interposed between the substrate 16 and the drift main region 17 ′.

[0121] In more detail, the drift buffer zone 17″ has an upper surface 17″a and a lower surface 17″b opposite to each other along the axis Z (which are in contact with the upper surface 16a of the substrate 16 and define the lower surface 17b of the drift layer 17), and the drift main zone 17′ has an upper surface 17′a (which defines the upper surface 17a of the drift layer) and a lower surface 17′b (which are in contact with the upper surface 17″a of the drift buffer zone 17″) opposite to each other along the axis Z.

[0122] The drift buffer zone 17″ has a maximum thickness S along the axis Z. b , the drift main zone 17 ′ has a minimum thickness S along the axis Z d , the minimum thickness is greater than or equal to the maximum thickness S of the drift buffer zone 17″ bIn particular, the drift buffer zone 17 ″ and the drift main zone 17 ′ have a substantially constant thickness S parallel to the axis Z. b and S d For example, the maximum thickness S of the drift buffer zone 17″ b is measured along the axis Z between the upper surface 17"a and the lower surface 17"b of the drift buffer zone 17", and the minimum thickness S of the drift main zone 17' is d It is measured along the axis Z between the body region 19 (in detail, the lower surface 19b of one of the body regions 19) and the lower surface 17'b of the drift main region 17'.

[0123] According to one embodiment, the maximum thickness S of the drift buffer zone 17″ is b The minimum distance D between the body region 19 and the substrate 16 b The ratio between (or the fourth ratio) S b / D b It is between about 30% and about 50% (inclusive), and is for example equal to about 40%.

[0124] The doping pocket region 25 may extend completely into the drift buffer region 17 ″, or completely into the drift main region 17 ′, or partially into the drift buffer region 17 ″ and partially into the drift main region 17 ′.

[0125] In particular, it has been verified that the presence of the drift buffer zone 17 ″ having a higher doping than the drift main zone 17 ′ prevents an active behavior of the MOSFET 10 ′.

[0126] In fact, the drift buffer 17″ increases the recombination rate of minority charge carriers (here holes) due to its higher doping. In other words, the average lifetime of holes in the drift layer 17 is reduced, so that the holes are recombined before reaching the substrate 16 even when the device 10 is operated at high temperatures (for example, above about 170°C), thereby preventing them from suddenly recombining when contacting the upper surface 16a of the substrate 16. Specifically, the drift buffer 17″ prevents the lower defining surface 27′ of the depletion region 27 from reaching the upper surface 16a of the substrate 16 in the static field. Therefore, this avoids the active behavior of the MOSFET 10′.

[0127] Furthermore, it has been confirmed that the presence of the drift buffer region 17″ in the drift layer 17 does not significantly change the operation and other electrical parameters of the device 10 (e.g., the on-resistance and breakdown voltage of the MOSFET 10′). In particular, the buffer dopant concentration and the maximum thickness S of the drift buffer region 17″ are b The value of is selected within the previously described range to keep the on-resistance of MOSFET 10' substantially constant.

[0128] The advantages provided by the present disclosure are evident through an examination of the features disclosed according to the present disclosure.

[0129] The presence of doped pocket region 25 allows for effective reduction of ringing in MOSFET 10 ′ of device 10 during the “recovery” phase of MOSFET 10 ′, without however negatively altering other electrical and physical properties of device 10 .

[0130] Furthermore, this advantage is achieved without reducing the switching speed of the MOSFET 10 ′, without increasing the area of ​​the device 10 , and without adding complex electronic circuitry external to the device 10 .

[0131] Furthermore, the doped pocket region 25 can be formed in the drift layer 17 by implantation of dopant species or "channeling". This allows the device 10 to be manufactured in a simple manner (especially using reference channeling techniques), ensuring accurate control of the size of the doped pocket region 25, and thus ensuring accurate control of the electrical characteristics of the device 10.

[0132] Furthermore, using the drift layer 17 including the drift buffer region 17 ″ and the drift main region 17 ′ prevents the MOSFET 10 ′ of the device 10 from having an active behavior, thereby improving the electrical properties, operation, and reliability of the device 10 .

[0133] Finally, it is obvious that modifications and variations may be made to the present disclosure described and illustrated herein without departing from the scope of the present disclosure as defined in the appended claims.For example, the different embodiments described may be combined with each other to provide further solutions.

[0134] The shape, number and arrangement of the doped pocket regions 25 may vary as previously described, and may be varied within the previously described ranges.

[0135] Furthermore, the foregoing description also applies to the case where the device 10 comprises a single portion 10′ a or 10′ b A single MOSFET 10′ (eg, having only the first MOSFET portion 10′) a ) situation.

[0136] Furthermore, in a manner known per se, the drift layer 17 of the device 10 may include a current spreading layer (CSL) 40, such as Fig. 9 shown.

[0137] In detail, Fig. 9 An embodiment of a device 10 is shown by way of example, and is related to Figure 1 Nevertheless, the CSL 40 may be similarly present in each of the embodiments described herein.

[0138] The CSL 40 extends from the upper surface 15a of the semiconductor body 15 toward the substrate 16 into the drift layer 17 (particularly, into the drift main region 17′) without reaching the substrate 16, so that the body region 19 is accommodated (e.g., completely accommodated) in the CSL 40. In particular, when the drift buffer region 17″ is present, the CSL 40 is located at a certain distance from the substrate 16 and the drift buffer region 17″ along the axis Z.

[0139] For example, along the axis Z and below the body region 19, the CSL 40 has a thickness equal to about 0.1 μm or 0.2 μm. In other words, the CSL 40 has an upper surface 40 a (which forms the upper surface 17 a of the drift layer 17) and a lower surface 40 b opposite to each other along the axis Z; the lower surface 40 b of the CSL 40 extends below the body region 19 along the axis Z and is about 0.1 μm-0.2 μm away from the lower surface 19 b of the body region 19 along the axis Z.

[0140] The CSL 40 has a first conductivity type (here, N-type) and has a CSL dopant concentration higher than the second dopant concentration (e.g., about 1·10 17 at / cm 3 of magnitude).

[0141] As is known, the CSL 40 enhances and homogenizes the diffusion of the charge flow in the drift layer 17 flowing under the gate structure 21 .

[0142] In addition, if Fig. 10A and Fig. 10B As shown, the shape of the doped pocket region 25 in the plane XY may vary.

[0143] In particular, Fig. 10A and Fig. 10B A top view (i.e., parallel to plane XY) of device 10 is shown. For ease of viewing, Fig. 10A and Fig. 10B Only the upper surface 15a of the semiconductor body 15 is shown, and the doped pocket region 25 buried in the semiconductor body 15 is shown in dotted lines; in other words, other elements of the previously described device 10 (e.g., the body region 19, the source region 20, the gate structure 21, etc.) are not shown here so as not to obscure the understanding of the figure, although they are obviously present.

[0144] In detail, Fig. 10A An embodiment of the previously described device 10 is shown in which the doped pocket region 25 has the shape of a stripe, the main extension of which is parallel to the axis Y and the length along the axis Y is substantially equal to the length of the body region 19 along the axis Y. For example, in this figure the doped pocket region has a rectangular shape.

[0145] Nevertheless, for example Fig. 10B As shown, the shape of the doping pocket region 25 parallel to the axis Y may be different.

[0146] For example, the doping pocket region 25 may be discontinuous parallel to the Y axis.

[0147] Specifically, Fig. 10B The doping pocket regions 25 are shown arranged in a matrix or checkerboard pattern parallel to the plane XY. In the matrix, the doping pocket regions 25 can be aligned in columns parallel to the axis Y (e.g. Fig. 10A as shown), or they may be misaligned with each other parallel to the axis Y (for example, the doped pocket regions 25 of a row may be laterally offset relative to the doped pocket regions 25 of two first adjacent rows adjacent to the row under consideration in the matrix, and may be aligned parallel to the axis Y with the doped pocket regions 25 of two rows adjacent to the two first adjacent rows in the matrix).

[0148] These doped pocket regions 25 may have a rectangular shape parallel to the plane XY (eg Fig. 10B As shown), square, circle, hexagon, etc.

[0149] In addition, if Fig.11 As shown, the device 10 may have a drift layer 17 including a drift buffer region 17″ and a drift main region 17′, and alternatively may not have a doped pocket region 25. In this embodiment where the doped pocket region 25 is not present, the device 10 does not have active behavior and can therefore be operated in an optimized manner at high power.

[0150] An electronic device (10) can be summarized as comprising: a semiconductor body (15) of silicon carbide (i.e., SiC), the semiconductor body (15) having an upper surface (15a) and a lower surface (15b) opposite to each other along a first axis (Z), and comprising: a drain substrate (16), the drain substrate (16) extending from the lower surface (15b) of the semiconductor body (15) into the semiconductor body (15) and having a first conductivity type and a first dopant concentration; a drift layer (17), the drift layer (17) extending from the upper surface (15a) of the semiconductor body (15) into the semiconductor body (15) to the drain substrate (16), and having the first conductivity type and a second dopant concentration lower than the first dopant concentration; at least one first body region (19), the at least one first body region (19) extending from the upper surface (15a) of the semiconductor body (15) to the semiconductor body (15). The electronic device (10) comprises a first MOSFET (10′) and a second MOSFET (10′) having a first conductive type opposite to the first conductive type; and at least one first source region (20), the at least one first source region (20) extending from the upper surface (15a) of the semiconductor body (15) into the semiconductor body (15), being accommodated in the first body region (19) to be spaced apart from the drift layer (17), and having the first conductive type. The electronic device (10) further comprises at least one first gate structure (21), the at least one first gate structure (21) extending on the upper surface (15a) of the semiconductor body (15) and being superposed on the first body region (19) along the axis Z to form a first MOSFET portion (10′) of the first MOSFET (10′) with the first source region (20), the first body region (19), the drift layer (17), and the drain substrate (16). a ), wherein the semiconductor body (15) further comprises at least one first doped pocket region (25), the at least one first doped pocket region (25) being buried in the drift layer (17), having a second conductivity type and being at least partially aligned with the first source region (20) and / or with the first gate structure (21) along a first axis (Z).

[0151] The first doping pocket region (25) may have a minimum doping pocket distance (D) from the drain substrate (16) along the first axis (Z). s ), the first body region (19) may have a minimum body distance (D) from the drain substrate (16) along the first axis (Z). b ), minimum doping pocket distance (D s ) and the minimum body distance (D b ) between the first ratio (D s / D b ) can be between 0% and 70% or equal to 0% or 70%.

[0152] If the first MOSFET (10') is configured to operate with a recovery current change rate (di / dt) between 0 A / ns and 1 A / ns or equal to 1 A / ns, the first ratio (D s / D b ) may be between 0% and 70% or may be equal to 0% or 70%; if the first MOSFET (10′) is configured to operate with a recovery current change rate (di / dt) between 1A / ns and 2A / ns or equal to 2A / ns, the first ratio (D s / D b ) may be between 0% and 60% or may be equal to 0% or 60%; if the first MOSFET (10′) is configured to operate with a recovery current change rate (di / dt) between 2A / ns and 3A / ns or equal to 3A / ns, the first ratio (D s / D b ) may be between 0% and 50% or may be equal to 0% or 50%; if the first MOSFET (10′) is configured to operate at a rate of change (di / dt) of the recovery current between 3A / ns and 4A / ns or equal to 4A / ns, the first ratio (Ds / Db) may be between 0% and 40% or may be equal to 0% or 40%; if the first MOSFET (10′) is configured to operate at a rate of change (di / dt) of the recovery current between 4A / ns and 5A / ns or equal to 5A / ns, the first ratio (Ds / Db) may be between 0% and 30% or may be equal to 0% or 30%; if the first MOSFET (10′) is configured to operate at a rate of change (di / dt) of the recovery current between 5A / ns and 5A / ns or equal to 5A / ns, the first ratio (Ds / Db) may be between 0% and 30% or may be equal to 0% or 30%; if the first MOSFET (10′) is configured to operate at a rate of change (di / dt) of the recovery current between 5A / ns and 5A / ns or equal to 5A / ns If the first MOSFET (10′) is configured to operate at a recovery current change rate (di / dt) between 6A / ns and 6A / ns or equal to 6A / ns, the first ratio (Ds / Db) may be between 0% and 20% or may be equal to 0% or 20%; if the first MOSFET (10′) is configured to operate at a recovery current change rate (di / dt) between 6A / ns and 7A / ns or equal to 7A / ns, the first ratio (Ds / Db) may be between 0% and 10% or may be equal to 0% or 10%; and if the first MOSFET (10′) is configured to operate at a recovery current change rate (di / dt) greater than or equal to 7A / ns, the first doped pocket region (25) may be in contact with the drain substrate (16).

[0153] The first doping pocket region (25) may have a maximum doping pocket width (L) along a second axis (X) orthogonal to the first axis (Z). s ), and the first MOSFET (10′) may have an average MOSFET width (L) along the second axis (X) m), where the maximum doping pocket width (L s ) and the average MOSFET width (L m ) between the second ratio (L s / L m ) can be between 15% and 30%, or equal to 15% or 30%.

[0154] The first doping pocket region (25) may have a maximum doping pocket thickness (S) along the first axis (Z). s ), and the maximum doping pocket thickness (S s ) and the minimum body distance (D b ) between the third ratio (S s / D b ) can be between 10% and 30%, or equal to 10% or 30%.

[0155] The doping pocket dopant concentration of the first doping pocket region (25) may be higher than the second dopant concentration of the drift layer (17), and in particular, may be between 1·10 17 at / cm 3 and 5.10 17 at / cm 3 or can be equal to 1·10 17 at / cm 3 or 5.10 17 at / cm 3 .

[0156] The first doped pocket region (25) can be aligned along the first axis (Z): aligned with the first source region (20) and offset relative to the first gate structure (21); or aligned with the first gate structure (21) and offset relative to the first source region (20); or partially aligned with the first source region (20) and partially aligned with the first gate structure (21).

[0157] The semiconductor body (15) may further include: at least one second body region (19), the at least one second body region (19) extending from an upper surface (15a) of the semiconductor body (15) into the semiconductor body (15) and located at a distance from the drain substrate (16), lateral to the first body region (19) orthogonally to the first axis (Z), accommodated in the drift layer (17), and having a second conductivity type; and at least one second source region (20), the at least one second source region extending from the semiconductor body (15) into the semiconductor body (15) and located at a distance from the drain substrate (16), lateral to the first body region (19) orthogonally to the first axis (Z), being accommodated in the drift layer (17), and having a second conductivity type. The upper surface (15a) of the body (15) begins to extend into the semiconductor body (15), is accommodated in the second body region (19) to be spaced apart from the drift layer (17), and has a first conductivity type, wherein the first gate structure (21) is also stacked on the second body region (19) parallel to the first axis (Z), thereby forming a second MOSFET part (10′) of the first MOSFET (10′) together with the second source region (20), the second body region (19), the drift layer (17) and the drain substrate (16). b ), wherein the semiconductor body (15) may further include at least one second doped pocket region (25), which is buried in the drift layer (17), has a second conductivity type and is at least partially aligned with the second source region (20) and / or the first gate structure (21) parallel to the first axis (Z).

[0158] The first doping pocket region (25) and the second doping pocket region may be at least partially aligned with each other orthogonally to the first axis (Z), or may be offset relative to each other orthogonally to the first axis (Z).

[0159] The semiconductor body (15) may further include at least one third source region (20), the at least one third source region extending from the upper surface (15a) of the semiconductor body (15) into the semiconductor body (15), being contained in the second body region (19) to be lateral to the second source region and spaced apart from the drift layer (17) and the second source region (20), and having a first conductivity type. The electronic device (10) may further include at least one second gate structure (21), the at least one second gate structure (21) extending above the upper surface (15a) of the semiconductor body (15), being lateral to the first gate structure (21) and being stacked on the second body region (19) parallel to the first axis (Z), so as to form a first MOSFET portion (10′) corresponding to the second MOSFET (10′) with the third source region (20), the second body region (19), the drift layer (17) and the drain substrate (16). a), wherein the semiconductor body (15) may further include at least one third doped pocket region (25), wherein the at least one third doped pocket region is buried in the drift layer (17), has a second conductivity type, and is at least partially aligned with the third source region (20) and / or the second gate structure (21) parallel to the first axis (Z).

[0160] The semiconductor body (15) may further include at least one further doped pocket region (25) buried in the drift layer (17), having a second conductivity type and being at least partially aligned with the first doped pocket region (25) along the first axis (Z).

[0161] The drift layer (17) may include a drift main region (17′) and a drift buffer region (17″), wherein the drift buffer region (17″) is located between the drift main region (17′) and the drain substrate (16) along a first axis (Z), wherein the drift main region (17′) may have a first conductivity type and the second dopant concentration, and the drift buffer region (17″) may have a first conductivity type and a buffer dopant concentration higher than the second dopant concentration.

[0162] The buffer dopant concentration of the drift buffer region (17″) may be 25% higher than the second dopant concentration. 16 at / cm 3 or equal to 25% or 3·10 higher than the second dopant concentration 16 at / cm 3 .

[0163] The drift buffer region (17″) may have a maximum thickness (S) along the first axis (Z). b ), and the maximum thickness (S b ) and the minimum body distance (D b ) between the fourth ratio (S b / D b ) may be between 30% and 50% or equal to 30% or 50%.

[0164] An apparatus can be generally described as including an electronic device (10).

[0165] The various embodiments described above can be combined to provide additional embodiments. All U.S. patents, U.S. patent application publications, U.S. patent applications, foreign patents, foreign patent applications, and non-patent publications mentioned in this specification and / or listed in the application data sheet are incorporated herein by reference in their entirety. If necessary, various aspects of the embodiments can be modified to adopt the concepts of various patents, applications, and disclosures to provide additional embodiments.

[0166] These and other changes can be made to the embodiments in light of the above detailed description. In general, in the appended claims, the terms used should not be interpreted as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be interpreted as including all possible embodiments and the full range of equivalent forms granted by these claims. Therefore, the claims are not limited by the present disclosure.

Claims

1. An electronic device, characterized in that: include: A semiconductor body of silicon carbide having an upper surface and a lower surface opposite to each other along a first axis, and comprising: a drain substrate extending from the lower surface of the semiconductor body into the semiconductor body and having a first conductivity type and a first dopant concentration; a drift layer extending from an upper surface of the semiconductor body into the semiconductor body and extending to the drain substrate and having a first conductivity type and a second dopant concentration lower than the first dopant concentration; at least one first body region, extending from an upper surface of the semiconductor body into the semiconductor body and at a distance from the drain substrate, is accommodated in the drift layer and has a second conductivity type opposite to the first conductivity type; and at least one first source region extending from an upper surface of the semiconductor body into the semiconductor body, being accommodated in the first body region to be spaced apart from the drift layer, and having a first conductivity type; at least one first gate structure extending on the upper surface of the semiconductor body and superimposed on the first body region along the first axis in such a way as to form a first MOSFET part of the first MOSFET with the first source region, the first body region, the drift layer and the drain substrate, The semiconductor body further comprises at least one first doped pocket region, which is buried in the drift layer, has the second conductivity type and is at least partially aligned with the first source region and / or with the first gate structure along the first axis.

2. The electronic device according to claim 1, characterized in that wherein the first doped pocket region has a minimum doped pocket distance from the drain substrate along the first axis, and the first body region has a minimum body distance from the drain substrate along the first axis, and Wherein a first ratio between the minimum doping pocket distance and the minimum body distance is between 0% and 70% or equal to 0% or 70%.

3. The electronic device according to claim 1, characterized in that: wherein the first doped pocket region has a maximum doped pocket width along a second axis orthogonal to the first axis, and the first MOSFET has an average MOSFET width along the second axis, Wherein a second ratio between the maximum doping pocket width and the average MOSFET width is between 15% and 30%, or equal to 15% or 30%.

4. The electronic device according to claim 2, characterized in that: wherein the first doping pocket region has a maximum doping pocket thickness along a first axis, and Wherein a third ratio between the maximum doping pocket thickness and the minimum body distance is between 10% and 30%, or is equal to 10% or 30%.

5. The electronic device according to claim 1, characterized in that The first doping pocket region is along the first axis: aligned with the first source region and offset relative to the first gate structure; or aligned with the first gate structure and offset relative to the first source region; or Partially aligned with the first source region and partially aligned with the first gate structure.

6. The electronic device according to claim 1, characterized in that The semiconductor body further comprises: at least one second body region extending from the upper surface of the semiconductor body into the semiconductor body and at a distance from the drain substrate, lateral to the first body region orthogonally to the first axis, located at a distance from the first body region orthogonally to the first axis, accommodated in the drift layer, and having a second conductivity type; and at least one second source region extending from the upper surface of the semiconductor body into the semiconductor body, being accommodated in the second body region to be spaced apart from the drift layer, and having the first conductivity type, The first gate structure is also stacked on the second body region in parallel with the first axis in a manner of forming a second MOSFET portion of the first MOSFET together with the second source region, the second body region, the drift layer and the drain substrate, The semiconductor body further comprises at least one second doped pocket region, which is buried in the drift layer, has a second conductivity type, and is at least partially aligned with the second source region and / or the first gate structure parallel to the first axis.

7. The electronic device according to claim 6, characterized in that: The first doping pocket region and the second doping pocket region are at least partially aligned with each other orthogonally to the first axis, or are offset relative to each other orthogonally to the first axis.

8. The electronic device according to claim 6, characterized in that: in, The semiconductor body further comprises at least one third source region, which extends from the upper surface of the semiconductor body into the semiconductor body, is accommodated in the second body region to be laterally spaced apart from the drift layer and the second source region, and has the first conductivity type, The electronic device further comprises at least one second gate structure extending above the upper surface of the semiconductor body, laterally to the first gate structure and superposed on the second body region parallel to the first axis in such a way as to form a corresponding first MOSFET portion of a second MOSFET with the third source region, the second body region, the drift layer and the drain substrate, The semiconductor body further comprises at least one third doped pocket region buried in the drift layer, having the second conductivity type and at least partially aligned with the third source region and / or the second gate structure parallel to the first axis.

9. The electronic device according to claim 1, characterized in that: The semiconductor body further comprises at least one further doped pocket region, which is buried in the drift layer, has a second conductivity type and is at least partially aligned with the first doped pocket region along the first axis.

10. The electronic device according to claim 1, characterized in that The drift layer includes a drift main region and a drift buffer region, wherein the drift buffer region is located between the drift main region and the drain substrate along a first axis. The drift main region has a first conductivity type and the second dopant concentration, and the drift buffer region has a first conductivity type and a buffer dopant concentration higher than the second dopant concentration.

11. The electronic device according to claim 2, characterized in that: in, The drift buffer zone has a maximum thickness along the first axis, and Wherein a fourth ratio between the maximum thickness and the minimum body distance is between 30% and 50%, or is equal to 30% or 50%.

12. An electronic device, characterized in that: include: A semiconductor body of silicon carbide, comprising: a drain substrate having a first conductivity type and a first dopant concentration; a drift layer located above the drain substrate and having a first conductivity type and a second dopant concentration lower than the first dopant concentration; a body region having a top surface coplanar with a top surface of the drift layer, separated from the drain substrate by the drift layer and having a second conductivity type opposite to the first conductivity type; a source region embedded in the body region and separated from the drift layer by the body region, and having a first conductivity type; and a first doped pocket region, having a second conductivity type, embedded in the drift layer and having a top surface lower than a bottom surface of the body region and a bottom surface higher than a top surface of the drain substrate; The gate structure is located directly above at least a portion of the first body region and at least a portion of the first doped pocket region. The gate structure, the source region, the body region, the drift layer and the drain substrate form a MOSFET.

13. The electronic device according to claim 12, characterized in that: The first doped pocket region and the gate structure are aligned on the same vertical axis.

14. The electronic device according to claim 13, characterized in that: The semiconductor body includes a second doped pocket region of a second conductivity type, which is embedded in the drift layer and has a top surface lower than a bottom surface of the body region and a bottom surface higher than a top surface of the drain substrate, and the second doped pocket region directly serves as the body region.

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