Light-emitting substrate and display device

Abstract

The utility model provides a light-emitting substrate and a display device. The light-emitting base plate comprises a substrate base plate; the plurality of bonding pad regions are arranged in an array and are arranged on the substrate; two bonding pad groups which are arranged at an interval in the first direction are arranged in the bonding pad area; a first spacer region is arranged between the two bonding pad groups; the plurality of chips are respectively arranged in the plurality of bonding pad areas; the plurality of chips are arranged in one-to-one correspondence with the plurality of bonding pad areas; wherein the bonding pad group comprises at least one first bonding pad, and the first bonding pad comprises a first sub-bonding pad and a second sub-bonding pad arranged on the periphery of the first sub-bonding pad; solder paste is arranged between the first sub-bonding pad and the corresponding chip pin; the second sub-pad is at least arranged on at least one of the two sides of the first sub-pad along the second direction; the area of the orthographic projection of the chip on the substrate is larger than that of the orthographic projection of the first sub-bonding pad on the substrate; and the orthographic projection of the second sub-bonding pad on the substrate is partially overlapped with the orthographic projection of the chip on the substrate.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a light-emitting substrate and a display device. Background Art

[0002] Micro Light Emitting Diode (Micro LED) or Mini Light Emitting Diode (Mini LED) is a miniaturized light emitting diode (LED) array structure with the characteristic of self-luminescence.

[0003] In the related art, solder balls are easily formed between the pins of the chip and the pads of the substrate during the soldering process. Currently, it is impossible to avoid solder ball defects while ensuring the soldering quality. Utility Model Content

[0004] In view of this, the purpose of the present application is to provide a light-emitting substrate and a display device.

[0005] Based on the above objectives, the present application provides a light-emitting substrate, including:

[0006] substrate substrate;

[0007] A plurality of pad areas arranged in an array are arranged on the substrate; two pad groups arranged at intervals along a first direction are arranged in the pad area; a first interval area is provided between the two pad groups;

[0008] A plurality of chips are respectively arranged in the plurality of pad areas; the plurality of chips are respectively arranged in one-to-one correspondence with the plurality of pad areas;

[0009] Wherein, the pad group includes at least one first pad, the first pad includes a first sub-pad and a second sub-pad arranged outside the first sub-pad; solder paste is arranged between the first sub-pad and the corresponding chip pin; the second sub-pad is at least arranged on at least one side of the first sub-pad along the second direction; wherein the first direction is perpendicular to the second direction, and the second direction and the first direction are parallel to the surface of the substrate; the area of ​​the orthographic projection of the chip on the substrate is greater than the area of ​​the orthographic projection of the first sub-pad on the substrate; the orthographic projection of the second sub-pad on the substrate partially overlaps with the orthographic projection of the chip on the substrate.

[0010] In some embodiments, the light emitting substrate further comprises an insulating layer disposed on the base substrate; at least one first opening area is formed on the insulating layer; the edge of the first opening area defines the pad area;

[0011] Two pin groups are arranged at intervals on one side of the chip close to the substrate; the two pin groups are arranged in one-to-one correspondence with the two pad groups respectively; the pin group includes at least one first pin; the first pin is arranged corresponding to the first pad; solder paste is arranged between the first pin of the chip and the corresponding first pad;

[0012] In the first direction, the size of the second sub-pad area is greater than the minimum distance between the edge of the first sub-pad and the edge of the first pin; and smaller than the maximum distance between the edge of the first sub-pad and the edge of the first pin;

[0013] In the second direction, a size of the second sub-pad area is larger than a minimum distance between an edge of the first sub-pad and an edge of the chip, and smaller than a minimum distance between an edge of the first sub-pad and an edge of the insulating layer.

[0014] In some embodiments, the pad group includes a first pad, in which two second sub-pads are provided and are respectively provided at two sides of the first sub-pad along the second direction.

[0015] In some embodiments, the pad group includes at least two first pads spaced apart in a second direction; in the pad group: a second spacing area is arranged between the two first pads; in the first pad, the second sub-pad is arranged on a side of the first sub-pad close to another pad group in the two pad groups and away from another first pad in the pad group.

[0016] In some embodiments, in the two pad groups, at least one of the first pads in at least one pad group further includes a third sub-pad disposed at the periphery of the first sub-pad; the third sub-pad is disposed on a side of the first sub-pad close to the second spacing area and away from the first spacing area;

[0017] In the first direction, the size of the third sub-pad area is larger than the minimum distance between the edge of the first sub-pad and the edge of the chip, and smaller than the minimum distance between the edge of the first sub-pad and the edge of the insulating layer;

[0018] In the second direction, a size of the third sub-pad area is larger than a minimum distance between an edge of the first sub-pad and an edge of the lead, and smaller than a maximum distance between an edge of the first sub-pad and an edge of the lead.

[0019] In some of the embodiments, in the first direction, the size of the third sub-pad area is greater than 150um and less than 250um; in the second direction, the size of the third sub-pad area is greater than 20um and less than 30um.

[0020] In some embodiments, the second sub-pad further includes a first extension portion, and the first extension portion is disposed on a side of the second sub-pad close to the first spacing area;

[0021] In the second direction, the size of the first extension portion is the same as that of the second sub-pad; the minimum distance between the two first extension portions respectively arranged on both sides of the first spacing region along the first direction is greater than 100um.

[0022] In some embodiments, the second sub-pad further includes a first extension portion, and the first extension portion is disposed on a side of the second sub-pad close to the first spacing region and away from the second spacing region; and / or

[0023] The third sub-pad further includes a second extending portion, and the second extending portion is disposed on a side of the third sub-pad close to the second spacing region and away from the first spacing region.

[0024] In some embodiments, in the second direction, the size of the first extension portion is the same as the size of the second sub-pad; the minimum distance between the two first extension portions respectively arranged on both sides of the first spacing region along the first direction is greater than 100um; and / or

[0025] In the first direction, the size of the second extension portion is the same as that of the third sub-pad; the minimum distance between the two second extension portions respectively arranged on both sides of the second spacing region along the second direction in the second direction is greater than 100um.

[0026] In some embodiments, the pad group further includes at least one second pad disposed in the second spacing area, and a third spacing area is provided between the second pad and the first pad; the second sub-pad is disposed on a side of the first sub-pad close to the first spacing area and away from the third spacing area;

[0027] Wherein, in the first direction, the size of the second sub-pad area is smaller than the maximum distance between the edge of the first sub-pad and the edge of the corresponding first pin;

[0028] In the second direction, a size of the second sub-pad area is larger than a minimum distance between an edge of the first sub-pad and an edge of the chip, and smaller than a minimum distance between an edge of the first sub-pad and an edge of the insulating layer.

[0029] In some embodiments, the pad group further includes a fourth sub-pad; in the first pad, the fourth sub-pad is arranged between the first sub-pad and the second sub-pad; and / or, in the second pad, the fourth sub-pad is arranged on a side of the second pad close to the first spacing area;

[0030] Among them, in the first direction, the size of the fourth sub-pad is larger than the size of the second sub-pad; in the second direction, the size of the fourth sub-pad is larger than the size of the first sub-pad and smaller than the sum of the sizes of the second sub-pad and the first sub-pad.

[0031] In some embodiments, on the side close to the first spacing area, in the first direction, the minimum distance from the edge of the first pad to the edge of the corresponding first pin is greater than 200um; and in the two pad groups, the minimum distance between the two first pads respectively arranged on both sides of the first spacing area along the first direction is greater than 100um; and / or

[0032] On the side away from the first spacing area, in the first direction, the minimum distance from the edge of the first pad to the edge of the corresponding first lead is greater than 200 um.

[0033] In some embodiments, the pad group includes a first pad group and a second pad group spaced apart in a first direction;

[0034] The first pad group is arranged at one side of the pad group close to the first spacing area, and includes two first pads spaced apart along the second direction; in the first pad group: a second spacing area is arranged between the two first pads, and two second sub-pads are arranged in the first pad, respectively arranged at two sides of the first sub-pad along the first direction;

[0035] Wherein, the second pad group is arranged at a side of the pad group away from the first spacing area, and the second pad group includes two first pads spaced apart in the second direction and at least one third pad arranged between the two first pads; in the second pad group: in the first pad, the second sub-pad is arranged at a side of the first sub-pad close to the first pad group and away from the third pad;

[0036] Wherein, in the first direction, the size of the second sub-pad area is smaller than the maximum distance between the edge of the first sub-pad and the edge of the corresponding first pin;

[0037] In the second direction, a size of the second sub-pad area is larger than a minimum distance between an edge of the first sub-pad and an edge of the chip, and smaller than a minimum distance between an edge of the first sub-pad and an edge of the insulating layer.

[0038] In some embodiments, a fifth sub-pad is further included; in the second pad group: in the first pad, the fifth sub-pad area is arranged on a side of the first sub-pad away from the first pad group and close to the third pad; and / or in the third pad, the fifth sub-pad is arranged in two, which are respectively arranged on both sides of the end of the third pad away from the first pad group in the second direction;

[0039] Wherein, in the first direction, the size of the fifth sub-pad area is larger than the minimum distance between the edge of the first sub-pad and the edge of the chip, and smaller than the minimum distance between the edge of the first sub-pad and the edge of the insulating layer;

[0040] In the second direction, the size of the fifth sub-pad area is greater than the minimum distance between the edge of the first sub-pad and the edge of the lead; and / or

[0041] In the first pad group and the second pad group, the size of the second sub-pad in the first direction differs by 20%; and / or the size of the second sub-pad in the first direction differs by 20% from the size of the fifth sub-pad in the second direction.

[0042] In some embodiments, in the first direction, the size of the fifth sub-pad is greater than 150um and less than 200um, and in the second direction, the size of the fifth sub-pad is greater than 20um and less than 30um; and / or

[0043] In the first pad group, in the first direction, the minimum distance from the edge of the first pad to the edge of the corresponding first pin is greater than 35um and less than 45um; and in the two pad groups, the minimum distance between the two first pads respectively arranged on both sides of the first spacing area along the first direction is greater than 100um; and / or

[0044] In the second pad group, in the first direction, the minimum distance from the edge of the first pad / third pad to the edge of the corresponding pin is greater than 35um and less than 45um; and in the pad group, in the first direction, the minimum distance between the edges of the first pad in the first pad group and the second pad in the second pad group that are close to each other is greater than 100um.

[0045] In some embodiments, in the first direction, the size of the second sub-pad area is greater than 20um and less than 30um; in the second direction, the size of the second sub-pad area is greater than 150um and less than 250um.

[0046] The present application provides a display device, comprising a light-emitting substrate as described in any of the preceding items. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] In order to more clearly illustrate the technical solutions in the present application or related technologies, the drawings required for use in the embodiments or related technical descriptions are briefly introduced below. Obviously, the drawings described below are only embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0048] Figure 1 This is a schematic structural diagram of a light-emitting substrate according to an embodiment of the present application;

[0049] Figure 2 This is a schematic diagram of the LED pad structure of an embodiment of the present application;

[0050] Figure 3 This is a schematic diagram of the LED pad extension structure of an embodiment of the present application;

[0051] Figure 4 This is a schematic diagram of the LED pad extension structure of an embodiment of the present application;

[0052] Figure 5 This is a schematic diagram of the 1CH IC pad structure of an embodiment of the present application;

[0053] Figure 6 This is a schematic diagram of the 1CH IC pad extension structure of an embodiment of the present application;

[0054] Figure 7 This is a schematic diagram of the 1CH IC pad extension structure of an embodiment of the present application;

[0055] Figure 8 This is a schematic diagram of the Package 4CH IC pad structure of an embodiment of the present application;

[0056] Fig. 9 This is a schematic diagram of the extended structure of the Package 4CH IC pad of an embodiment of the present application;

[0057] Fig.10 This is a schematic diagram of the extended structure of the Package 4CH IC pad of an embodiment of the present application;

[0058] Fig.11 This is a schematic diagram of the 8CH IC pad structure of an embodiment of the present application;

[0059] Fig.12 This is a schematic diagram of the 8CH IC pad extension structure of an embodiment of the present application;

[0060] Fig.13 This is a schematic diagram of the 8CH IC pad extension structure of an embodiment of the present application;

[0061] Fig.14 Schematic diagram of the structure of a display device according to an embodiment of the present application. DETAILED DESCRIPTION

[0062] In order to make the objectives, technical solutions and advantages of the present application more clearly understood, the present application is further described in detail below in combination with specific embodiments and with reference to the accompanying drawings.

[0063] It should be noted that, unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present application should be the usual meanings understood by people with ordinary skills in the field to which the present application belongs. The "first", "second" and similar words used in the embodiments of the present application do not represent any order, quantity or importance, but are only used to distinguish different components. "Including" or "comprising" and similar words mean that the elements or objects appearing in front of the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0064] In the related art, in the MLED backlight substrate, the chip (LED / IC) is soldered to the substrate pad through solder paste, so that the pins of the chip and the pads of the substrate are soldered to achieve conduction. Usually, the solder paste can be made onto the substrate pad by steel screen printing, and the amount of solder paste on the pad can determine the welding quality. Among them, if there is too much solder paste on the pad, it will cause short circuits between pads and poor solder beads, and if there is too little solder paste on the pad, it will cause excessive welding voids and too thin welding layers, and poor cracking of the welding layer. Therefore, it is necessary to control the amount of solder paste within an appropriate range to achieve good conduction.

[0065] In some technologies, the amount of solder paste on the pad is adjusted by the stencil thickness and stencil opening of the printed stencil. Generally, the smaller the stencil thickness, the smaller the stencil opening rate, and the less solder paste will be printed on the pad. However, the reduction in stencil thickness will lead to a decrease in stencil life. In addition, the reduction in stencil thickness will also lead to too small an opening rate, which will lead to poor printing. Therefore, the stencil needs to be controlled at an appropriate thickness to control the amount of solder paste within an appropriate range.

[0066] In MLED backlight substrates, due to the small size of MLED chips (about 100μm), the pad size and pad gap are about 100μm, so the amount of solder paste is more stringent. In addition, due to the small pad size, only No. 6 powder can be used for solder paste. The metal particle size of No. 6 powder is small (15μm) and it is easy to oxidize. The oxidized solder beads are squeezed out during the soldering process and attached to the chip after reflow soldering to form solder beads.

[0067] Therefore, in the related art, the problem of defective solder beads cannot be avoided while ensuring the soldering quality of the chip pins and the substrate pads through the solder paste.

[0068] Based on this, an embodiment of the present application provides a light-emitting substrate, which extends the solder pad outward on the inner side of the solder pad. The extended solder pad can weld oxidized solder beads, thereby solving the problem of defective solder beads to a certain extent.

[0069] Figure 1 A schematic structural diagram of an exemplary light-emitting substrate according to an embodiment of the present application is shown.

[0070] like Figure 1 to Figure 5 As shown, the light-emitting substrate of the embodiment of the present application may include:

[0071] Base substrate 10;

[0072] A plurality of pad areas arranged in an array are arranged on the base substrate 10; the pad area is provided with two pad groups 51 arranged at intervals along a first direction Y; a first spacing area 512 (for example, 512a, 512b, 512c or 512d) is provided between the two pad groups 51;

[0073] A plurality of chips 70 are respectively arranged in the plurality of pad areas; the plurality of chips 70 are respectively arranged in one-to-one correspondence with the plurality of pad areas;

[0074] The pad group 51 includes at least one first pad (e.g., a first pad 511a, a first pad 511b, a first pad 511c, or a first pad 511d), the first pad (e.g., a first pad 511a, a first pad 511b, a first pad 511c, or a first pad 511d) including a first sub-pad (e.g., a first sub-pad 5111a, a first sub-pad 5111b, a first sub-pad 5111c, or a first sub-pad 5111d) and a pad disposed on the first pad. A second sub-pad (e.g., second sub-pad 5112a, second sub-pad 5112b, second sub-pad 5112c, or second sub-pad 5112d) is disposed around a sub-pad (e.g., first sub-pad 5111a, first sub-pad 5111b, first sub-pad 5111c, or first sub-pad 5111d); solder paste 72 is disposed between the first sub-pad and the pin of the corresponding chip; the second sub-pad (e.g., second sub-pad 5112a, second sub-pad 5112b, second sub-pad 5112c, or second sub-pad 5112d) is disposed around a second sub-pad (e.g., second sub-pad 5111a, second sub-pad 5111b, second sub-pad 5111c, or first sub-pad 5111d); solder paste 72 is disposed between the first sub-pad and the pin of the corresponding chip; The pad 5112c or the second sub-pad 5112d) is at least arranged on at least one side of the first sub-pad (for example, the first sub-pad 5111a, the first sub-pad 5111b, the first sub-pad 5111c or the first sub-pad 5111d) along the second direction X; wherein the first direction Y is perpendicular to the second direction X, and the second direction X and the first direction Y are parallel to the surface of the base substrate 10; the chip 70 is on the positive projection of the base substrate 10 The area is larger than the area of ​​the orthographic projection of the first sub-pad (for example, the first sub-pad 5111a, the first sub-pad 5111b, the first sub-pad 5111c or the first sub-pad 5111d) on the base substrate 10; the orthographic projection of the second sub-pad (for example, the second sub-pad 5112a, the second sub-pad 5112b, the second sub-pad 5112c or the second sub-pad 5112d) on the base substrate 10 partially overlaps with the orthographic projection of the chip 70 on the base substrate 10.

[0075] The light-emitting substrate provided in the embodiment of the present application is provided with a first pad (for example, a first pad 511a, a first pad 511b, a first pad 511c or a first pad 511d) including a first sub-pad (for example, a first sub-pad 5111a, a first sub-pad 5111b, a first sub-pad 5111c or a first sub-pad 5111d) and a second sub-pad (for example, a second sub-pad 5112) provided at the periphery of the first sub-pad (for example, the first sub-pad 5111a, the first sub-pad 5111b, the first sub-pad 5111c or the first sub-pad 5111d). a, second sub-pad 5112b, second sub-pad 5112c or second sub-pad 5112d); the second sub-pad (for example, second sub-pad 5112a, second sub-pad 5112b, second sub-pad 5112c or second sub-pad 5112d) is at least arranged in the first spacing area 512 (for example, 512a, 512b, 512c or 512d) between the two pad groups 51 near the first sub-pad (for example, first sub-pad 5111a, first sub-pad 5111b, first sub-pad 5111c or first sub-pad 5111d). ) on one side; the area of ​​the orthographic projection of the chip 70 on the base substrate 10 is larger than the area of ​​the orthographic projection of the first sub-pad (for example, the first sub-pad 5111a, the first sub-pad 5111b, the first sub-pad 5111c or the first sub-pad 5111d) on the base substrate 10; the orthographic projection of the second sub-pad (for example, the second sub-pad 5112a, the second sub-pad 5112b, the second sub-pad 5112c or the second sub-pad 5112d) on the base substrate 10 partially overlaps with the orthographic projection of the chip 70 on the base substrate 10, which can It is possible to extend the first solder pad (e.g., first solder pad 511a, first solder pad 511b, first solder pad 511c or first solder pad 511d) outward on the inner side of the first solder pad (e.g., first solder pad 511a, first solder pad 511b, first solder pad 511c or first solder pad 511d) to form a second sub-pad (e.g., second sub-pad 5112a, second sub-pad 5112b, second sub-pad 5112c or second sub-pad 5112d), and the extended solder pad (i.e., the second sub-pad) can weld oxidized tin beads, thereby solving the problem of defective tin beads to a certain extent.

[0076] Generally, the base substrate 10 can play a supporting role. The base substrate 10 can be a glass substrate, or an Al substrate, a FR4 substrate, a BT substrate, or a FPC substrate.

[0077] In some embodiments, a first insulating layer 20 may be disposed on the base substrate 10, and a routing layer 30 may be disposed on a side of the first insulating layer 20 away from the base substrate 10. Generally, the routing layer 30 may play a role in signal transmission. The routing layer 30 may be a copper routing layer.

[0078] In some embodiments, a second insulating layer 40 may be provided on the side of the routing layer 30 away from the base substrate 10. At least one first opening area is provided on the second insulating layer 40; the edge of the first opening area defines the pad area. That is, the backplane further includes an insulating layer (e.g., a second insulating layer 40), which is provided on the base substrate 10; at least one first opening area is provided on the insulating layer (e.g., the second insulating layer 40); the edge of the first opening area defines the pad area.

[0079] In some embodiments, a reflective layer 60 may be provided on a side of the second insulating layer 40 away from the base substrate 10, the reflective layer 60 may have a second opening, and the orthographic projection of the second opening on the base substrate 10 may cover the orthographic projection of the first opening on the base substrate 10. Generally, the reflective layer 60 may reflect light, and the material of the reflective layer 60 may be ink.

[0080] In some embodiments, the chip 70 may include an IC and an LED, where the LED is a light emitting unit and the IC is a control unit. Figure 2 to Figure 5 FIG. 2 shows a schematic diagram of the structure of a pad in an embodiment. Figure 2-Figure 5 As shown, two pin groups 71 may be arranged at intervals on one side of the chip 70 close to the base substrate 10; the two pin groups 71 may be arranged one-to-one corresponding to the two pad groups 51. That is, the pin groups 71 are arranged at intervals in the first direction Y, and there is a spacing area between the two pin groups 71. The pin group 71 includes at least one first pin (for example, a first pin 711a, a first pin 711b, a first pin 711c or a first pin 711d); the first pin (for example, a first pin 711a, a first pin 711b, a first pin 711c or a first pin 711d) is arranged correspondingly to the first solder pad (for example, a first solder pad 511a, a first solder pad 511b, a first solder pad 511c or a first solder pad 511d), and solder paste 72 is arranged between the first pin 711 (for example, a first pin 711a, a first pin 711b, a first pin 711c or a first pin 711d) and the corresponding first solder pad (for example, a first solder pad 511a, a first solder pad 511b, a first solder pad 511c or a first solder pad 511d).

[0081] Typically, the area of ​​the orthographic projection of the reflective layer 60 / the second insulating layer 40 on the base substrate 10 may be greater than the area of ​​the orthographic projection of the first sub-pad (e.g., the first sub-pad 5111a, the first sub-pad 5111b, the first sub-pad 5111c, or the first sub-pad 5111d) in the first pad (e.g., the first pad 511a, the first pad 511b, the first pad 511c, or the first pad 511d) on the base substrate 10. The area of ​​the orthographic projection of the chip 70 on the base substrate 10 is greater than the area of ​​the orthographic projection of the corresponding first sub-pad (e.g., the first sub-pad 5111a, the first pad 511b, the first pad 511c, or the first pad 511d) on the base substrate 10. The area of ​​the orthographic projection of the first sub-pad (e.g., first sub-pad 5111a, first sub-pad 5111b, first sub-pad 5111c or first sub-pad 5111d) in the first pad (e.g., first pad 511a, first pad 511b, first pad 511c or first pad 511d) on the substrate 10 is larger than the area of ​​the orthographic projection of the pin corresponding to the chip 70 on the substrate 10.

[0082] In some embodiments, the pad extension size relative to the pin (e.g., a1, a2, c2, a3, c3, d3, f4) at the location where there is a risk of short circuit (i.e., the gap between the pad and the adjacent pad) can be designed to be 10 μm, or can be designed to be 25 um (e.g., b4, c4, d4) and 100 um (e.g., a4), and the pad extension size relative to the pin (e.g., b1, c1, d1, b2, d2, b3, e3) at the location where there is no risk of short circuit can be set to 20 μm (e.g., a4), or can be designed to be 200 μm (e.g., e4). In this way, the problem of short circuit between pads caused by too small pad gap can be avoided, and the problem of blocking the reflective layer 60 due to the pad being too large beyond the shape of the chip 70 at the non-pad gap, which can affect the light effect due to the inability to reflect light.

[0083] In some embodiments, in the first direction Y, the size of the second sub-pad (e.g., the second sub-pad 5112a, the second sub-pad 5112b, the second sub-pad 5112c, or the second sub-pad 5112d) area is greater than the minimum distance between the edge of the first sub-pad (e.g., the first sub-pad 5111a, the first sub-pad 5111b, the first sub-pad 5111c, or the first sub-pad 5111d) and the edge of the corresponding first pin (e.g., the first pin 711a, the first pin 711b, the first pin 711c, or the first pin 711d); and is less than the maximum distance between the edge of the first sub-pad (e.g., the first sub-pad 5111a, the first sub-pad 5111b, the first sub-pad 5111c, or the first sub-pad 5111d) and the edge of the first pin (e.g., the first pin 711a, the first pin 711b, the first pin 711c, or the first pin 711d).

[0084] In the second direction X, the size of the second sub-pad (e.g., the second sub-pad 5112a, the second sub-pad 5112b, the second sub-pad 5112c, or the second sub-pad 5112d) is larger than the minimum distance between the edge of the first sub-pad (e.g., the first sub-pad 5111a, the first sub-pad 5111b, the first sub-pad 5111c, or the first sub-pad 5111d) and the edge of the chip 70, and smaller than the minimum distance between the edge of the first sub-pad (e.g., the first sub-pad 5111a, the first sub-pad 5111b, the first sub-pad 5111c, or the first sub-pad 5111d) and the edge of the second insulating layer 40 / reflective layer 60. In this way, the solder bead defect can be improved and the light effect can be avoided from being affected.

[0085] In some embodiments, when the gap between the first pads (e.g., the first pad 511a, the first pad 511b, the first pad 511c, or the first pad 511d) in the two pad groups 51 is relatively limited, in the first direction Y, the size of the second sub-pad (e.g., the second sub-pad 5112a, the second sub-pad 5112b, the second sub-pad 5112c, or the second sub-pad 5112d) is greater than 20um and less than 30um, for example, about 25μm; in the second direction X, the size of the second sub-pad (e.g., the second sub-pad 5112a, the second sub-pad 5112b, the second sub-pad 5112c, or the second sub-pad 5112d) is greater than 150um and less than 250um, for example, about 200μm. In this way, the solder ball reacts with the pad without forming a solder bead, and the extension area of ​​the pad is small, which has the advantages of not affecting the light effect and effectively improving the defective solder bead.

[0086] In some embodiments, such as Figure 2As shown, the pad group 51 may include a first pad 511a, for example, a P-pole pad or an N-pole pad. Correspondingly, the pin group 71 of the chip 70 may include a first pin 711a, corresponding to a P-pole pin or an N-pole pin. Among them, the edge of the first pad 511a on one side close to the first spacing area 512a, and the distance a1 to the edge of the first pin 711a on the side close to the first pad 511a can be 10um, that is, the gap between the pad and the pin at the position of the first pad 511a on the pad gap side can be 10um. The distances b1, c1 and d1 of the remaining edges of the first pad 511a to the edge of the first pin 711a on the side close to the first pad 511a can be 20um respectively.

[0087] In some embodiments, such as Figure 6 As shown, in the first pad 511a, the number of the second sub-pads 5112a can be two, and they can be respectively arranged on both sides of the first sub-pad 5111a along the second direction X. In this way, the solder beads on both sides of the first sub-pad 5111a along the second direction X can be welded simultaneously.

[0088] In some embodiments, such as Figure 7 As shown, when the spacing between the first pads 511a in the two pad groups 51 is large, the second sub-pad 5112a can also extend to the side close to the first spacing area 512a to form a first extension area 5113a, and the width L1 of the first extension area 5113a (that is, the size in the second direction X) remains unchanged and can be the same as the width L1 of the second sub-pad 5112a. It should be understood that the same width can include that the width L1 of the first extension area 5113a (that is, the size in the second direction X) can also have a certain difference with the width L1 of the second sub-pad 5112a, for example, the difference is within ±20%. The length of the first extension area 5113a (that is, the size in the first direction Y) can be h1, so as to better improve the solder bead defect. Among them, in the first direction Y, the size of the first extension portion 5113a can meet the minimum distance g1 between the two first pads 511a in the two pad groups 51, that is, the minimum distance between the two second sub-pads 5112a in the two pad groups 51 respectively arranged on both sides of the first spacing area 512a along the first direction Y can meet the insulation requirements of the pads.

[0089] In some embodiments, the dimension w1 of the second sub-pad 5112a in the first direction Y may be greater than 20um and less than 30um, for example, about 25um; the dimension L1 of the second sub-pad 5112a in the second direction X may be greater than 150um and less than 250um, for example, about 200um.

[0090] In some embodiments, in the two pad groups 51, the minimum distance g1 between the two edges of the two second sub-pads 5112a respectively disposed on both sides of the first direction Y and respectively close to the first spacing area 512a is greater than 100um. That is, the size of the first extension portion 5113a satisfies that the minimum distance g1 between the two first extension portions 5113a respectively disposed on both sides of the first spacing area 512a along the first direction Y is greater than 100um.

[0091] In some embodiments, such as Figure 3 and Figure 4 As shown, the pad group 51 includes at least two first pads (eg, first pad 511b or first pad 511c) spaced apart in the second direction X. Figure 3 As shown, the pad group 51 includes two first pads 511b spaced apart in the second direction X. In the pad group 51: a second spacing area 513b is provided between the two first pads 511b. The first pad 511b may have a size a2 and a size c2 of 10um at a location close to the first spacing area 512b and close to the second spacing area 513b relative to the corresponding first pin 711b in the corresponding chip 70. The first pad 511b may have a size b2 and a size d2 of 25um at a location far from the first spacing area 512b and far from the second spacing area 513b relative to the corresponding first pin 711b in the corresponding chip 70.

[0092] like Figure 3 and Figure 8 As shown, in the pad group 51: in the first pad 511b, the second sub-pad 5112b is arranged on a side of the first sub-pad 5111b close to the first spacing area 512b and away from the second spacing area 513b. That is, in the pad group 51: in the first pad 511b, the second sub-pad 5112b is arranged on a side of the first sub-pad 5111b close to the other pad group of the two pad groups and away from the other first pad 5111b in the pad group 51.

[0093] In some embodiments, in the first direction Y, the size w2 of the second sub-pad 5112b is greater than the minimum distance between the edge of the first sub-pad 5111b and the edge of the first lead 711b; and less than the maximum distance between the edge of the first sub-pad 5111b and the edge of the first lead 711b;

[0094] In the second direction X, the size L2 of the second sub-pad 5112 area is larger than the minimum distance between the edge of the first sub-pad 5111b and the edge of the chip 70, and smaller than the minimum distance between the edge of the first sub-pad 511b and the edge of the second insulating layer 40.

[0095] In some embodiments, the dimension w2 of the second sub-pad 5112b in the first direction Y may be greater than 20um and less than 30um, for example, about 25um; the dimension L2 of the second sub-pad 5112b in the second direction X may be greater than 150um and less than 250um, for example, about 200um.

[0096] In some embodiments, the first pad 511b may further include a third sub-pad 5114 disposed at the periphery of the first sub-pad; the third sub-pad 5114 is disposed at a side of the first sub-pad 5111b close to the second spacing area 513b and away from the first spacing area 512b;

[0097] In the first direction Y, a size L2 of the third sub-pad area 5114 is larger than a minimum distance between an edge of the first sub-pad 5111b and an edge of the chip 70, and smaller than a minimum distance between an edge of the first sub-pad 5111b and an edge of the reflective layer 60;

[0098] In the second direction X, the size w2 of the third sub-pad area is greater than the minimum distance between the edge of the first sub-pad 5111b and the edge of the first pin 711b; and less than the maximum distance between the edge of the first sub-pad 5111b and the edge of the first pin 711b.

[0099] In this way, solder bead defects can be better avoided.

[0100] It can be understood that, in the two pad groups 51, at least one pad group 51 has one first pad 511b including the third sub-pad 5114. That is, in the two pad groups 51, only one first pad 511b may include the third sub-pad 5114, or each pad group 51 may have one first pad 511b including the third sub-pad 5114, or only one pad group 51 may have two first pads 511b including the third sub-pad 5114, while the other pad group 51 does not have the first pad 511b including the third sub-pad 5114. Alternatively, in each pad group 51, both first pads 511b may include the third sub-pad 5114.

[0101] In some embodiments, when the gap between the first pads 511b in the two pad groups 51 is relatively small, in the first direction Y, the size L2 of the third sub-pad 5114 is greater than 150um and less than 250um, for example, about 200μm; in the second direction X, the size w2 of the third sub-pad 5114 is greater than 20um and less than 30um, for example, about 25μm. In this way, the solder ball reacts with the pad without forming a solder bead, and the extension area of ​​the pad is small, which has the advantages of not affecting the light effect and effectively improving the solder bead defect.

[0102] In some embodiments, such as Fig. 9 As shown, when the spacing between the first pads 511b in the two pad groups 51 is large, the second sub-pad 5112b can also extend to the side close to the first spacing area 512b to form a first extension portion 5113b. In the second direction X, the size L2 (i.e., width) of the first extension portion 5113b remains unchanged and can be the same as the size L2 (i.e., width) of the second sub-pad 5112b. It should be understood that the same width can include a certain difference between the width L1 of the first extension area 5113b (i.e., the size in the second direction X) and the width L1 of the second sub-pad 5112b, for example, within ±20%. The length of the first extension portion 5113b (i.e., the size in the first direction Y) can be h2 to better improve solder bead defects. Among them, in the first direction Y, the minimum distance g2 between the two first pads 511b in the two pad groups 51, that is, the minimum distance between the two first extension portions 5113b in the two pad groups 51 respectively arranged on both sides of the first direction Y, meets the insulation requirements of the pads.

[0103] In some embodiments, in the two pad groups 51, the minimum distance between the two first extensions 5113b respectively arranged on both sides of the first direction Y, that is, the distance g2 between the two edges respectively close to the first spacing area 512b is greater than 100um. That is, in the first direction Y, the size h2 of the first extension 5113b satisfies that the minimum distance between the two first extensions 5113b respectively arranged on both sides of the first spacing area 512b along the first direction Y is greater than 100um.

[0104] In some of the embodiments, the third sub-pad 5114 may further include a second extension portion 5115, and the second extension portion 5115 is disposed on a side of the third sub-pad 5114 close to the second spacing region 513b and away from the first spacing region 512b.

[0105] In the first direction Y, the size of the second extension portion 5115 may be the same as the size of the third sub-pad 5114. It should be understood that the same width may include that in the first direction Y, the size of the second extension portion 5115 and the size of the third sub-pad 5114 have a certain difference, for example, within ±20%. In the second direction X, the size h2 of the second extension portion 5115 satisfies that the minimum distance g2 of the two second extension portions 5115 respectively arranged on both sides of the second spacing area 513b along the second direction X is greater than 100um, so as to meet the insulation requirements. That is, in the two pad groups 51, the minimum distance of the two second extension portions 5115 in the second direction X in the second direction may be greater than 100um.

[0106] Back to Figure 4 , in some embodiments, such as Figure 4 As shown, the pad group 51 includes two first pads 511c (i.e., first sub-pads 5111c) spaced apart in the second direction X, and the pad group 51 also includes at least one second pad 517 disposed in the second spacing area 513c. In the pad group 51, a third spacing area 514 is provided between the second pad 517 and the first pad 511c. Generally, in the design of such chip 70, in the first direction Y, on the side close to the first spacing area 512c, the edge distance a3 of the pad (e.g., the first pad 511c or the second pad 517) to the edge of the corresponding pin (e.g., the first pin 711c) may be 100um, and on the side away from the first spacing area 512c, the edge distance e3 of the pad (e.g., the first pad 511c or the second pad 517) to the edge of the corresponding pin (e.g., the first pin 711c) may be 200um. In the second direction X, the distance between the edge of the solder pad and the edge of the corresponding pin on the same side can be 100um. For example, the edge distance b3 from the edge of the solder pad (for example, the first solder pad 511c) on the side away from the third spacing area to the edge of the corresponding pin (for example, the first pin 711c) can be 100um, the edge distance c3 from the edge of the solder pad (for example, the first solder pad 511c) on the side close to the third spacing area 514 to the corresponding pin (for example, the first pin 711c) can be 100um, and the edge distance d3 from the edge of the solder pad (for example, the second solder pad 517) on the side close to the third spacing area 514 to the corresponding pin (for example, the second pin) can be 100um.

[0107] In some embodiments, such as Figure 4 and Fig.10As shown, the second sub-pad 5112c is disposed on a side of the first sub-pad 5111c close to the first spacing region 512c and away from the third spacing region 514. In each first pad 511c, one second sub-pad 5112c may be provided.

[0108] Wherein, in the first direction Y, the size w3 of the second sub-pad 5112c is smaller than the maximum distance between the edge of the first sub-pad 5111c and the edge of the corresponding first pin 711c;

[0109] In the second direction X, the size L3 of the second sub-pad 5112 is larger than the minimum distance between the edge of the first sub-pad 5111c and the edge of the chip 70, and smaller than the minimum distance between the edge of the first sub-pad 5111c and the edge of the insulating layer.

[0110] In some embodiments, in the first direction Y, the size w3 of the second sub-pad 5112c is greater than 20um and less than 30um, for example, about 25μm; in the second direction X, the size L3 of the second sub-pad 5112c is greater than 150um and less than 250um, for example, about 200μm. In this way, the solder ball reacts with the pad without forming a solder bead, and the extension area of ​​the pad is small, which has the advantages of not affecting the light effect and effectively improving the defective solder bead.

[0111] In some embodiments, such as Fig.11 As shown, a fourth sub-pad 515 may also be included. In the pad group 51: a second spacing area is provided between the two first pads 511c; in the first pad 511, the fourth sub-pad 515 is provided between the first sub-pad 5111c and the second sub-pad 5112c; in the second pad 517, the fourth sub-pad 515 is provided on a side of the second pad 517 close to the first spacing area 512.

[0112] Among them, in the first direction Y, the size a5 of the fourth sub-pad 515 is larger than the size of the second sub-pad 5112c; in the second direction X, the size L5 of the fourth sub-pad 515 is larger than the size of the first sub-pad and smaller than the sum of the sizes of the second sub-pad 5112c and the first sub-pad.

[0113] In some embodiments, such as Fig.11As shown, the pad group 51 may further include a sixth sub-pad; in the first pad 511c, the sixth sub-pad is disposed on a side of the first sub-pad away from the first spacing area 512c. In the second pad, the sixth sub-pad is disposed on a side of the second pad away from the first spacing area 512c.

[0114] In which, in the second direction X, the size of the sixth sub-pad is the same as the size of the first sub-pad 5111c; in the first direction Y, the minimum distance from the edge of the sixth sub-pad to the edge of the first sub-pad is less than or equal to the minimum distance from the edge of the first sub-pad away from the first spacing area 512c to the edge of the corresponding first pin 711c.

[0115] In some embodiments, in the first direction Y, the size a5 of the fourth sub-pad 515 satisfies that the sum of the size of the second sub-pad 5112c and the size of the fourth sub-pad 515, and the minimum distance from the edge of the first sub-pad to the edge of the corresponding first pin 711c, is greater than 200um; and in the two pad groups 51, the minimum distance between the two second sub-pads 5112c respectively arranged on both sides of the first spacing area 512c along the first direction Y is greater than 100um. That is, on the side close to the first spacing area 512c, in the first direction Y, the minimum distance g3 from the edge of the first pad 511c to the edge of the corresponding first pin 711c is greater than 200um; and in the two pad groups 51, the minimum distance between the two first pads 511c respectively arranged on both sides of the first spacing area 512c along the first direction Y is greater than 100um. In the second direction X, the size of the fourth sub-pad 515 can be greater than 25um and less than 200um.

[0116] In some embodiments, the size of the sixth sub-pad satisfies that, in the first direction Y, the minimum distance from the edge of the sixth sub-pad (that is, the edge of the second pad) to the edge of the corresponding first lead 711c is greater than 200um. That is, on the side away from the first spacing area 512c, in the first direction Y, the minimum distance L5 from the edge of the first pad 511c to the edge of the corresponding first lead 711c is greater than 200um.

[0117] Back to Figure 5 In some embodiments, the pad group 51 may include a first pad group 52 and a second pad group 53 spaced apart in the first direction Y; wherein a fourth spacing area is provided between the first pad group 52 and the second pad group 53.

[0118] The first pad group 52 is arranged on one side of the pad group 51 close to the first spacing area 512d, and includes two first pads 511d spaced apart along the second direction X; in the first pad group 52, a second spacing area 513d is arranged between the two first pads 511d. In the first direction Y, the distance f4 from the edge of the pad in the first pad 511d to the corresponding first pin 711d is 10um. Fig.12 As shown, in the first pad group 52, the second sub-pad 5112d in the first pad 511d is set to two, which are respectively arranged on the side of the first sub-pad 5111d away from the second spacing area 513d and close to the fourth spacing area; and the side of the first sub-pad 5111d away from the second spacing area 513d and close to the first spacing area 512d, that is, respectively arranged on both sides of the first sub-pad 5111d along the first direction Y.

[0119] The second pad group 53 is arranged on the side of the pad group 51 away from the first spacing area 512d, and the second pad group 53 includes two first pads 511d spaced apart in the second direction X and at least one third pad 519 arranged between the two first pads 511d. In the second pad group 53: in the first direction Y, on the side close to the fourth spacing area, the minimum distance a4 / f4 between the edge of the first sub-pad 5111d in the first pad 511d and the edge of the corresponding first lead 711d is 10um. In the second direction X, on the side close to the second spacing area 513d, the minimum distance c4 between the edge of the first sub-pad 5111d in the first pad 511d and the edge of the corresponding first lead 711d is 10um. In the second direction X, on the side away from the second spacing area 513d, the minimum distance b4 between the edge of the first sub-pad 5111d in the first pad 511d and the edge of the corresponding first lead 711d is 20um. In the second direction X, the minimum distance d4 from the edge of the pad in the third pad 519 to the edge of the corresponding pin is 10um. In the second direction X, on the side away from the fourth spacing area, the minimum distance e4 from the edge of the pad in the third pad 519 to the edge of the corresponding pin is 20um. In the first pad 511d, the second sub-pad 5112d is arranged on a side of the first sub-pad 5111d close to the first pad group 52 and away from the third pad 519.

[0120] In some embodiments, such as Fig.12 As shown, in the first direction Y, the size w4 of the second sub-pad 5112d is smaller than the maximum distance between the edge of the first sub-pad 5111d and the edge of the corresponding first pin 711d;

[0121] In the second direction X, a size L4 of the second sub-pad 5112d is larger than a minimum distance between an edge of the first sub-pad 5111d and an edge of the chip 70, and smaller than a minimum distance between an edge of the first sub-pad 5111d and an edge of the insulating layer.

[0122] In some embodiments, in the first direction Y, the size of the second sub-pad 5112d area is greater than 20um and less than 30um, for example, about 25μm; in the second direction X, the size of the second sub-pad 5112d area is greater than 150um and less than 250um, for example, about 200μm. In this way, the solder ball reacts with the pad without forming a solder bead, and the extension area of ​​the pad is small, which has the advantages of not affecting the light effect and effectively improving the defective solder bead.

[0123] In some of these embodiments, continue to rely on Fig.12 and Fig.13 , further comprising a fifth sub-pad 518. In the second pad group 53: in the first pad 511d, the fifth sub-pad 518 is arranged on a side of the first sub-pad 5111d away from the first pad group 52 and close to the third pad 519; and / or in the third pad 519, two fifth sub-pads 518 are arranged, respectively arranged on both sides of an end of the third pad 519 away from the first pad group 52 in the second direction X;

[0124] Wherein, in the first direction Y, the size L5 of the fifth sub-pad 518 is larger than the minimum distance between the edge of the first sub-pad 5111d and the edge of the chip 70, and smaller than the minimum distance between the edge of the first sub-pad 5111d and the edge of the insulating layer;

[0125] In the second direction X, a size w5 of the fifth sub-pad 518 is greater than a minimum distance between an edge of the first sub-pad 5111d and an edge of the lead.

[0126] In some embodiments, in the first direction Y, the size of the fifth sub-pad 518 is greater than 150um and less than 250um, for example, about 200um. In the second direction X, the size of the fifth sub-pad 518 is greater than 20um and less than 30um, for example, about 25um.

[0127] In some embodiments, in the first pad group 52 and the second pad group 53, the sizes of the second sub-pads 5112d in the first direction Y may be the same, and may differ by about 20%. The size of the second sub-pad 5112d in the first direction Y and the size of the fifth sub-pad 518 in the second direction X may differ by 20%. In this way, different pad spacings can be accommodated.

[0128] In some embodiments, such as Fig.13 , a seventh sub-pad is further arranged between the first sub-pad 5111d and the second sub-pad 5112d, the size of the seventh sub-pad in the first direction Y is 25um to 35um, and in the first direction Y, the minimum distance between the first pad group 52 and the second pad group 53 is greater than 100um; and / or the minimum distance between the two pad groups 51 is greater than 100um; the size of the seventh sub-pad in the second direction X is the same as the size of the first sub-pad 5111d. That is, in the first pad group 52, in the first direction Y, the minimum distance from the edge of the first pad 511d to the edge of the corresponding first pin 711d is greater than 35um and less than 45um; and in the two pad groups 51, the minimum distance between the two first pads 511d respectively arranged on both sides of the first spacing area 512d along the first direction Y is greater than 100um. In the second pad group 53, in the first direction Y, the minimum distance from the edge of the first pad 511d / the third pad 519 to the edge of the corresponding pin is greater than 35um and less than 45um; and in the pad group 51, in the first direction Y, the minimum distance between the edges of the first pad 511d in the first pad group 52 and the second pad in the second pad group 53 that are close to each other is greater than 100um.

[0129] In some embodiments, an encapsulation layer 80 may be further included, and the encapsulation layer 80 may be disposed on a side of the chip 70 away from the substrate 10. The encapsulation layer 80 may be an OC protective layer. The encapsulation layer 80 may play a role in adjusting the light shape and isolating water and oxygen, and the material may be a lens or flat glue.

[0130] In some embodiments, a support column 93 may be further included, and the support column 93 is arranged on a side of the reflective layer 60 away from the base substrate 10. There may be at least one support column 93. The support column 93 may be fixed to the base substrate by glue.

[0131] In some embodiments, a printed circuit board (PCB 91 ), a connector or a flexible printed circuit (FPC) 92 may also be included. The signal is controlled by the PCB 91 , connected through the connector or the FPC, and transmitted through the routing layer 30 .

[0132] Based on the same inventive concept, corresponding to any of the above-mentioned embodiment methods, the present application also provides a display device.

[0133] refer to Fig.14 The display device comprises: a light-emitting substrate as described in any of the previous embodiments, and also comprises a diffusion plate 12, a diffusion sheet 13, an organic protective layer 14 and a frame glue 15 which are sequentially arranged on the light-emitting substrate.

[0134] The diffuser plate 12 and the diffuser sheet 13 can be used to eliminate lamp shadows and improve the uniformity of the picture. The diffuser sheet 13 can be a multi-layer structure. The support column 93 can support the diffuser plate and the diffuser sheet to obtain a certain light mixing distance and eliminate lamp shadows. The organic protective layer 14 can adjust the light shape and isolate water and oxygen. The material can be Lens or flat glue. The organic protective layer 14 can be a multi-layer structure.

[0135] In some of the embodiments, the display device may be various display products such as a mobile phone, a tablet computer, etc.

[0136] The device of the above embodiment includes the corresponding light-emitting substrate in any of the above embodiments, and has the beneficial effects of the corresponding light-emitting substrate embodiment, which will not be described in detail here.

[0137] Those skilled in the art should understand that the discussion of any of the above embodiments is merely illustrative and is not intended to imply that the scope of the present application (including the claims) is limited to these examples. In line with the concept of the present application, the technical features in the above embodiments or different embodiments may be combined, the steps may be implemented in any order, and there are many other variations of the different aspects of the embodiments of the present application as described above, which are not provided in detail for the sake of simplicity.

[0138] In addition, to simplify the description and discussion, and in order not to make the embodiments of the present application difficult to understand, the known power supply / ground connection with the integrated circuit (IC) chip and other components may or may not be shown in the provided drawings. In addition, the device can be shown in the form of a block diagram to avoid making the embodiments of the present application difficult to understand, and this also takes into account the fact that the details of the implementation of these block diagram devices are highly dependent on the platform to be implemented in the embodiments of the present application (that is, these details should be fully within the scope of understanding of those skilled in the art). In the case of elaborating specific details (e.g., circuits) to describe exemplary embodiments of the present application, it is obvious to those skilled in the art that the embodiments of the present application can be implemented without these specific details or when these specific details are changed. Therefore, these descriptions should be considered to be illustrative rather than restrictive.

[0139] Although the present application has been described in conjunction with specific embodiments of the present application, many replacements, modifications and variations of these embodiments will be apparent to those skilled in the art from the foregoing description. For example, other memory architectures (e.g., dynamic RAM (DRAM)) may use the embodiments discussed.

[0140] The embodiments of the present application are intended to cover all such substitutions, modifications and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the embodiments of the present application should be included in the scope of protection of the present application.

Claims

1. A light-emitting substrate, characterized in that: include: substrate substrate; A plurality of pad areas arranged in an array are arranged on the substrate; Two pad groups spaced apart along a first direction are arranged in the pad area; a first spacing area is provided between the two pad groups; A plurality of chips are respectively arranged in the plurality of pad areas; the plurality of chips are respectively arranged in one-to-one correspondence with the plurality of pad areas; Wherein, the pad group includes at least one first pad, the first pad includes a first sub-pad and a second sub-pad arranged outside the first sub-pad; solder paste is arranged between the first sub-pad and the corresponding chip pin; the second sub-pad is at least arranged on at least one side of the first sub-pad along the second direction; wherein the first direction is perpendicular to the second direction, and the second direction and the first direction are parallel to the surface of the substrate; the area of ​​the orthographic projection of the chip on the substrate is greater than the area of ​​the orthographic projection of the first sub-pad on the substrate; the orthographic projection of the second sub-pad on the substrate partially overlaps with the orthographic projection of the chip on the substrate.

2. The light-emitting substrate according to claim 1, characterized in that: The light-emitting substrate further comprises an insulating layer, which is disposed on the base substrate; at least one first opening area is formed on the insulating layer; the edge of the first opening area defines the pad area; Two pin groups are arranged at intervals on one side of the chip close to the substrate; the two pin groups are arranged in one-to-one correspondence with the two pad groups respectively; the pin group includes at least one first pin; the first pin is arranged corresponding to the first pad; solder paste is arranged between the first pin of the chip and the corresponding first pad; In the first direction, the size of the second sub-pad is greater than the minimum distance between the edge of the first sub-pad and the edge of the first pin; and smaller than the maximum distance between the edge of the first sub-pad and the edge of the first pin; In the second direction, a size of the second sub-pad is larger than a minimum distance between an edge of the first sub-pad and an edge of the chip, and smaller than a minimum distance between an edge of the first sub-pad and an edge of the insulating layer.

3. The light-emitting substrate according to claim 1, characterized in that: The pad group includes a first pad, in which two second sub-pads are provided and are respectively provided at two sides of the first sub-pad along the second direction.

4. The light-emitting substrate according to claim 2, characterized in that: The pad group includes at least two first pads spaced apart in a second direction; in the pad group: a second spacing area is arranged between the two first pads; in the first pad, the second sub-pad is arranged on a side of the first sub-pad close to another pad group in the two pad groups and away from another first pad in the pad group.

5. The light-emitting substrate according to claim 4, characterized in that: In the two pad groups, at least one of the first pads in at least one pad group further includes a third sub-pad disposed at the periphery of the first sub-pad; the third sub-pad is disposed on a side of the first sub-pad close to the second spacing area and away from the first spacing area; In the first direction, the size of the third sub-pad is larger than the minimum distance between the edge of the first sub-pad and the edge of the chip, and smaller than the minimum distance between the edge of the first sub-pad and the edge of the insulating layer; In the second direction, a size of the third sub-pad is larger than a minimum distance between an edge of the first sub-pad and an edge of the lead, and smaller than a maximum distance between an edge of the first sub-pad and an edge of the lead.

6. The light-emitting substrate according to claim 5, characterized in that: In the first direction, the size of the third sub-pad is greater than 150um and less than 250um; in the second direction, the size of the third sub-pad is greater than 20um and less than 30um.

7. The light-emitting substrate according to claim 3, characterized in that: The second sub-pad further includes a first extension portion, and the first extension portion is arranged on a side of the second sub-pad close to the first spacing area; In the second direction, the size of the first extension portion is the same as that of the second sub-pad; the minimum distance between the two first extension portions respectively arranged on both sides of the first spacing region along the first direction is greater than 100um.

8. The light-emitting substrate according to claim 5, characterized in that: The second sub-pad further includes a first extension portion, and the first extension portion is arranged on a side of the second sub-pad close to the first spacing area and away from the second spacing area; and / or The third sub-pad further includes a second extending portion, and the second extending portion is disposed on a side of the third sub-pad close to the second spacing region and away from the first spacing region.

9. The light-emitting substrate according to claim 8, characterized in that: In the second direction, the size of the first extension portion is the same as the size of the second sub-pad; the minimum distance between the two first extension portions respectively arranged on both sides of the first spacing region along the first direction is greater than 100um; and / or In the first direction, the size of the second extension portion is the same as that of the third sub-pad; the minimum distance between the two second extension portions respectively arranged on both sides of the second spacing region along the second direction in the second direction is greater than 100um.

10. The light emitting substrate according to claim 4, characterized in that: The pad group further includes at least one second pad disposed in the second spacing area, and a third spacing area is provided between the second pad and the first pad; the second sub-pad is disposed on a side of the first sub-pad close to the first spacing area and away from the third spacing area; Wherein, in the first direction, the size of the second sub-pad is smaller than the maximum distance between the edge of the first sub-pad and the edge of the corresponding first pin; In the second direction, a size of the second sub-pad is larger than a minimum distance between an edge of the first sub-pad and an edge of the chip, and smaller than a minimum distance between an edge of the first sub-pad and an edge of the insulating layer.

11. The light emitting substrate according to claim 10, characterized in that: The pad group further includes a fourth sub-pad; in the first pad, the fourth sub-pad is arranged between the first sub-pad and the second sub-pad; and / or, in the second pad, the fourth sub-pad is arranged on a side of the second pad close to the first spacing area; Among them, in the first direction, the size of the fourth sub-pad is larger than the size of the second sub-pad; in the second direction, the size of the fourth sub-pad is larger than the size of the first sub-pad and smaller than the sum of the sizes of the second sub-pad and the first sub-pad.

12. The light emitting substrate according to claim 11, characterized in that: On the side close to the first spacing area, in the first direction, the minimum distance between the edge of the first pad and the edge of the corresponding first pin is greater than 200um; and in the two pad groups, the minimum distance between the two first pads respectively arranged on both sides of the first spacing area along the first direction is greater than 100um; and / or On the side away from the first spacing area, in the first direction, the minimum distance from the edge of the first pad to the edge of the corresponding first lead is greater than 200 um.

13. The light-emitting substrate according to claim 2, characterized in that: The pad group includes a first pad group and a second pad group spaced apart in a first direction; The first pad group is arranged at one side of the pad group close to the first spacing area, and includes two first pads spaced apart along the second direction; in the first pad group: a second spacing area is arranged between the two first pads, and two second sub-pads are arranged in the first pad, respectively arranged at two sides of the first sub-pad along the first direction; Wherein, the second pad group is arranged on a side of the pad group away from the first spacing area, and the second pad group includes two first pads spaced apart in the second direction and at least one third pad arranged between the two first pads; in the second pad group: in the first pad, the second sub-pad is arranged on a side of the first sub-pad close to the first pad group and away from the third pad; Wherein, in the first direction, the size of the second sub-pad is smaller than the maximum distance between the edge of the first sub-pad and the edge of the corresponding first pin; In the second direction, a size of the second sub-pad is larger than a minimum distance between an edge of the first sub-pad and an edge of the chip, and smaller than a minimum distance between an edge of the first sub-pad and an edge of the insulating layer.

14. The light emitting substrate according to claim 13, characterized in that: Also includes a fifth sub-pad; in the second pad group: in the first pad, the fifth sub-pad is arranged on a side of the first sub-pad away from the first pad group and close to the third pad; and / or in the third pad, the fifth sub-pad is arranged in two, respectively arranged on both sides of the end of the third pad away from the first pad group in the second direction; Wherein, in the first direction, the size of the fifth sub-pad is larger than the minimum distance between the edge of the first sub-pad and the edge of the chip, and smaller than the minimum distance between the edge of the first sub-pad and the edge of the insulating layer; In the second direction, the size of the fifth sub-pad is greater than the minimum distance between the edge of the first sub-pad and the edge of the lead; and / or In the first pad group and the second pad group, the size of the second sub-pad in the first direction differs by 20%; and / or the size of the second sub-pad in the first direction differs by 20% from the size of the fifth sub-pad in the second direction.

15. The light emitting substrate according to claim 14, characterized in that: In the first direction, the size of the fifth sub-pad is greater than 150um and less than 200um, and in the second direction, the size of the fifth sub-pad is greater than 20um and less than 30um; and / or In the first pad group, in the first direction, the minimum distance from the edge of the first pad to the edge of the corresponding first pin is greater than 35um and less than 45um; and in the two pad groups, the minimum distance between the two first pads respectively arranged on both sides of the first spacing area along the first direction is greater than 100um; and / or In the second pad group, in the first direction, the minimum distance from the edge of the first pad / third pad to the edge of the corresponding pin is greater than 35um and less than 45um; and in the pad group, in the first direction, the minimum distance between the edges of the first pad in the first pad group and the second pad in the second pad group that are close to each other is greater than 100um.

16. The light-emitting substrate according to any one of claims 1 to 15, characterized in that: In the first direction, the size of the second sub-pad is greater than 20um and less than 30um; in the second direction, the size of the second sub-pad is greater than 150um and less than 250um.

17. A display device, characterized in that: It comprises the light-emitting substrate as described in any one of claims 1-16.

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