A vertical cavity surface emitting laser

Abstract

The utility model discloses a vertical cavity surface emitting laser, comprising a first DBR layer, an active layer, an oxide layer and a second DBR layer stacked on a substrate in sequence, and also comprising a current expansion layer, the current expansion layer being located between the active layer and the oxide layer. The utility model reduces the current density at the location of the quantum well, improves the reliability of the device, and maintains the advantage of a high transmission rate at the same time.

Description

Technical Field

[0001] The utility model relates to the field of optoelectronic technology, in particular to a vertical cavity surface emitting laser. Background Art

[0002] Vertical-Cavity Surface-Emitting Laser (VCSEL) is a semiconductor laser that emits laser light perpendicular to the top surface, which is different from edge-emitting lasers that are generally made by cutting independent chips and emit laser light from the edge. VCSEL has the advantages of small threshold current, circular spot, low cost, high modulation rate, and easy two-dimensional integration. It plays an important role in short-distance data communication applications.

[0003] like Figure 1 As shown, the structure of a general VCSEL includes a substrate 11, an N-type DBR layer 12, an active layer 13, an oxide layer 14, a P-type DBR layer 15, an N-electrode 16, and a P-electrode 17. The N-type DBR layer 12, the active layer 13, the oxide layer 14, and the P-type DBR layer 15 are sequentially stacked on the substrate 11, the N-electrode 16 is located on the back side of the substrate 11, and the P-electrode 17 is located on the P-type DBR layer 15.

[0004] At present, the oxidation aperture of high-speed VCSEL is generally 5um-8um. Generally, the smaller the oxidation aperture, the smaller the photon volume and the higher the transmission rate. Figure 2 As shown, the current passes through the aperture of the oxide layer 14 and directly reaches the location of the quantum well of the active layer 13, so that the working current density of the active layer 13 increases, resulting in a shortened device life. Utility Model Content

[0005] The technical problem to be solved by the utility model is to provide a vertical cavity surface emitting laser, reduce the current density at the location of the quantum well, improve the reliability of the device, and at the same time maintain the advantage of high transmission rate.

[0006] In order to solve the above technical problems, the technical solution of the utility model is:

[0007] A vertical cavity surface emitting laser comprises a first DBR layer, an active layer, an oxide layer and a second DBR layer which are sequentially stacked on a substrate, and also comprises a current spreading layer which is located between the active layer and the oxide layer.

[0008] Furthermore, the material of the current spreading layer is AlGaAs or GaAs.

[0009] Furthermore, the current diffusion layer is P-type doped.

[0010] Furthermore, the thickness of the current spreading layer is (1 / 4+m*1 / 2)λ, λ is the lasing wavelength, and m=1, 2, 3, 4.

[0011] Further, the range of λ is 800-1000 nm.

[0012] Furthermore, it also includes a first SCH layer and a second SCH layer, wherein the first SCH layer and the first DBR layer have the same doping type, and the second SCH layer and the second DBR layer have the same doping type; the first SCH layer is located between the first DBR layer and the active layer, and the second SCH layer is located between the active layer and the oxide layer.

[0013] Furthermore, the substrate is n-type GaAs, the doping types of the first SCH layer and the first DBR layer are N-type, the current spreading layer is P-type, and the doping types of the second SCH layer and the second DBR layer are P-type.

[0014] Furthermore, the active layer comprises 3-5 quantum wells, the material of the potential wells is InGaAs, and the material of the potential barriers is one of GaAs, AlGaAs, GaAsP or AlGaAsP.

[0015] Furthermore, the oxide layer includes a first oxide layer and a second oxide layer, and the oxide pore diameter of the first oxide layer is smaller than the oxide pore diameter of the second oxide layer.

[0016] Furthermore, it also includes a first electrode and a second electrode, wherein the first electrode is located on the back side of the substrate, and the second electrode is located on the second DBR layer.

[0017] After adopting the above scheme, since the p-type current expansion layer of the utility model is located between the p-type SCH and the oxide layer, the current is restricted by the oxide layer and then diffuses rapidly in the p-type current expansion layer. Compared with the existing high-speed VCSEL structure, the current density reaching the quantum well active region is reduced by introducing the p-type current expansion layer, which greatly improves the working life of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 It is a schematic diagram of the prior art;

[0019] Figure 2 yes Figure 1 Schematic diagram of current expansion at A in the middle;

[0020] Figure 3 This is a schematic diagram of the utility model Figure 1 ;

[0021] Figure 4 yes Figure 3 Schematic diagram of current expansion at point B in the figure

[0022] Figure 5 This is a schematic diagram of the utility model Figure 2 ;

[0023] Figure 6 This is a schematic diagram of the utility model Figure 3 .

[0024] Description of symbols

[0025] Substrate 11 N-type DBR layer 12 Active layer 13 Oxide layer 14 P-type DBR layer 15

[0026] N electrode 16 P electrode 17

[0027] Substrate 1 First DBR layer 2 Active layer 3 Oxide layer 4 First oxide layer 41

[0028] Second oxide layer 42 Second DBR layer 5 First SCH layer 7 Second SCH layer 8

[0029] First electrode 91 Second electrode 92 DETAILED DESCRIPTION

[0030] The present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that if the terms "upper", "lower", "inner", "outer" and other positions or positional relationships are based on the positions or positional relationships shown in the accompanying drawings, or the positions or positional relationships in which the product of the application is usually placed when in use, they are only for the convenience of description and cannot be understood as limitations on the present invention. The technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0031] The utility model discloses a vertical cavity surface emitting laser. Figure 5 As shown, the first embodiment of the utility model includes a first DBR layer 2, an active layer 3, an oxide layer 4 and a second DBR layer 5 stacked in sequence on a substrate 1, and also includes a current spreading layer 6, which is located between the active layer 3 and the oxide layer 4.

[0032] Furthermore, the material of the current spreading layer 6 is AlGaAs or GaAs.

[0033] Further, the thickness of the current spreading layer 6 is (1 / 4+m*1 / 2)λ, λ is the optical thickness, m is a positive integer, m=1, 2, 3, 4, and the range of λ is 800-1000 nm.

[0034] Furthermore, the active layer comprises 3-5 quantum wells, the material of the potential wells is InGaAs, and the material of the potential barriers is one of GaAs, AlGaAs, GaAsP or AlGaAsP.

[0035] like Figure 4As shown, compared with the existing high-speed VCSEL structure, by introducing the p-type current spreading layer 6, the current spreads to both sides along the current spreading layer 6, the current density reaching the quantum well active layer 3 is reduced, and the working life of the device is greatly improved.

[0036] like Figure 6 As shown, it is a second embodiment of the utility model, including a first DBR layer 2, an active layer 3, an oxide layer 4 and a second DBR layer 5 stacked in sequence on a substrate 1, and also including a current spreading layer 6, the current spreading layer 6 is located between the active layer 3 and the oxide layer 4, the oxide layer 4 includes a first oxide layer 41 and a second oxide layer 42, and the oxide pore diameter of the first oxide layer 41 is smaller than the oxide pore diameter of the second oxide layer 42.

[0037] Furthermore, the aperture of the first oxide layer 41 is 3 μm-5 μm. By reducing the oxide aperture, the photon volume is reduced and the modulation rate is improved. In combination with the current expansion layer 6, the device can maintain a lower current density at a smaller aperture, avoiding the reliability problem caused by reducing the aperture.

[0038] Furthermore, the multiple oxide layers are used to further reduce capacitance. In this embodiment, the number of the first oxide layer 41 is one, and the number of the second oxide layers 42 is four.

[0039] Furthermore, the pore size of the second oxide layer 42 is 8 μm-15 μm, which can reduce the capacitance without increasing the resistance too much.

[0040] like Figure 3 As shown, the third embodiment of the utility model is a vertical cavity surface emitting laser, including a first DBR layer 2, a first SCH layer 7, an active layer 3, a second SCH layer 8, a first oxide layer 41, a second oxide layer 42 and a second DBR layer 5 stacked on a substrate 1 in sequence.

[0041] It also includes a first SCH layer 7 and a second SCH layer 8, and the SCH is a separated confinement heterostructure, wherein the first SCH layer 7 and the first DBR layer 2 have the same doping type, and the second SCH layer 8 and the second DBR layer 5 have the same doping type. The first SCH layer 7 is located between the first DBR layer 2 and the active layer 3, and the second SCH layer 8 is located between the active layer 3 and the oxide layer 4. The first SCH layer 7 and the second SCH layer 8 are used to confine holes and electrons, respectively, to improve the carrier injection efficiency.

[0042] It also includes a first electrode 91 and a second electrode 92, wherein the first electrode 91 is located on the back of the substrate 1, and the second electrode 92 is located on the second DBR layer 5. In this embodiment, the first electrode 91 is an N electrode, and the second electrode 92 is a P electrode.

[0043] In this embodiment, the substrate 1 is n-type GaAs, the doping type of the first DBR layer 2 is N-type, the first SCH layer 7 is the same as the first DBR layer 2 in doping type, which is also N-type, and the first SCH layer 7 is used to limit holes and improve the carrier injection efficiency. The doping type of the current spreading layer 6 is P-type, the doping type of the second DBR layer 5 is P-type, the second SCH layer 8 is the same as the second DBR layer 5 in doping type, which is also P-type, and the second SCH layer 8 is used to limit electrons and improve the carrier injection efficiency.

[0044] Of course, according to actual product conditions, a vertical cavity surface emitting laser can also be designed, including a first DBR layer 2, a first SCH layer 7, an active layer 3, a second SCH layer 8, a first oxide layer 41, a second oxide layer 42, and a second DBR layer 5 stacked in sequence on a substrate 1. The doping type of the substrate 1 is P type, the doping type of the first DBR layer 2 is P type, the doping type of the first SCH layer 7 is P type, the doping type of the current spreading layer 6 is N type, the doping type of the second DBR layer 5 is N type, and the doping type of the second SCH layer 8 is N type.

[0045] The above description is only a preferred embodiment of the utility model and does not limit the technical scope of the utility model. Therefore, any changes or modifications made according to the claims and description of the utility model should fall within the scope of the utility model patent.

Claims

1. A vertical cavity surface emitting laser, characterized in that: The invention comprises a first DBR layer, an active layer, an oxide layer and a second DBR layer which are sequentially stacked on a substrate, a current spreading layer which is located between the active layer and the oxide layer, and a first SCH layer and a second SCH layer, wherein the first SCH layer and the first DBR layer have the same doping type, and the second SCH layer and the second DBR layer have the same doping type; the first SCH layer is located between the first DBR layer and the active layer, and the second SCH layer is located between the active layer and the oxide layer.

2. A vertical cavity surface emitting laser according to claim 1, characterized in that: The material of the current spreading layer is AlGaAs or GaAs.

3. A vertical cavity surface emitting laser according to claim 1, characterized in that: The current diffusion layer is P-type doped.

4. A vertical cavity surface emitting laser according to claim 1, characterized in that: The thickness of the current spreading layer is (1 / 4+m*1 / 2)λ, λ is the lasing wavelength, and m=1, 2, 3, 4.

5. A vertical cavity surface emitting laser according to claim 4, characterized in that: The range of λ is 800-1000nm.

6. A vertical cavity surface emitting laser according to claim 1, characterized in that: The substrate is n-type GaAs, the doping types of the first SCH layer and the first DBR layer are N-type, the current spreading layer is P-type, and the doping types of the second SCH layer and the second DBR layer are P-type.

7. The vertical cavity surface emitting laser according to claim 1, characterized in that: The active layer contains 3-5 quantum wells, the material of the potential wells is InGaAs, and the material of the potential barriers is one of GaAs, AlGaAs, GaAsP or AlGaAsP.

8. The vertical cavity surface emitting laser according to claim 1, characterized in that: The oxide layer includes a first oxide layer and a second oxide layer, and the diameter of the oxide pores in the first oxide layer is smaller than that in the second oxide layer.

9. The vertical cavity surface emitting laser according to claim 1, characterized in that: The device also includes a first electrode and a second electrode. The first electrode is located on the back side of the substrate, and the second electrode is located on the second DBR layer.

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