Quantum chip, quantum chip packaging box and quantum computer
Through the three-layer quantum chip design, the top wiring layer and the middle qubit layer are directly laminated and connected to disperse the wiring pressure, solving the problem of increasing the lateral size of the quantum chip, which makes it difficult to suppress the packaging cavity mode, and achieving the effect of reducing wiring density and preparation difficulty.
Patent Information
- Application Number
- CN202420632759.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-03-29
- Publication Date
- 2025-04-11
- Estimated Expiration
- 2034-03-29
AI Technical Summary
As the number of qubits increases, the lateral size of the quantum chip increases, making it difficult to suppress the packaging cavity pattern and affecting the performance of the qubit.
A quantum chip design adopts a three-layer structure, in which the top wiring layer and the middle qubit layer are directly connected layered, and the microwave control line, flux control line, read bus and read resonator are optionally arranged in the three layers to disperse the wiring pressure and reduce the lateral dimension.
Effectively reduce the lateral size of the quantum chip, reduce the impact of the packaging cavity mode on the performance of quantum bits, reduce wiring density, and reduce preparation difficulty.
Smart Images
Figure CN222750829U_ABST
Abstract
Description
Technical Field
[0001] The utility model belongs to the technical field of quantum chip manufacturing, in particular to a quantum chip, a quantum chip packaging box and a quantum computer. Background Art
[0002] At present, the structure of superconducting quantum chips is basically a two-layer chip structure. The two layers of chips are connected by flip-chip technology, which can alleviate the wiring pressure problem to a certain extent.
[0003] As the number of quantum bits increases, the wiring density increases dramatically, and the lateral size of the quantum chip will continue to increase. Since the lateral size of a quantum chip is much larger than its longitudinal size, the increase in the lateral size will make it difficult to suppress the packaging cavity mode corresponding to the quantum chip, which in turn affects the performance of the quantum bit.
[0004] Therefore, reducing the lateral size of the quantum chip and thereby suppressing the impact of the packaging cavity mode on the performance of the quantum bit is an urgent problem to be solved. Utility Model Content
[0005] The purpose of the utility model is to provide a quantum chip, a quantum chip packaging box and a quantum computer to solve the deficiencies in the prior art, and the utility model can reduce the lateral size of the quantum chip.
[0006] The solution of this application example is implemented through the following contents.
[0007] In a first aspect, an example of the present application proposes a quantum chip, comprising a top wiring layer, an intermediate quantum bit layer, and a bottom wiring layer, wherein the top wiring layer and the intermediate quantum bit layer are directly stacked and connected;
[0008] The quantum chip includes a quantum bit, a microwave control line, a magnetic flux control line, a read bus and a read resonator;
[0009] The qubits are arranged in the intermediate qubit layer, and the microwave control lines, the flux control lines, the read bus and the read resonator are optionally arranged in the top wiring layer or the intermediate qubit layer or the bottom wiring layer;
[0010] The read resonator is coupled to the read bus and the quantum bit respectively, and the microwave control line and the magnetic flux control line are coupled to the quantum bit respectively.
[0011] According to some examples of the present application, the lines of the top wiring layer and the quantum bits of the intermediate quantum bit layer are connected by out-of-plane capacitive coupling.
[0012] According to some examples of the present application, the top wiring layer includes a first surface and a second surface that are opposite to each other, the intermediate quantum bit layer includes a third surface and a fourth surface that are opposite to each other, and the bottom wiring layer includes a fifth surface;
[0013] The quantum bits are arranged on the fourth surface;
[0014] The third surface of the intermediate qubit layer is connected to the second surface of the top wiring layer, and the fourth surface of the intermediate qubit layer is connected to the fifth surface of the bottom wiring layer via a support.
[0015] According to some examples of the present application, the support member includes an indium column, the indium column includes a first end and a second end, the first end is connected to the fourth surface, and the second end is connected to the fifth surface;
[0016] And / or, a non-metallic dielectric layer is disposed between the second surface and the third surface, and the non-metallic dielectric layer is used to protect the circuits configured on the second surface.
[0017] According to some examples of the present application, the top wiring layer includes a first surface and a second surface that are opposite to each other, the intermediate quantum bit layer includes a third surface and a fourth surface that are opposite to each other, and the bottom wiring layer includes a fifth surface;
[0018] The quantum bits are arranged on the third surface;
[0019] The third surface of the intermediate qubit layer is connected to the second surface of the top wiring layer, and the fourth surface of the intermediate qubit layer is connected to the fifth surface of the bottom wiring layer.
[0020] According to some examples of the present application, a non-metallic dielectric layer is provided between the second surface and the third surface, and the non-metallic dielectric layer is used to protect the circuit configured on the third surface;
[0021] And / or, the non-metallic dielectric layer is disposed between the fourth surface and the fifth surface, and the non-metallic dielectric layer is also used to protect the circuits configured on the fifth surface.
[0022] According to some examples of the present application, the quantum chip includes a first port, the first port being connected to the microwave control line and being used to input a microwave control signal to the microwave control line;
[0023] And / or, the quantum chip comprises a second port, the second port is coplanarly connected to the magnetic flux control line, and is used to input a magnetic flux control signal to the magnetic flux control line;
[0024] And / or, the quantum chip includes a third port, which is connected to the read bus and is used to input a read signal to the quantum bit and output a read output signal fed back by the quantum bit.
[0025] In a second aspect, an example of the present application provides a quantum chip packaging box, comprising the quantum chip described in the first aspect above, wherein the quantum chip packaging box further comprises a base, side walls and a top cover;
[0026] The base is used to place the quantum chip;
[0027] The side wall has a first connection port, a second connection port and a third connection port;
[0028] The first connection port is connected to the first port of the microwave control line in the quantum chip, and is used to input a microwave control signal to the microwave control line;
[0029] The second connection port is connected to the second port of the magnetic flux control line in the quantum chip, and is used to input a magnetic flux control signal to the magnetic flux control line;
[0030] The third connection port is connected to the third port of the read bus in the quantum chip, and is used to input a read signal to the quantum bit of the quantum chip through the read bus and obtain a read output signal fed back by the quantum bit.
[0031] According to some examples of the present application, the first connection port and the first port are in the same plane;
[0032] The second connection port and the second port are located in the same plane;
[0033] The third connection port and the third port are located in the same plane.
[0034] In a third aspect, an example of the present application proposes a quantum computer, comprising the quantum chip described in the first aspect above, or the quantum chip packaging box described in the second aspect above.
[0035] In the quantum chip of the aforementioned example in the present application, microwave control lines, flux control lines, read buses and read resonators are optionally configured in the top wiring layer, the middle quantum bit layer or the bottom wiring layer, dispersing the wiring of the entire quantum chip to each layer, reducing the wiring pressure of each layer of the quantum chip, effectively reducing the lateral size of the quantum chip, and thereby suppressing the influence of the packaging cavity mode on the quantum bit performance.
[0036] The quantum chip packaging box and quantum computer provided by the utility model have the same beneficial effects, which will not be described in detail here. BRIEF DESCRIPTION OF THE DRAWINGS
[0037] For a clearer explanation, the following briefly introduces the drawings required for the description.
[0038] Figure 1 This is a schematic diagram of the structure of a quantum chip in an example of this application;
[0039] Figure 2 This is a schematic diagram of the structure of a quantum chip in another example of this application;
[0040] Figure 3 This is a schematic diagram of the structure of a quantum chip in another example of this application;
[0041] Figure 4 This is a schematic diagram of the structure of a quantum chip packaging box in another example of the present application. DETAILED DESCRIPTION
[0042] In order to enable those skilled in the art to better understand the technical solutions in the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of this application. The embodiments described below with reference to the drawings are exemplary and are only used to explain the present application, and cannot be interpreted as limitations on the present application.
[0043] In the description of the present invention, it should be understood that the terms "center", "up", "down", "left", "right", etc. indicate directions or positional relationships based on the directions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore should not be understood as a limitation on the present invention.
[0044] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present utility model, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.
[0045] At present, the structure of superconducting quantum chips is basically a two-layer chip structure, and the two layers of chips are connected by flip-chip technology, which can alleviate the wiring pressure problem to a certain extent. However, as the number of quantum bits increases, the layout pressure of the two-layer chip gradually increases, the wiring density on the quantum chip increases dramatically, and the crosstalk problem faced by quantum bits becomes more and more serious.
[0046] In addition, in the process of superconducting quantum chip packaging, the quantum chip needs to be placed in a metal structure component. The size of the metal component is related to the size of the quantum chip, and the metal component itself has a specific resonant frequency. In theory, the waveguide rectangular cavity model is often used to describe the above metal component. For a rectangular cavity structure with a certain size, it has a fixed resonant mode and its eigenmode frequency is
[0047]
[0048] Where n, m, and p are integers representing different cavity modes, such as the TE110 mode. x , l y , l z Represents the size of the rectangular cavity in all directions in the rectangular coordinate system (i.e., the length, width, and height of the rectangular cavity). ∈ and μ represent the dielectric constant and magnetic permeability of the medium in the cavity, respectively.
[0049] It can be seen from the above formula that when the size of the rectangular cavity is larger, the cavity mode frequency is smaller and the impact on the quantum bit is stronger. At the same time, because the relative dielectric constant of the chip medium (generally silicon) is large, the effective dielectric constant inside the entire cavity will be much larger than that in the vacuum state, resulting in a further reduction in the cavity mode. The bit frequency is generally set in the range of 4-6GHz. If the low-order mode of the rectangular cavity is lower than this frequency, the high-order mode of the rectangular cavity will enter this frequency range and affect the quantum bit. Therefore, in actual engineering, it is necessary to increase the lowest submode frequency of the rectangular cavity to above the bit frequency range.
[0050] Usually l x , l y 》l z According to the above formula, the dimension that affects the lowest mode frequency of the rectangular cavity is mainly l x , l y . x , l y The size of the quantum chip package (i.e., the length and width of the quantum chip package) is usually proportional to the size of the quantum chip wiring layer (the size of the quantum chip wiring layer is larger than the quantum bit layer). Then, as the number of quantum bits increases, the horizontal length and width of the quantum chip wiring layer increase, and the corresponding cavity membrane type will have a more serious impact on the performance of the quantum bit.
[0051] Therefore, how to reduce the lateral size of the quantum chip, suppress the impact of the packaging cavity mode on the performance of the quantum bit, and reduce the wiring density of the quantum chip is an urgent problem to be solved.
[0052] Based on this, Figure 1As shown, an embodiment of the present invention discloses a quantum chip, for example, the quantum chip includes a top wiring layer 100, an intermediate quantum bit layer 200 and a bottom wiring layer 300, and the top wiring layer 100 and the intermediate quantum bit layer 200 are directly stacked and connected;
[0053] The quantum chip includes a quantum bit, a microwave control line, a magnetic flux control line, a read bus, and a read resonator;
[0054] The qubits are arranged in the middle qubit layer 200, and the microwave control lines, the magnetic flux control lines, the read bus and the read resonator are optionally arranged in the top wiring layer 100 or the middle qubit layer 200 or the bottom wiring layer 300;
[0055] The read resonator is coupled to the read bus and the quantum bit, respectively, and the microwave control line and the flux control line are coupled to the quantum bit, respectively.
[0056] Among them, for the top wiring layer 100, the intermediate quantum bit layer 200 and the bottom wiring layer 300 in the quantum chip disclosed in the present utility model, the top wiring layer 100 and the intermediate quantum bit layer 200 are directly stacked and connected, and the intermediate quantum bit layer 200 and the bottom wiring layer 300 can be directly stacked and connected or connected through a supporting element.
[0057] In addition, all quantum bits in the quantum chip disclosed in the utility model are located on the same surface of the middle quantum bit layer 200; all microwave control lines in the quantum chip are located on the same surface of the top wiring layer 100 or the middle quantum bit layer 200 or the bottom wiring layer 300, and the distribution principle of the flux control line, the read bus and the read resonator is consistent with the microwave control line. Therefore, there are no lines of the same type distributed in different layers in the quantum chip, nor are there lines of the same type distributed on two opposite surfaces of the same layer, which avoids the risk of upper and lower routing of the same type of lines. In the manufacturing process of the quantum chip disclosed in the utility model, the same type of lines are made on the same surface, which can reduce the risk of line breakage and reduce the difficulty of chip preparation.
[0058] In the quantum chip disclosed in the present utility model, microwave control lines, flux control lines, read buses and read resonators are optionally configured in the top wiring layer 100 or the intermediate quantum bit layer 200 or the bottom wiring layer 300, dispersing the wiring of the entire quantum chip to each layer, reducing the wiring density of each layer, and reducing the impact of line crosstalk. Compared with the two-layer chip structure of the prior art, the three-layer structure disclosed in the present utility model can disperse the wiring pressure of the bottom wiring layer 300 through the top wiring layer 100 and the intermediate quantum bit layer 200, which can effectively reduce the size of the bottom wiring layer 300, thereby reducing the length and width of the quantum chip. In addition, the direct stacking connection between the top wiring layer 100 and the intermediate quantum bit layer 200 can effectively reduce the difficulty of preparing the quantum chip.
[0059] Based on the above description, the cavity mode of the quantum chip package is mainly affected by the lateral length and width. Compared with the length and width, the influence of the height on the cavity mode can be ignored. Therefore, in the present invention, the microwave control line, the magnetic flux control line, the read bus and the read resonator are optionally configured in the top wiring layer 100 or the middle quantum bit layer 200 or the bottom wiring layer 300 to reduce the length and width of the quantum chip, thereby suppressing the influence of the package cavity mode on the quantum bit performance.
[0060] In one embodiment of the present application, the wiring of the top wiring layer 100 and the qubits of the intermediate qubit layer 200 are connected by out-of-plane capacitive coupling. In capacitive coupling, the top wiring layer 100 or the intermediate qubit layer 200 serves as an intermediate dielectric layer of the capacitor.
[0061] The lines of the top wiring layer 100 and the qubits of the intermediate qubit layer 200 are coupled via capacitance, and the top wiring layer 100 or the intermediate qubit layer 200 serves as an intermediate dielectric layer of the capacitor.
[0062] Specifically, when the circuits of the top wiring layer 100 and the qubits of the intermediate qubit layer 200 are capacitively coupled, a parallel plate capacitor is formed between the circuits of the top wiring layer 100 and the qubits. Figure 2, the top wiring layer 100 includes a first surface 110 and a second surface 120 that are opposite to each other, and the intermediate qubit layer 200 includes a third surface 210 and a fourth surface 220 that are opposite to each other. When the qubits are distributed on the fourth surface 220, the lines distributed on the first surface 110 connect the qubits through capacitive coupling, and the top wiring layer 100 and the intermediate qubit layer 200 jointly serve as the intermediate dielectric layer of the capacitor; when the qubits are distributed on the fourth surface 220, the lines distributed on the second surface 120 connect the qubits through capacitive coupling, and the intermediate qubit layer 200 serves as the intermediate dielectric layer of the capacitor; when the qubits are distributed on the third surface 220, the lines distributed on the first surface 110 connect the qubits through capacitive coupling, and the top wiring layer 100 serves as the intermediate dielectric layer of the capacitor.
[0063] like Figure 2 As shown, in one embodiment of the present application, the top wiring layer 100 includes an opposite first surface 110 and a second surface 120, the intermediate quantum bit layer 200 includes an opposite third surface 210 and a fourth surface 220, and the bottom wiring layer 300 includes a fifth surface 310;
[0064] The quantum bits are arranged on the fourth surface 220;
[0065] The third surface 210 of the intermediate qubit layer 200 is connected to the second surface 120 of the top wiring layer 100 , and the fourth surface 220 of the intermediate qubit layer 200 is connected to the fifth surface 310 of the bottom wiring layer 300 via a support.
[0066] The microwave control lines, magnetic flux control lines, read buses and read resonators are optionally configured on the first surface 110 or the second surface 120 or the fourth surface 220 or the fifth surface 310. The first surface 110 and the second surface 120 may be distributed with one or more of the microwave control lines, magnetic flux control lines, read buses and read resonators at the same time.
[0067] Since the quantum bits are arranged on the fourth surface 220, and the intermediate quantum bit layer 200 and the bottom wiring layer 300 are connected via a support, the coupling mode between the lines on the fifth surface 310 and the quantum bits of the intermediate quantum bit layer 200 can be capacitive coupling or inductive coupling.
[0068] In one embodiment of the present application, the support is a superconductor.
[0069] The support member in the quantum chip disclosed in the utility model can be selected as a superconducting material such as an indium column, or a non-superconducting material. However, no matter what material the support member is made of, the support member serves as a structural component that supports and connects the fourth surface 220 and the fifth surface 310, rather than a signal line.
[0070] In one embodiment of the present application, the support member includes an indium column, the indium column includes a first end and a second end, the first end is connected to the fourth surface 220, and the second end is connected to the fifth surface 310;
[0071] And / or, a non-metallic dielectric layer is disposed between the second surface 120 and the third surface 210 , and the non-metallic dielectric layer is used to protect the circuits configured on the second surface 120 .
[0072] The support member includes an indium column. Since the support member is not a signal line, the indium column does not need to be used as a transmission channel for transmitting signals, thereby avoiding the high production quality requirement of the indium column used for signal transmission.
[0073] When the second surface 120 of the top wiring layer 100 is distributed with circuits, at this time, the circuits of the top wiring layer 100 and the qubits of the intermediate qubit layer 200 are capacitively coupled, and the intermediate qubit layer 200 is equivalent to the medium between the two plates of the capacitor. The size of the capacitor is determined by the thickness and material of the intermediate qubit layer 200. When the top wiring layer 100 and the qubit are connected, a non-metallic dielectric layer needs to be coated between the top wiring layer 100 and the intermediate qubit to reduce the risk of damage to the wiring of the second surface 120 during the connection process. In addition, the non-metallic property of the non-metallic dielectric layer can reduce the interference with the capacitive coupling between the circuits of the second surface 120 and the qubit. The material of the non-metallic dielectric layer can be selected as needed, and the scheme disclosed in the utility model does not specifically limit this.
[0074] like Figure 3 As shown, in one embodiment of the present application, the top wiring layer 100 includes an opposite first surface 110 and a second surface 120, the intermediate quantum bit layer 200 includes an opposite third surface 210 and a fourth surface 220, and the bottom wiring layer 300 includes a fifth surface 310;
[0075] The quantum bits are arranged on the third surface 210;
[0076] The third surface 210 of the intermediate qubit layer 200 is connected to the second surface 120 of the top wiring layer 100 , and the fourth surface 220 of the intermediate qubit layer 200 is connected to the fifth surface 310 of the bottom wiring layer 300 .
[0077] Among them, when the quantum bits are configured on the third surface 210, the microwave control lines, the flux control lines, the read bus and the read resonator are optionally configured on the first surface 110 or the third surface 210 or the fifth surface 310 to reduce the risk of damage to the lines configured in each layer during the process of connecting the intermediate quantum bit layer 200 to the bottom wiring layer 300 of the top wiring layer 100 respectively.
[0078] In one embodiment of the present application, a non-metallic dielectric layer is disposed between the second surface 120 and the third surface 210, and the non-metallic dielectric layer is used to protect the circuit configured on the third surface 210;
[0079] And / or, a non-metallic dielectric layer is disposed between the fourth surface 220 and the fifth surface 310, and the non-metallic dielectric layer is also used to protect the circuits configured on the fifth surface 310;
[0080] And / or, the coupling mode between the lines of the bottom wiring layer 300 and the quantum bits of the middle quantum bit layer 200 is capacitive coupling.
[0081] Specifically, when the qubit is configured on the third surface 210, the circuit of the top wiring layer 100 is distributed on the first surface 110, and the circuit of the bottom wiring layer 300 is distributed on the fifth surface 310. At this time, the intermediate qubit layer 200 and the bottom wiring layer 300 are directly stacked and connected, and the coupling mode between the circuit of the top wiring layer 100 and the qubit of the intermediate qubit layer 200 is capacitive coupling, and the coupling mode between the circuit of the bottom wiring layer 300 and the qubit of the intermediate qubit layer 200 is also capacitive coupling. When the top wiring layer 100 and the intermediate qubit are connected, a non-metallic dielectric layer needs to be coated between the top wiring layer 100 and the intermediate qubit to reduce the risk of damage to the wiring of the second surface 120 during the connection process. When the bottom wiring layer 300 and the intermediate qubit are connected, a non-metallic dielectric layer needs to be coated between the bottom wiring layer 300 and the intermediate qubit to reduce the risk of damage to the wiring of the fifth surface 310 during the connection process. The material of the non-metallic dielectric layer can be selected as needed, and the scheme disclosed in the utility model does not specifically limit this.
[0082] In one embodiment of the present application, Figure 4 As shown, the quantum chip includes a first port 410, which is connected to the microwave control line and is used to input a microwave control signal to the microwave control line;
[0083] And / or, the quantum chip comprises a second port 510, the second port 510 is coplanarly connected to the magnetic flux control line, and is used to input a magnetic flux control signal to the magnetic flux control line;
[0084] And / or, the quantum chip includes a third port 610, which is connected to the read bus and is used to input a read signal to the quantum bit and output a read output signal fed back by the quantum bit.
[0085] Among them, since the microwave control line transmits high-frequency signals, the first port 410 and the microwave control line can be connected in the same plane or connected by capacitor coupling in different planes. Since the read bus also transmits high-frequency signals, the third port 610 and the read bus can be connected in the same plane or connected by capacitor coupling in different planes. Since the magnetic flux control line transmits DC signals, the second port 510 and the magnetic flux control line need to be electrically connected in the same plane.
[0086] In one embodiment of the present application, the first port 410 , the second port 510 , and the third port 610 are optionally distributed on the first surface 110 or the fifth surface 310 .
[0087] Specifically, the first port 410 of the quantum chip is bonded to the packaging box for obtaining and inputting a microwave control signal to the microwave control line; the second port 510 of the quantum chip is bonded to the packaging box for obtaining and inputting a flux control signal to the flux control line; the third port 610 of the quantum chip is bonded to the packaging box for inputting a read signal to the quantum bit and outputting a read output signal fed back by the quantum bit ( Figure 4 In the example, only the microwave control lines and the magnetic flux control lines are distributed on the first surface 110, and the read bus is distributed on the fifth surface 310).
[0088] In one embodiment of the present application, Figure 4 As shown, the utility model provides a quantum chip packaging box, comprising: the quantum chip disclosed above, the quantum chip packaging box also includes a base, side walls and a top cover;
[0089] The base is used to place the quantum chip;
[0090] The side wall has a first connection port 420, a second connection port 520 and a third connection port 620;
[0091] The first connection port 420 is connected to the first port 410 of the microwave control line in the quantum chip, and is used to input a microwave control signal to the microwave control line;
[0092] The second connection port 520 is connected to the second port 510 of the magnetic flux control line in the quantum chip, and is used to input a magnetic flux control signal to the magnetic flux control line;
[0093] The third connection port 620 is connected to the third port 610 of the read bus in the quantum chip, and is used to input a read signal to the quantum bit of the quantum chip through the read bus and obtain a read output signal fed back by the quantum bit.
[0094] Specifically, the quantum chip packaging box connects the quantum chip to the first connection port 420 , the second connection port 520 , and the third connection port 620 respectively by bonding to perform signal transmission.
[0095] Since the size of the quantum chip package box is determined by the size of the bottom wiring layer 300 of the quantum chip, when the length and width of the quantum chip are reduced, the size of the corresponding quantum chip package box is also reduced, thereby suppressing the influence of the cavity mode of the package box on the quantum bit and protecting the performance of the quantum bit.
[0096] In one embodiment of the present application, Figure 4 As shown, the first connection port 420 and the first port 410 are located in the same plane;
[0097] The second connection port 520 and the second port 510 are on the same plane;
[0098] The third connection port 620 and the third port 610 are located on the same plane.
[0099] Specifically, the first connection port 420 is coplanarly bonded to the first port 410, the second connection port 520 is coplanarly bonded to the second port 510, and the third connection port 620 is coplanarly bonded to the third port 610, which can shorten the length of the bonding wire, facilitate distortion-free transmission of the signal and reduce signal crosstalk between the bonding wires.
[0100] In one embodiment of the present application, the utility model provides a quantum computer, comprising the above-mentioned quantum chip.
[0101] Regarding the technical effects of the quantum chip packaging box and quantum computer of the above-mentioned embodiment, reference can be made to other embodiments of this specification for comparative explanation, and no further description will be given here.
[0102] In the description of this specification, the description with reference to the terms "some embodiments" or "examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiments or examples are included in at least one embodiment or example of the utility model. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments in a suitable manner. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification.
[0103] The above are only preferred embodiments of the present invention and do not limit the present invention in any way. Any technician in the relevant technical field, without departing from the scope of the technical solution of the present invention, may make any equivalent replacement or modification to the technical solution and technical content disclosed in the present invention, which shall be deemed as the content of the technical solution of the present invention and still fall within the protection scope of the present invention.
Claims
1. A quantum chip, characterized in that: It includes a top wiring layer, an intermediate quantum bit layer and a bottom wiring layer, wherein the top wiring layer and the intermediate quantum bit layer are directly stacked and connected; The quantum chip includes a quantum bit, a microwave control line, a magnetic flux control line, a read bus and a read resonator; The qubits are arranged in the intermediate qubit layer, and the microwave control lines, the flux control lines, the read bus and the read resonator are optionally arranged in the top wiring layer or the intermediate qubit layer or the bottom wiring layer; The read resonator is coupled to the read bus and the quantum bit respectively, and the microwave control line and the magnetic flux control line are coupled to the quantum bit respectively.
2. The quantum chip according to claim 1, characterized in that: The lines of the top wiring layer and the quantum bits of the intermediate quantum bit layer are connected by out-of-plane capacitive coupling.
3. The quantum chip according to claim 1, characterized in that: The top wiring layer includes a first surface and a second surface that are opposite, the intermediate qubit layer includes a third surface and a fourth surface that are opposite, and the bottom wiring layer includes a fifth surface; The quantum bits are arranged on the fourth surface; The third surface of the intermediate qubit layer and the second surface of the top wiring layer are directly connected, and the fourth surface of the intermediate qubit layer and the fifth surface of the bottom wiring layer are connected via a support.
4. The quantum chip according to claim 3, characterized in that: The support member includes an indium column, the indium column includes a first end and a second end, the first end is connected to the fourth surface, and the second end is connected to the fifth surface; And / or, a non-metallic dielectric layer is disposed between the second surface and the third surface, and the non-metallic dielectric layer is used to protect the circuits configured on the second surface.
5. The quantum chip according to claim 1, characterized in that: The top wiring layer includes a first surface and a second surface that are opposite, the intermediate qubit layer includes a third surface and a fourth surface that are opposite, and the bottom wiring layer includes a fifth surface; The quantum bits are arranged on the third surface; The third surface of the intermediate qubit layer is connected to the second surface of the top wiring layer, and the fourth surface of the intermediate qubit layer is connected to the fifth surface of the bottom wiring layer.
6. The quantum chip according to claim 5, characterized in that: A non-metallic dielectric layer is disposed between the second surface and the third surface, and the non-metallic dielectric layer is used to protect the circuits configured on the third surface; And / or, the non-metallic dielectric layer is disposed between the fourth surface and the fifth surface, and the non-metallic dielectric layer is also used to protect the circuits configured on the fifth surface.
7. The quantum chip according to claim 1, characterized in that: The quantum chip comprises a first port, the first port being connected to the microwave control line and being used to input a microwave control signal to the microwave control line; And / or, the quantum chip comprises a second port, the second port is coplanarly connected to the magnetic flux control line, and is used to input a magnetic flux control signal to the magnetic flux control line; And / or, the quantum chip includes a third port, which is connected to the read bus and is used to input a read signal to the quantum bit and output a read output signal fed back by the quantum bit.
8. A quantum chip packaging box, comprising the quantum chip according to any one of claims 1 to 7, characterized in that: The quantum chip packaging box also includes a base, side walls and a top cover; The base is used to place the quantum chip; The side wall has a first connection port, a second connection port and a third connection port; The first connection port is connected to the first port of the microwave control line in the quantum chip, and is used to input a microwave control signal to the microwave control line; The second connection port is connected to the second port of the magnetic flux control line in the quantum chip, and is used to input a magnetic flux control signal to the magnetic flux control line; The third connection port is connected to the third port of the read bus in the quantum chip, and is used to input a read signal to the quantum bit of the quantum chip through the read bus and obtain a read output signal fed back by the quantum bit.
9. The quantum chip packaging box according to claim 8, characterized in that: The first connection port and the first port are located in the same plane; The second connection port and the second port are located in the same plane; The third connection port and the third port are located in the same plane.
10. A quantum computer, characterized in that: It comprises the quantum chip according to any one of claims 1 to 7, or the quantum chip packaging box according to claim 8 or 9.