Transmission control circuit for camera and camera

Abstract

The embodiment of the utility model provides a transmission control circuit for a camera and the camera. The alarm circuit for the camera comprises a clock selection circuit, a data selection circuit, a control circuit, a bus circuit, a first chip and a second chip, an input end of the clock selection circuit is respectively connected with the control circuit and the bus circuit, an input end of the data selection circuit is respectively connected with the control circuit and the bus circuit, and an output end of the data selection circuit is connected with the first chip. The output end of the clock selection circuit is respectively connected with the first chip and the second chip, and the output end of the data selection circuit is respectively connected with the first chip and the second chip; the control circuit is used for controlling the first chip to be communicated with the bus circuit through the clock selection circuit and the data selection circuit, or controlling the second chip to be communicated with the bus circuit through the clock selection circuit and the data selection circuit. And the complexity of the internal circuit structure of the camera is reduced.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of electronic technology, and in particular to a transmission control circuit for a camera and a camera. Background Art

[0002] The camera includes at least one camera, and a geomagnetic sensor chip can be set in the camera. When the camera collects images, the geomagnetic sensor chip can simultaneously obtain the direction and position of the current shooting scene.

[0003] After acquiring the image captured by the camera, the camera needs to obtain the direction and position of the geomagnetic sensor chip. In actual application, a set of busses of the camera can only be connected to one geomagnetic sensor chip. If there are multiple geomagnetic sensor chips in the camera, multiple sets of buses need to be set up to connect the corresponding geomagnetic sensor chips, resulting in a high complexity of the internal circuit structure of the camera. Utility Model Content

[0004] The embodiments of the present application provide a transmission control circuit for a camera and a camera, so as to solve the problem of high complexity of the internal circuit structure of the camera.

[0005] In a first aspect, an embodiment of the present application provides a transmission control circuit for a camera, comprising: a clock selection circuit, a data selection circuit, a control circuit, a bus circuit, a first chip and a second chip, wherein:

[0006] The input end of the clock selection circuit is connected to the control circuit and the bus circuit respectively, the input end of the data selection circuit is connected to the control circuit and the bus circuit respectively, the output end of the clock selection circuit is connected to the first chip and the second chip respectively, and the output end of the data selection circuit is connected to the first chip and the second chip respectively;

[0007] The control circuit is used to control the first chip to be connected to the bus circuit through the clock selection circuit and the data selection circuit respectively, or to control the second chip to be connected to the bus circuit through the clock selection circuit and the data selection circuit respectively.

[0008] In a possible implementation manner, the clock selection circuit and the data selection circuit respectively include a first input terminal, a second input terminal and a third input terminal, wherein:

[0009] The first input terminal of the clock selection circuit is connected to the bus circuit, the second input terminal of the clock selection circuit is connected to the control circuit, and the third input terminal of the clock selection circuit is connected to the first power supply circuit;

[0010] The first input terminal of the data selection circuit is connected to the bus circuit, the second input terminal of the data selection circuit is connected to the control circuit, and the third input terminal of the data selection circuit is connected to the second power supply circuit.

[0011] In a possible implementation, the first power supply circuit includes a first capacitor and a first power supply, and the second power supply circuit includes a second capacitor and a second power supply, wherein:

[0012] One end of the first capacitor is connected to one end of the first power supply, the other end of the first capacitor is grounded, and the other end of the first power supply is connected to the third input end of the clock selection circuit;

[0013] One end of the second capacitor is connected to one end of the second power supply, the other end of the second capacitor is grounded, and the other end of the second power supply is connected to the third input end of the data selection circuit.

[0014] In a possible implementation manner, the clock selection circuit and the data selection circuit respectively include a first output terminal, a second output terminal and a third output terminal, wherein:

[0015] The first output terminal of the clock selection circuit is connected to the first chip, the second output terminal of the clock selection circuit is connected to the second chip, and the third output terminal of the clock selection circuit is grounded;

[0016] The first output terminal of the data selection circuit is connected to the first chip, the second output terminal of the data selection circuit is connected to the second chip, and the third output terminal of the data selection circuit is grounded.

[0017] In a possible implementation manner, the control circuit is specifically used for:

[0018] Control the first output end of the clock selection circuit to be connected to the first chip, and control the first output end of the data selection circuit to be connected to the first chip; or,

[0019] The second output end of the clock selection circuit is controlled to be connected to the second chip, and the second output end of the data selection circuit is controlled to be connected to the second chip.

[0020] In a possible implementation, the bus circuit includes a data bus and a clock bus, wherein:

[0021] The clock bus is connected to the first input terminal of the clock selection circuit;

[0022] The data bus is connected to a first input terminal of the data selection circuit.

[0023] In a possible implementation, the control circuit includes a control chip, a first resistor and a second resistor, wherein:

[0024] One end of the first resistor is connected to the control chip, and the other end of the first resistor is connected to the second input of the clock selection circuit;

[0025] One end of the second resistor is connected to the control chip, and the other end of the second resistor is connected to the second input of the data selection circuit.

[0026] In a possible implementation manner, the control chip is specifically used for:

[0027] A control signal is output to the control circuit so that the control circuit controls the first chip to be connected to the bus circuit through the clock selection circuit and the data selection circuit according to the control signal, or controls the second chip to be connected to the bus circuit through the clock selection circuit and the data selection circuit according to the control signal.

[0028] In a possible implementation, the circuit further includes a third resistor, a fourth resistor, a fifth resistor and a sixth resistor, wherein:

[0029] One end of the third resistor is connected to the first output end of the clock selection circuit, and the other end of the third resistor is connected to the power pin of the first chip;

[0030] One end of the fourth resistor is connected to the second output end of the clock selection circuit, and the other end of the fourth resistor is connected to the power pin of the second chip;

[0031] One end of the fifth resistor is connected to the first output end of the data selection circuit, and the other end of the fifth resistor is connected to the power pin of the first chip;

[0032] One end of the sixth resistor is connected to the second output end of the data selection circuit, and the other end of the sixth resistor is connected to the power pin of the second chip.

[0033] In a second aspect, an embodiment of the present application provides a camera, comprising a transmission control circuit for a camera as described in any one of the first aspects.

[0034] The embodiment of the present application provides a transmission control circuit for a camera and a camera, comprising: a clock selection circuit, a data selection circuit, a control circuit, a bus circuit, a first chip and a second chip, wherein the input end of the clock selection circuit is connected to the control circuit and the bus circuit respectively, the input end of the data selection circuit is connected to the control circuit and the bus circuit respectively, the output end of the clock selection circuit is connected to the first chip and the second chip respectively, and the output end of the data selection circuit is connected to the first chip and the second chip respectively. The control circuit is used to control the first chip to be connected to the bus circuit through the clock selection circuit and the data selection circuit respectively, or to control the second chip to be connected to the bus circuit through the clock selection circuit and the data selection circuit respectively. In the above process, when the first chip and the second chip are connected to the same bus, the control circuit can control the first chip or the second chip to be connected to the bus circuit, thereby realizing the connection of multiple chips to the same bus. In order to avoid the situation where multiple geomagnetic sensor chips are provided in the camera, it is necessary to set up multiple groups of buses to connect the corresponding geomagnetic sensor chips, thereby reducing the complexity of the internal circuit structure of the camera. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0036] Figure 1 A schematic diagram of an application scenario provided by an embodiment of the present application;

[0037] Figure 2 A schematic diagram of the structure of a transmission control circuit for a camera provided in an embodiment of the present application;

[0038] Figure 3 A schematic diagram of the structure of a clock selection circuit provided in an embodiment of the present application;

[0039] Figure 4 A schematic diagram of a clock selection circuit provided in an embodiment of the present application;

[0040] Figure 5 A schematic diagram of the structure of a data selection circuit provided in an embodiment of the present application;

[0041] Figure 6 A schematic diagram of a data selection circuit provided in an embodiment of the present application;

[0042] Figure 7 A schematic diagram of the structure of a control circuit provided in an embodiment of the present application;

[0043] Figure 8 A schematic diagram of a transmission control circuit for a camera provided in an embodiment of the present application.

[0044] The above drawings have shown clear embodiments of the present application, which will be described in more detail later. These drawings and text descriptions are not intended to limit the scope of the present application in any way, but to illustrate the concept of the present application to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION

[0045] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0046] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0047] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with relevant laws, regulations and standards, and provide corresponding operation entrances for users to choose to authorize or refuse.

[0048] For ease of understanding, below, combined Figure 1 , the application scenarios to which the embodiments of the present application are applicable are described.

[0049] Figure 1 This is a schematic diagram of an application scenario provided by an embodiment of the present application. Figure 1 , including camera 101. Camera 101 includes multiple cameras, namely camera 1, camera 2, ..., camera N. Each camera is provided with a chip, which may be a geomagnetic sensor chip. When at least one camera of camera 101 captures an image, the chip in the camera can simultaneously obtain the direction and position of the current shooting scene. When camera 101 acquires an image captured by at least one camera, it also needs to acquire the direction and position captured by the chip in the camera.

[0050] In actual application, a set of buses of a camera can only be connected to one geomagnetic sensor chip. If a plurality of geomagnetic sensor chips are provided in the camera, a plurality of sets of buses need to be provided to connect the corresponding geomagnetic sensor chips, which results in a high complexity of the internal circuit structure of the camera.

[0051] In an embodiment of the present application, a transmission control circuit for a camera is provided, including: a clock selection circuit, a data selection circuit, a control circuit, a bus circuit, a first chip, and a second chip, wherein the input end of the clock selection circuit is connected to the control circuit and the bus circuit respectively, the input end of the data selection circuit is connected to the control circuit and the bus circuit respectively, the output end of the clock selection circuit is connected to the first chip and the second chip respectively, and the output end of the data selection circuit is connected to the first chip and the second chip respectively. The control circuit is used to control the first chip to be connected to the bus circuit through the clock selection circuit and the data selection circuit respectively, or to control the second chip to be connected to the bus circuit through the clock selection circuit and the data selection circuit respectively. In the above process, when the first chip and the second chip are connected to the same bus, the control circuit can be used to control the first chip or the second chip to be connected to the bus circuit, thereby realizing the connection of multiple chips to the same bus. In order to avoid the situation where multiple geomagnetic sensor chips are provided in the camera, it is necessary to set up multiple groups of buses to connect the corresponding geomagnetic sensor chips, thereby reducing the complexity of the internal circuit structure of the camera.

[0052] The method shown in the present application is described below through specific embodiments. It should be noted that the following embodiments can exist independently or in combination with each other, and the same or similar contents will not be described repeatedly in different embodiments.

[0053] Figure 2 This is a schematic diagram of the structure of a transmission control circuit for a camera provided in an embodiment of the present application. Figure 2 The transmission control circuit 200 for the camera may include: a clock selection circuit 201, a data selection circuit 202, a control circuit 203, a bus circuit 204, a first chip 205 and a second chip 206, wherein:

[0054] The input end of the clock selection circuit 201 is connected to the control circuit 203 and the bus circuit 204 respectively, the input end of the data selection circuit 202 is connected to the control circuit 203 and the bus circuit 204 respectively, the output end of the clock selection circuit 201 is connected to the first chip 205 and the second chip 206 respectively, and the output end of the data selection circuit 202 is connected to the first chip 205 and the second chip 206 respectively;

[0055] The control circuit 203 is used to control the first chip 205 to be connected to the bus circuit 204 through the clock selection circuit 202 and the data selection circuit 202, or to control the second chip 206 to be connected to the bus circuit 204 through the clock selection circuit 201 and the data selection circuit 202.

[0056] The first chip 205 and the second chip 206 may be geomagnetic sensor chips.

[0057] The bus circuit 204 includes a data bus and a clock bus. The clock selection circuit 201 is used to control the first chip 205 or the second control chip 206 to communicate with the clock bus in the bus circuit 204. The data selection circuit 202 is used to control the first chip 205 or the second control chip 206 to communicate with the data bus in the bus circuit 204.

[0058] The clock selection circuit 201 and the data selection circuit 202 may be electronic single-pole double-throw switches. For example, the model of the clock selection circuit 201 and the data selection circuit 202 may be 74LVC1G3157.

[0059] After the geomagnetic sensor chip is connected to the bus circuit 204 through the clock selection circuit 202 and the data selection circuit 202 respectively, the camera can obtain the data collected by the geomagnetic sensor chip through the bus circuit 204.

[0060] In actual application, the camera includes at least one camera, and each camera is provided with a geomagnetic sensor chip. The geomagnetic sensor chip in each camera can be connected to a bus of the camera through the control transmission circuit provided in the embodiment of the present application. In this way, multiple geomagnetic sensor chips with the same bus address can be configured and data acquired in a time-sharing manner.

[0061] The transmission control circuit for the camera provided in the embodiment of the present application can connect the first chip and the second chip to the same bus through the control circuit respectively through the clock selection circuit and the data selection circuit, or control the second chip to connect to the bus circuit respectively through the clock selection circuit and the data selection circuit, thereby realizing the connection of multiple chips to the same bus. This avoids the situation where multiple groups of buses need to be set up to connect the corresponding geomagnetic sensor chips when multiple geomagnetic sensor chips are set in the camera, thereby reducing the complexity of the internal circuit structure of the camera.

[0062] The clock selection circuit 201 controls the geomagnetic sensor chip to be connected to the clock bus. Figure 3 , the structure of the clock selection circuit 201 is described.

[0063] Figure 3This is a schematic diagram of the structure of the clock selection circuit provided in the embodiment of the present application. Figure 3 , the clock selection circuit 201 may include: a first input terminal, a second input terminal, a third input terminal, a first output terminal, a second output terminal and a third output terminal, wherein,

[0064] A first input terminal of the clock selection circuit 201 is connected to the bus circuit 204, a second input terminal of the clock selection circuit 201 is connected to the control circuit 203, and a third input terminal of the clock selection circuit 201 is connected to the first power supply circuit 207;

[0065] A first output terminal of the clock selection circuit 201 is connected to the first chip 205 , a second output terminal of the clock selection circuit 201 is connected to the second chip 206 , and a third output terminal of the clock selection circuit 201 is grounded.

[0066] The first input end of the clock selection circuit 201 may be a common end of an electronic single-pole double-throw switch, the first output end of the clock selection circuit 201 may be one output end of the electronic single-pole double-throw switch, and the second output end of the clock selection circuit 201 may be another output end of the electronic single-pole double-throw switch. The clock selection circuit 201 may determine that the first input end of the clock selection circuit 201 is connected to the first output end or the second output end according to the control signal output by the control circuit 203, so that the clock bus in the bus circuit 204 is connected to the first chip 205 or the second chip 206.

[0067] The clock bus in the bus circuit 204 is connected to the first input terminal of the clock selection circuit 201 .

[0068] The first power supply circuit 207 includes a first capacitor and a first power supply, wherein:

[0069] One end of the first capacitor is connected to one end of the first power supply, the other end of the first capacitor is grounded, and the other end of the first power supply is connected to the third input end of the clock selection circuit 201 .

[0070] Figure 4 Schematic diagram of a clock selection circuit provided in an embodiment of the present application. Figure 4 , including a clock selection circuit U22, a chip 1, a chip 2, a clock bus, a first capacitor C1 and a first power supply 3V3_PER. Pin 4 of the clock selection circuit U22 is connected to the clock bus, pin 6 of the clock selection circuit U22 is used to receive a control signal, and pin 5 of the clock selection circuit U22 is connected to the first power supply 3V3_PER. One end of the first capacitor C1 is connected to the other end of the first power supply 3V3_PER, and the other end of the first capacitor C1 is grounded. Pin 1 of the clock selection circuit U22 is connected to chip 1, pin 3 of the clock selection circuit U22 is connected to chip 2, and pin 2 of the clock selection circuit U22 is grounded.

[0071] The first capacitor C1 is used for decoupling and voltage stabilization. For example, the first capacitor C1 may have a specification of 100nF and a withstand voltage of 16V.

[0072] After the 6th pin of the clock selection circuit U22 receives the control signal output by the control circuit 203, if the control signal is a high level signal, the 4th pin of the clock selection circuit U22 is connected to the 1st pin. At this time, the chip 1 is connected to the clock bus through the clock selection circuit U22. If the control signal is a low level signal, the 4th pin of the clock selection circuit U22 is connected to the 3rd pin. At this time, the chip 2 is connected to the clock bus through the clock selection circuit U22.

[0073] The clock selection circuit provided in the embodiment of the present application can determine whether the first chip or the second chip is connected to the clock bus according to the control signal, thereby realizing the connection of multiple chips to the same bus. This avoids the situation where multiple geomagnetic sensor chips are provided in the camera and multiple groups of buses need to be provided to connect the corresponding geomagnetic sensor chips, thereby reducing the complexity of the internal circuit structure of the camera.

[0074] The data selection circuit 202 controls the geomagnetic sensor chip to be connected to the data bus. Figure 5 , the structure of the clock selection circuit 202 is described.

[0075] Figure 5 This is a schematic diagram of the structure of the data selection circuit provided in the embodiment of the present application. Figure 5 , the data selection circuit 202 may include: a first input terminal, a second input terminal, a third input terminal, a first output terminal, a second output terminal and a third output terminal, wherein,

[0076] A first input terminal of the data selection circuit 202 is connected to the bus circuit 204, a second input terminal of the data selection circuit 202 is connected to the control circuit 203, and a third input terminal of the data selection circuit 202 is connected to the second power supply circuit 207;

[0077] A first output terminal of the data selection circuit 202 is connected to the first chip 205 , a second output terminal of the data selection circuit 202 is connected to the second chip 206 , and a third output terminal of the data selection circuit 202 is grounded.

[0078] The first input end of the data selection circuit 202 may be a common end of an electronic single-pole double-throw switch, the first output end of the data selection circuit 202 may be one output end of the electronic single-pole double-throw switch, and the second output end of the data selection circuit 202 may be another output end of the electronic single-pole double-throw switch. The data selection circuit 202 may determine that the first input end of the data selection circuit 202 is connected to the first output end or the second output end according to the control signal output by the control circuit 203, so that the data bus in the bus circuit 204 is connected to the first chip 205 or the second chip 206.

[0079] The data bus is connected to a first input terminal of the data selection circuit 202 .

[0080] The second power supply circuit 207 includes a second capacitor and a second power supply, wherein one end of the second capacitor is connected to one end of the second power supply, the other end of the second capacitor is grounded, and the other end of the second power supply is connected to the third input end of the data selection circuit.

[0081] Figure 6 This is a schematic diagram of a data selection circuit provided in an embodiment of the present application. Figure 6 , including a data selection circuit U176, a chip 1, a chip 2, a data bus, a second capacitor C2 and a second power supply 3V3_PER. Pin 4 of the data selection circuit U176 is connected to the data bus, pin 6 of the data selection circuit U176 is used to receive a control signal, and pin 5 of the data selection circuit U176 is connected to the second power supply 3V3_PER. One end of the second capacitor C2 is connected to the other end of the second power supply 3V3_PER, and the other end of the second capacitor C2 is grounded. Pin 1 of the data selection circuit U176 is connected to chip 1, pin 3 of the data selection circuit U176 is connected to chip 2, and pin 2 of the data selection circuit U176 is grounded.

[0082] The second capacitor C2 is used for decoupling and voltage stabilization. For example, the specification of the second capacitor C2 can be 100nF and the withstand voltage can be 16V.

[0083] After the 6th pin of the data selection circuit U176 receives the control signal output by the control circuit 203, if the control signal is a high level signal, the 4th pin of the data selection circuit U176 is connected to the 1st pin. At this time, the chip 1 is connected to the data bus through the data selection circuit U176. If the control signal is a low level signal, the 4th pin of the data selection circuit U176 is connected to the 3rd pin. At this time, the chip 2 is connected to the data bus through the data selection circuit U176.

[0084] The data selection circuit provided in the embodiment of the present application can determine whether the first chip or the second chip is connected to the data bus according to the control signal, thereby realizing the connection of multiple chips to the same bus. This avoids the situation where multiple geomagnetic sensor chips are provided in the camera and multiple groups of buses need to be provided to connect the corresponding geomagnetic sensor chips, thereby reducing the complexity of the internal circuit structure of the camera.

[0085] The control circuit 203 is used to output a control signal to connect the bus circuit 204 to the first chip 206 or the second chip 207. Figure 7 , the structure of the control circuit 203 is explained.

[0086] Figure 7 This is a schematic diagram of the structure of the control circuit provided in the embodiment of the present application. Figure 7 The control circuit 203 may include: a control chip 301, a first resistor 302 and a second resistor 303, wherein:

[0087] One end of the first resistor 302 is connected to the control chip 301 , and the other end of the first resistor 302 is connected to the second input of the clock selection circuit 201 ;

[0088] One end of the second resistor 303 is connected to the control chip 301 , and the other end of the second resistor 303 is connected to the second input of the data selection circuit 202 .

[0089] Exemplarily, the resistance of the first resistor 301 and the second resistor 302 may be 10KΩ.

[0090] The control circuit 203 is specifically used for:

[0091] Control the first output terminal of the clock selection circuit 201 to be connected to the first chip 205, and control the first output terminal of the data selection circuit 202 to be connected to the first chip 205; or,

[0092] The second output terminal of the control clock selection circuit 201 is connected to the second chip 206 , and the second output terminal of the control data selection circuit 202 is connected to the second chip 206 .

[0093] The control chip 301 may be a main control chip of the camera and may be connected to the first resistor 302 and the second resistor 303 via a general-purpose input / output (GPIO) interface in the control chip 301 .

[0094] The control chip is specifically used to: output a control signal to the control circuit 204, so that the control circuit 204 controls the first chip 205 to connect with the bus circuit 204 through the clock selection circuit 201 and the data selection circuit 202 according to the control signal, or controls the second chip 206 to connect with the bus circuit 204 through the clock selection circuit 201 and the data selection circuit 202 according to the control signal.

[0095] The first resistor 302 and the second resistor 303 can be connected to the power supply of the chip 301 through the GPIO interface. In this way, the control signal output by the control circuit 203 can be a high-level signal in a normal state. That is, in a normal state, the control circuit 203 controls the first output end of the clock selection circuit 201 to be connected to the first chip 205, and controls the first output end of the data selection circuit 202 to be connected to the first chip 205. At this time, the camera can obtain data in the first chip 205 through the bus circuit 204.

[0096] When acquiring data in the second chip 206, the control signal output by the control chip 301 is a low level signal. The control circuit 203 controls the second chip 206 to communicate with the bus circuit 204 through the clock selection circuit 201 and the data selection circuit 202. The camera can acquire data in the second chip 206 through the bus circuit 204.

[0097] The control signal output by the control chip 301 can be controlled to be a high level signal or a low level signal through software configuration.

[0098] In actual application, one transmission control circuit can connect two geomagnetic sensor chips at the same time. The bus addresses of the two geomagnetic sensor chips are the same. If there are multiple geomagnetic sensor chips, multiple groups of selection circuits need to be set up, and one group of selection circuits includes a clock selection circuit and a data selection circuit. One group of selection circuits can connect two geomagnetic sensor chips at the same time. In this way, multiple chips can be connected to the same bus.

[0099] The control circuit provided in the embodiment of the present application can control the first chip or the second chip to be connected to the bus circuit according to the control signal, thereby realizing the connection of multiple chips to the same bus. This avoids the situation where multiple geomagnetic sensor chips are provided in the camera and multiple groups of buses need to be provided to connect the corresponding geomagnetic sensor chips, thereby reducing the complexity of the internal circuit structure of the camera.

[0100] Figure 8 This is a schematic diagram of a transmission control circuit for a camera provided in an embodiment of the present application. Figure 8 The transmission control circuit 200 for the camera also includes a third resistor 304, a fourth resistor 305, a fifth resistor 306 and a sixth resistor 307, wherein:

[0101] One end of the third resistor 304 is connected to the first output end of the clock selection circuit 201, and the other end of the third resistor 304 is connected to the power pin of the first chip 205;

[0102] One end of the fourth resistor 305 is connected to the second output end of the clock selection circuit 201, and the other end of the fourth resistor 305 is connected to the power pin of the second chip 206;

[0103] One end of the fifth resistor 306 is connected to the first output end of the data selection circuit 202, and the other end of the fifth resistor 306 is connected to the power pin of the first chip 205;

[0104] One end of the sixth resistor 307 is connected to the second output end of the data selection circuit 202 , and the other end of the sixth resistor 307 is connected to the power pin of the second chip 206 .

[0105] Exemplarily, the resistance values ​​of the third resistor 304 , the fourth resistor 305 , the fifth resistor 306 , and the sixth resistor 307 may be 10 KΩ.

[0106] The output signals of the clock selection circuit 201 and the data selection circuit 202 can be pulled up to the IO port power domain of the first chip 205 and the second chip 206 through the third resistor 304, the fourth resistor 305, the fifth resistor 306 and the sixth resistor 307. In this way, it can be ensured that all circuits can pull up to stabilize the signal after the switching is completed.

[0107] An embodiment of the present application provides a camera, including the transmission control circuit for the camera shown in the above embodiment.

[0108] Obviously, those skilled in the art can make various changes and modifications to the embodiments of the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the embodiments of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

[0109] In the present application, the term "include" and its variations may refer to non-restrictive inclusion; the term "or" and its variations may refer to "and / or". The terms "first", "second", etc. in the present application are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. In the present application, "plurality" refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B may mean: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the previously associated objects are in an "or" relationship.

Claims

1. A transmission control circuit for a camera, characterized in that: include: A clock selection circuit, a data selection circuit, a control circuit, a bus circuit, a first chip and a second chip, wherein: The input end of the clock selection circuit is connected to the control circuit and the bus circuit respectively, the input end of the data selection circuit is connected to the control circuit and the bus circuit respectively, the output end of the clock selection circuit is connected to the first chip and the second chip respectively, and the output end of the data selection circuit is connected to the first chip and the second chip respectively; The control circuit is used to control the first chip to be connected to the bus circuit through the clock selection circuit and the data selection circuit respectively, or to control the second chip to be connected to the bus circuit through the clock selection circuit and the data selection circuit respectively.

2. The circuit according to claim 1, characterized in that The clock selection circuit and the data selection circuit respectively include a first input terminal, a second input terminal and a third input terminal, wherein: The first input terminal of the clock selection circuit is connected to the bus circuit, the second input terminal of the clock selection circuit is connected to the control circuit, and the third input terminal of the clock selection circuit is connected to the first power supply circuit; The first input terminal of the data selection circuit is connected to the bus circuit, the second input terminal of the data selection circuit is connected to the control circuit, and the third input terminal of the data selection circuit is connected to the second power supply circuit.

3. The circuit according to claim 2, characterized in that The first power supply circuit includes a first capacitor and a first power supply, and the second power supply circuit includes a second capacitor and a second power supply, wherein: One end of the first capacitor is connected to one end of the first power supply, the other end of the first capacitor is grounded, and the other end of the first power supply is connected to the third input end of the clock selection circuit; One end of the second capacitor is connected to one end of the second power supply, the other end of the second capacitor is grounded, and the other end of the second power supply is connected to the third input end of the data selection circuit.

4. The circuit according to claim 3, characterized in that The clock selection circuit and the data selection circuit respectively include a first output terminal, a second output terminal and a third output terminal, wherein: The first output terminal of the clock selection circuit is connected to the first chip, the second output terminal of the clock selection circuit is connected to the second chip, and the third output terminal of the clock selection circuit is grounded; The first output terminal of the data selection circuit is connected to the first chip, the second output terminal of the data selection circuit is connected to the second chip, and the third output terminal of the data selection circuit is grounded.

5. The circuit according to any one of claims 1 to 4, characterized in that: The control circuit is specifically used for: Control the first output end of the clock selection circuit to be connected to the first chip, and control the first output end of the data selection circuit to be connected to the first chip; or, The second output end of the clock selection circuit is controlled to be connected to the second chip, and the second output end of the data selection circuit is controlled to be connected to the second chip.

6. The circuit according to any one of claims 1 to 4, characterized in that: The bus circuit includes a data bus and a clock bus, wherein: The clock bus is connected to the first input terminal of the clock selection circuit; The data bus is connected to a first input terminal of the data selection circuit.

7. The circuit according to any one of claims 1 to 4, characterized in that: The control circuit includes a control chip, a first resistor and a second resistor, wherein: One end of the first resistor is connected to the control chip, and the other end of the first resistor is connected to the second input of the clock selection circuit; One end of the second resistor is connected to the control chip, and the other end of the second resistor is connected to the second input of the data selection circuit.

8. The circuit according to claim 7, characterized in that The control chip is specifically used for: A control signal is output to the control circuit so that the control circuit controls the first chip to be connected to the bus circuit through the clock selection circuit and the data selection circuit according to the control signal, or controls the second chip to be connected to the bus circuit through the clock selection circuit and the data selection circuit according to the control signal.

9. The circuit according to any one of claims 1 to 4, characterized in that: The circuit further includes a third resistor, a fourth resistor, a fifth resistor and a sixth resistor, wherein: One end of the third resistor is connected to the first output end of the clock selection circuit, and the other end of the third resistor is connected to the power pin of the first chip; One end of the fourth resistor is connected to the second output end of the clock selection circuit, and the other end of the fourth resistor is connected to the power pin of the second chip; One end of the fifth resistor is connected to the first output end of the data selection circuit, and the other end of the fifth resistor is connected to the power pin of the first chip; One end of the sixth resistor is connected to the second output end of the data selection circuit, and the other end of the sixth resistor is connected to the power pin of the second chip.

10. A camera, characterized in that: A transmission control circuit for a camera comprising the transmission control circuit of any one of claims 1 to 9.

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