10-gigabit service board

Abstract

The utility model discloses a 10-gigabit business board, and belongs to the field of high-speed data information processing. The problem that the information processing and transmission capabilities of equipment and a system are insufficient is solved; according to the technical scheme, the device comprises a PCB, a P0 port and a front panel, a processor, a bridge piece, a 10-gigabit network card, an FPGA module and a BMC single-chip microcomputer are arranged on the PCB, the processor comprises a plurality of PCle3.0 interfaces, a plurality of UART serial ports and an RGMII interface, the processor is electrically connected with the BMC single-chip microcomputer through the UART serial ports, the P0 port is electrically connected with the BMC single-chip microcomputer, the P0 port is electrically connected with the bridge piece, and the front panel is electrically connected with the BMC single-chip microcomputer through the RGMII interface. The bridge chip is electrically connected with the BMC single-chip microcomputer through a GPIO interface. The BMC single-chip microcomputer comprises a plurality of GPIO interfaces, an ADC voltage conversion interface and an IIC bus. The utility model is applied to the business board.

Description

Technical Field

[0001] The utility model provides a 10G business board, belonging to the technical field of high-speed data information processing. Background Art

[0002] The 10G business card is a nationally industrialized, self-controllable 10G business module with small size, high integration and high performance. With the development of science and technology, the 10G business board will be applied in more fields, and will be expanded to 5G, edge computing, cloud computing and other industry businesses. The use of the place will be expanded from aviation, aerospace, workshop ships, etc. to various working environments with special environmental requirements. However, in the actual use of demanding operating environments, there are many equipment, and high-speed signal exchange between equipment is required frequently, the signal exchange speed is fast, and the throughput of big data is large, which cannot guarantee the absolute security of the information channel and the self-controllability of information equipment. Therefore, there is an urgent need to provide a 10G business board that can improve the information processing and transmission capabilities of equipment and systems. Utility Model Content

[0003] In order to solve the technical problems that the high-speed signal exchange between devices is frequent, the signal exchange speed is fast, the throughput of big data is large, and the absolute security of the information channel and the autonomous controllability of the information equipment cannot be guaranteed, the utility model proposes a 10 Gigabit business board, and the purpose is to ensure the security of the information channel and the autonomous controllability of the information equipment by improving the hardware structure of the 10 Gigabit business board or improving the combined connection of the hardware modules and / or circuits.

[0004] In order to solve the above technical problems, the technical solution adopted by the utility model is: a 10G business board, including a PCB circuit board, a P0 port and a front panel, wherein the PCB circuit board is provided with a processor, a bridge chip, a 10G network card, an FPGA module and a BMC microcontroller;

[0005] The processor includes several PCle3.0 interfaces, several UART serial ports and RGMII interfaces;

[0006] The PCle3.0 interface includes a plurality of PEU0 interfaces and a plurality of PEU1 interfaces;

[0007] The PEU0_0:7 interface of the PEU0 interface is electrically connected to the bridge chip via a bus;

[0008] The PEU0_8:15 interface of the PEU0 interface is electrically connected to the 10G network card through a bus.

[0009] The PEU1_0:7 interface of the PEU1 interface is electrically connected to the FPGA module via a bus;

[0010] The processor is electrically connected to the BMC microcontroller via a UART serial port;

[0011] The processor is electrically connected to the front panel via an RGMII interface;

[0012] The bridge chip is integrated with a plurality of GPIO interfaces, and the bridge chip is electrically connected to the front panel via the GPIO interfaces;

[0013] The FPGA module is electrically connected to the P0 port;

[0014] The 10 Gigabit network card is electrically connected to the front panel;

[0015] The P0 port is electrically connected to the BMC microcontroller;

[0016] The P0 port is electrically connected to the bridge chip;

[0017] The bridge chip is electrically connected to the BMC microcontroller via a GPIO interface;

[0018] The BMC single chip computer includes several GPIO interfaces, an ADC voltage conversion interface and an IIC bus.

[0019] Further, the slot identification interface on the P0 port is electrically connected to a GPIO interface on the BMC microcontroller;

[0020] The GPIO interface on the P0 port is electrically connected to a GPIO interface on the BMC microcontroller;

[0021] The IPMB interface on the P0 port is electrically connected to the IIC bus on the BMC microcontroller;

[0022] The indicator light on the P0 port is electrically connected to a GPIO interface on the BMC microcontroller;

[0023] The reset input terminal of the P0 port is electrically connected to a GPIO interface on the bridge chip.

[0024] Furthermore, a UART serial port on the processor is electrically connected to an RJ45 interface on the front panel after being externally connected to the first chip; another UART serial port on the processor is electrically connected to the BMC microcontroller.

[0025] Furthermore, the RGMII interface on the processor is electrically connected to a second chip, and the second chip is electrically connected to an RJ45 interface on the front panel.

[0026] Furthermore, the processor is integrated with several DDR4-3200 channels to support real-time encryption of DDR storage data.

[0027] Furthermore, the PEU1_8:15 interface of the PEU1 interface is electrically connected to the isolation card socket through a bus.

[0028] Furthermore, the USB interface on the front panel is electrically connected to the USB interface on the bridge chip; the reset interface on the front panel is electrically connected to a GPIO interface on the bridge chip; and the indicator light on the front panel is electrically connected to a GPIO interface on the bridge chip.

[0029] Furthermore, a DP interface is integrated on the bridge chip, and the DP interface is electrically connected to the VGA interface.

[0030] Furthermore, an I2C1 interface on the processor is connected to an external clock signal.

[0031] Furthermore, the FPGA module includes a JFM7K325T chip; the processor uses a Feiteng D2000 chip; the specific model of the bridge chip is a Feiteng X100 series chip; the 10 Gigabit network card uses a WX1820AL chip; and the specific model of the BMC microcontroller is a GD32F103 series.

[0032] Compared with the prior art, the utility model has the following beneficial effects: the utility model integrates components such as Feiteng D2000 processor, Feiteng X100 bridge chip, WX1820AL 10 Gigabit network card, RIO FPGA and GD32F103 single-chip microcomputer on a PCB circuit board; the processor is electrically connected to the FPGA module, bridge chip, 10 Gigabit network card and BMC single-chip microcomputer respectively; the BMC single-chip microcomputer is electrically connected to the bridge chip, thereby ensuring frequent high-speed signal exchange between devices, fast signal exchange speed and large throughput of big data, while ensuring absolute security of information channels and autonomous controllability of information equipment, solving the technical problems of high-speed transmission and security compatibility of big data, and improving the information processing and transmission capabilities of equipment and systems. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The utility model is further described below in conjunction with the accompanying drawings:

[0034] Figure 1 It is an axonometric drawing of the utility model;

[0035] Figure 2 It is a front view of the utility model;

[0036] Figure 3 It is an exploded view of the utility model;

[0037] Figure 4 This is the front device layout diagram of the utility model;

[0038] Figure 5 This is a principle block diagram of the utility model;

[0039] Figure 6 This is the main interface diagram of the processor of the utility model;

[0040] Figure 7 This is the DDR4 principle diagram of the utility model;

[0041] Figure 8 This is the main interface diagram of the bridge piece of the utility model;

[0042] Fig. 9 This is a schematic diagram of the bridge chip of the utility model realizing the power management function;

[0043] Fig.10 This is the principle diagram of YT8521SH-CA of the utility model;

[0044] Fig.11 This is the schematic diagram of the SRIO interface of the utility model;

[0045] Fig.12 This is the schematic diagram of the low-speed interface of the utility model;

[0046] Fig.13 A topological diagram of the clock signal of the utility model;

[0047] Fig.14 This is the topological diagram of the power supply circuit of the utility model;

[0048] In the figure: 1 is the first connector, 2 is the FPGA module, 3 is the BMC microcontroller, 4 is the 10 Gigabit network card, 5 is the second connector, 6 is the bridge chip, 7 is the processor, 8 is the hard disk, 9 is the button, 10 is the indicator light, 11 is the serial port, 12 is the network port, 13 is the optical port, 14 is the USB port, and 15 is the switch. DETAILED DESCRIPTION

[0049] In the present invention, unless otherwise specified, the directional words used, such as "up, down, top, bottom", usually refer to the directions shown in the drawings, or to the components themselves in the vertical, perpendicular or gravity directions; similarly, for ease of understanding and description, "inside and outside" refer to the inside and outside relative to the outline of each component itself, but the above-mentioned directional words are not used to limit the present invention.

[0050] like Figures 1 to 14As shown, the utility model provides a 10 Gigabit service board, including a PCB circuit board, a P0 port and a front panel, the PCB circuit board is integrated with a processor 7, a bridge chip 6, a 10 Gigabit network card 4, an FPGA module 2 and a BMC microcontroller 3; the processor 7 adopts Feiteng's Tengrui D2000 / 8 domestic processor 7, the main frequency is 2.0GHz, the processor 7 peripherals 34 PCIE3.0 interfaces, including 2 X16 (each X16 can be split into 2 X8), 2 X1, the processor 7 also includes 2 UART serial ports 11 and an RGMII interface. The PCIE3.0 interface includes several PEU0 interfaces and several PEU1 interfaces. The PEU0_0:7 interface of the PEU0 interface is electrically connected to the bridge chip 6 to realize 4 USB2.0 interfaces and 2 SATA interfaces, wherein one USB2.0 interface is electrically connected to the USB interface 14 on the front panel, and the SATA interface is electrically connected to the onboard mSATA connector to expand 128GB storage; the PEU0_8:15 interface of the PEU0 interface is electrically connected to the 10 Gigabit network card 4, and the 10 Gigabit network card 4 adopts the WX1820A chip to realize 1 10 Gigabit Ethernet; the 10 Gigabit network card 4 is integrated with an SFP module, and the 10 Gigabit network card 4 is electrically connected to the SFP+ interface on the front panel through the SFP module interface; the PEU1_0:7 interface of the PEU1 interface is externally connected to the electronic JFM7K325T FPGA to realize 1 SRIO communication; the PEU1_8:15 interface of the PEU1 interface is electrically connected to the isolation card socket. One UART serial port 11 on processor 7 converts the voltage level from 1.8V to 3.3V through the level converter NCA9306 of Nanochip Micro, and is electrically connected to the BMC microcontroller 3 to realize the reporting management function of the BMC microcontroller 3. Another UART serial port 11 on processor 7 converts the voltage level from 1.8V to 3.3V through the level converter NCA9306 of Nanochip Micro, and is connected to an RJ45 interface on the front panel after being externally connected to the RS232 interface chip SIT3232 of Xinlite, as a debugging serial port. The RGMII interface on processor 7 is externally connected to the YT8521 PHY chip of Yutai Microelectronics to realize one Gigabit Ethernet. Two DDR4-3200 channels are integrated on processor 7, which supports real-time encryption of DDR storage data. DR4 uses Changxin Storage's DDR4 CXDQ3A8AM-WG. Each channel can connect to 8 DDR4 chips and 1 ECC chip, and dual channels can realize 16GB of DDR4. An I2C1 interface on processor 7 converts the 1.8V level into 3.3V through Nanochip's level converter NCA9306, and is externally connected to the AIP1307 clock chip of China Electronics 58 Institute to realize the RTC real-time clock function.

[0051] The BMC microcontroller 3 integrates multiple GPIO interfaces, ADC voltage conversion interfaces, UART serial port 11 and IIC bus. The BMC microcontroller 3 uses the GD32F103 series chip to realize voltage monitoring, motherboard temperature monitoring and fan control. The BMC microcontroller 3 is electrically connected to the P0 port, the slot identification interface on the P0 port is electrically connected to a GPIO interface on the BMC microcontroller 3, the GPIO interface on the P0 port is electrically connected to a GPIO interface on the BMC microcontroller 3, the IPMB interface on the P0 port is electrically connected to the IIC bus on the BMC microcontroller 3, the indicator light on the P0 port is electrically connected to a GPIO interface on the BMC microcontroller 3, and a GPIO interface on the BMC microcontroller 3 is electrically connected to a GPIO interface on the bridge chip 6. The voltage monitoring device monitors the voltage on the PCB through the ADC voltage conversion interface, and the temperature detection device realizes PCB board temperature monitoring and fan control through a GPIO interface on the BMC microcontroller 3.

[0052] The bridge chip 6 has an integrated DP interface, which is converted into a VGA interface by an external LT8711V of Longxun Semiconductor for extended display. The bridge chip 6 uses the Feiteng X100 series chip. The reset input end of the P0 port is electrically connected to a GPIO interface on the bridge chip 6, and an I2C0 bus on the bridge chip 6 is electrically connected to an I2C1 bus on the processor 7.

[0053] Among them, Figure 4 As described, the PCB circuit board of the utility model integrates a first connector 1, an FPGA module 2, a BMC microcontroller 3, a 10 Gigabit network card 4, a second connector 5, a bridge chip 6, a processor 7, a hard disk 8, a button 9, an indicator light 10, a serial port 11, a network port 12, an optical port 13, a USB interface 14, and a switch 15.

[0054] The processor 7 in the embodiment of the utility model is based on the domestically produced processor Tengrui D2000 / 8 of Feiteng, and its specifications are as follows:

[0055] Ⅰ. Functional indicators

[0056] Compatible with ARM v8 architecture, supports 64-bit and 32-bit instructions; compatible with ARM v8 virtualization architecture, supports the industry's mainstream KVM and Xen virtual machines; supports single-precision and double-precision floating-point operation instructions; supports ASIMD processing instructions; supports processor security architecture PSPA1.0.

[0057] II. Structural indicators

[0058] Integrates 8 FTC663 cores;

[0059] L2 Cache: 2MB in each cluster, 8MB in total;

[0060] L3 Cache: Divided into 8 banks, totaling 4MB;

[0061] Integrated 2 DDR4-3200Mbps;

[0062] Integrated 34 Lanes PCIe 3.0 interface: 2 X16 (each can be split into 2 X8), 2 X1;

[0063] Integrated 2 Gigabit Ethernet interfaces (RGMII), supporting 10 / 100 / 1000Mbps self-adaptation;

[0064] Integrated 1 SD card controller, compatible with SD 2.0 specification;

[0065] Integrated 4 UARTs, 1 LPC Master, 32 GPIOs, 4 I2Cs, 1 QSPI, 2 general SPIs, 3 CANs, 2 WDTs, 16 external interrupts;

[0066] Integrated temperature sensor;

[0067] Integrated 128KB On Chip Memory.

[0068] III. Power Management

[0069] Support power off;

[0070] Support dynamic frequency adjustment;

[0071] Support standby and hibernation.

[0072] IV. Interface settings.

[0073] The supporting chip of the Feiteng X100 series Feiteng processor in the embodiment of the utility model can be used with the Feiteng series processor to form a complete solution for desktops, all-in-one computers or notebooks; it can also be used as a display chip to build an independent graphics card for various terminal and server application scenarios. The main indicators of the Feiteng X100 bridge chip are as follows:

[0074] Integrated 1 low-power GPU, main frequency 400MHz;

[0075] Integrates 1 VideoDecoder, supports 4K@30fps decoding rate, and supports H.264 / 265, MPEG4, MPEG2, and other mainstream encoding formats;

[0076] Integrated 3 DisplayPort1.4 display interfaces, two of which support a maximum resolution of 3840×2160@60Hz, and one supports a maximum resolution of 1366×768@60Hz;

[0077] Integrated 4-channel I2S, supports high-definition audio playback, 3 of which are fixed to the DisplayPort display interface, and another 1 can be connected to the I2S Codec to perform recording and playback functions;

[0078] Integrated with 1 64-bit DDR4 / LPDDR4 video memory controller, supporting video memory capacity up to 8GB and maximum rate of 2666MT / s;

[0079] Integrated 1-way X16 PCIe3.0 uplink interface, 8-way PCIe3.0 downlink interface, including 2-way X2 and 6-way X1, of which 2-way X1 is multiplexed with SATA3.0 interface;

[0080] Integrated 4-way SATA3.0 interface;

[0081] Integrated 8 independent USB3.1 Gen1 interfaces;

[0082] Integrates two SD / SDIO / eMMC controllers, supporting SD3.0, SDIO3.0 and eMMC5.0 protocol specifications;

[0083] Integrates 4 UARTs, 96 GPIOs, 8 MIOs (configurable as UART, I2C, PWM modes), 4 PWMs, 1 QSPI, 2 general SPI Masters, 3 SMBus controllers, 2 CAN controllers; 2 single-ended clock drive interfaces;

[0084] Integrate the whole machine control functions, including power on and off control, reset control, low power consumption control, etc.

[0085] Integrated temperature sensor can monitor the on-chip temperature in real time with an accuracy of ±5°C.

[0086] When Feiteng X100 implements the power management function, Feiteng X100 uses a fixed interface to control the power-on and power-off timing and external device reset control. This function is used to implement the power management of the CPU processor.

[0087] The 10 Gigabit network card 4 in the embodiment of the utility model is the WX1820AL 10 Gigabit network chip independently designed by Beijing Netxun, which can meet the latest network requirements of enterprise data centers. It is applied on servers and supports the hypervisor data diversion and sorting function. By effectively balancing the network load on the CPU processor core, it improves data throughput and CPU processor utilization, and shows excellent performance in multi-CPU processor systems. The WX1820AL processor has excellent noise immunity and also supports 300-meter fiber optic connections. It is suitable for servers and high-end devices. It can easily integrate any PCI Express X8 into a 10 Gigabit network and optimizes performance, so that system I / O is no longer a bottleneck for high-end network applications. The WX1820AL processor comes with two fully integrated 10 Gigabit Ethernet media access control (MAC) and SFP+ ports. It is an ideal solution for deploying multiple networks and deploying critical network application environments on high-performance servers. The main technical indicators of the 10 Gigabit network card 4 are as follows:

[0088]

[0089]

[0090]

[0091] In the embodiment of the utility model, the FPGA module 2 adopts JFM7K325T, which belongs to the JFM7 series products. It is a high-performance FPGA with field programmable characteristics. The JFM7 series FPGA integrates powerful and flexibly configured programmable resources to realize input and output interfaces, general digital logic, memory, digital signal processing, clock management and other functions. At the same time, it provides abundant dedicated clock and wiring resources for use in complex and high-speed digital logic circuits. It can be widely used in communications, information processing, industrial control, data centers, instrumentation, medical instruments, artificial intelligence and autonomous driving. The JFM7K325T product includes CLB modules that can be used to realize conventional digital logic and distributed RAM. In addition, it also includes programmable modules such as I / O, blockRAM, DSP, MMCM, GTX, etc., which can easily realize various special applications. The specific functions are described in the following table:

[0092]

[0093] The functional interface design of this utility model is as follows:

[0094] Ⅰ. Memory Circuit Design

[0095] The DDR controller and DDR PHY integrated on the processor 7 are the off-chip large-capacity storage control components in the processor, responsible for managing the main memory space of the entire chip. DDR4 uses Hefei Changxin CXDQ3A8AM-WG, 8Gb (1GbX8) each channel can connect 8 DDR4, 1 ECC, two channels total 16GB. Its main features are as follows:

[0096] Support DDR4 and LPDDR4 protocols;

[0097] Support DDR4UDIMM, SODIMM, RDIMM, LRDIMM;

[0098] Supported device types:

[0099] DDR4: x4, x8, x16; LPDDR4: x16, x32;

[0100] Maximum supported rate:

[0101] DDR4—3200MT / s; LPDDR4—3200MT / s;

[0102] Supported interface voltages:

[0103] DDR4—1.2V; LPDDR4—1.1V;

[0104] Support 1 / 2 / 4 Ranks;

[0105] Supports two DDR access channels, each channel contains 64 data bits and 8 ECC check bits. Note: Due to the address mapping method of the interconnection network, when using two DDR channels, the storage capacity on the two channels must be consistent;

[0106] Supports multiple low-power features, including DRAM self-refresh, DDR controller clock shutdown, and power shutdown;

[0107] Support 3DS and DBI in DDR4 mode;

[0108] Support timing parameter combinations of multiple frequency points;

[0109] Supports DDR4 and LPDDR4 devices in various organizational forms;

[0110] The supported DDR4 device parameter combinations are detailed in the following table:

[0111]

[0112] Ⅱ. Main interfaces of Feiteng X100 bridge chip:

[0113] 1) USB interface

[0114] X100 integrates 8 USB host controllers and supports 8 independent USB3.1 Gen1 interfaces. It is compatible with xHCI1.0 specification, USB3.1 Gen1 specification and USB2.0 specification; it supports USB3.1 Gen1 ultra-high-speed devices and USB2.0 high-speed, full-speed and low-speed devices. Through this USB control, it realizes an external USB2.0 interface to the front panel.

[0115] 2) SATA interface

[0116] X100 integrates 4 interfaces compatible with SATA3.0 specification, of which 2 are multiplexed with PCIeX1 and 1 is multiplexed with DisplayPort X1. The four interfaces share a SATA controller and are compatible with AHCI1.3 and 1.31 specifications. It can be connected to devices that comply with SATA specifications through the SATA interface and M.2 interface (B key / M key), supporting the connection of 1.5Gb / s, 3.0Gb / s, and 6.0Gb / s SATA devices, with a peak transfer rate greater than 500MB / s. This controller interacts with storage devices through a register interface compatible with the SATA AHCI host adapter. The host software follows relevant standards and conventions when accessing the register interface, and follows standard command protocol conventions. A 1-way SATA interface is implemented through this SATA controller as an onboard MSATA connector for onboard storage.

[0117] 3) Display interface

[0118] Feiteng X100 integrates 3 DisplayPort1.4 HBR2 display interfaces, of which two are 4Lane and support up to 3840×2160@60Hz, and one is 1Lane and supports up to 1366×768@60Hz. DisplayPort uses differential signals to implement high-bandwidth bus interfaces, supporting the output of video and audio signals from the X100 chip; through the first DP controller, it is converted into a VGA signal through the LT8711V video processing chip of Longxun Semiconductor for extended display.

[0119] III. SRIO interface

[0120] FPGA module 2 uses JFM7K325T chip. This FPGA has 1 PCIE 2.1 hard core, which is connected to the Feiteng D2000 processor through this IP core. The FPGA side is used as the EndPort of PCIE, and the CPU processor side is configured as the RC mode of PCIE. At the same time, this FPGA has 1 GTX channel, which realizes the external Serial RapidIO interface through the internal SRIO IP. The PEU1 controller of D2000 is configured with two X8 modes, and connected to two JFM7K325T respectively to realize 1 X1 mode Serial RapidIO interface.

[0121] IV. Low-speed interface

[0122] The D2000 processor has 4 UART controllers with an interface level of 1.8V COMS; UART1 converts 1.8V level to 3.3V through NCA9306 of Nanochip Microelectronics, and is connected to the RS232 interface chip SIT3232 of Xinlite as a debugging serial port. UART3 converts 1.8V level to 3.3V through NCA9306 of Nanochip Microelectronics, and is interconnected with BMC microcontroller 3 to realize BMC reporting management function; The D2000 processor has 4 IIC controllers with an interface level of 1.8V COMS; I2C1 converts 1.8V level to 3.3V level through NCA9306 of Nanochip Microelectronics, and is connected to the real-time clock chip AIP1307 of China Electronics Technology Group Corporation 58 Institute to realize RTC clock function; The D2000 processor has a QSPI controller with an interface level of 1.8V COMS, and uses SPI FLASHGD25LQ128 to realize the BIOS boot program.

[0123] The required clock model and parameters of the clock signal of the utility model are as follows:

[0124]

[0125] The total power consumption of this utility model is about 65W, and the power consumption table of the product is as follows:

[0126]

[0127] Regarding the specific structure of the utility model, it should be explained that the connection relationship between the various component modules adopted in the utility model is definite and feasible. Except for special instructions in the embodiments, the specific connection relationship can bring corresponding technical effects and solve the technical problems raised by the utility model without relying on the execution of corresponding software programs. The components, modules, models of specific components and the connection methods between each other appearing in the utility model, as well as the conventional use methods and expected technical effects brought about by the above-mentioned technical features, except for specific instructions, all belong to the disclosed contents in patents, journal articles, technical manuals, technical dictionaries, and textbooks that can be obtained by technical personnel in this field before the application date, or belong to the existing technologies such as conventional technologies and common knowledge in this field, and there is no need to elaborate, so that the technical solution provided in this case is clear, complete and feasible, and the corresponding physical products can be reproduced or obtained according to the technical means.

[0128] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the utility model, rather than to limit it. Although the utility model has been described in detail with reference to the aforementioned embodiments, ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not make the essence of the corresponding technical solution deviate from the scope of the technical solution of the embodiments of the utility model.

Claims

1. A 10G service board, characterized in that: It comprises a PCB circuit board, a P0 port and a front panel, wherein the PCB circuit board is provided with a processor (7), a bridge chip (6), a 10 Gigabit network card (4), an FPGA module (2) and a BMC single-chip computer (3); The processor (7) includes a plurality of PCle3.0 interfaces, a plurality of UART serial ports (11) and an RGMII interface; The PCle3.0 interface includes a plurality of PEU0 interfaces and a plurality of PEU1 interfaces; The PEU0_0:7 interface of the PEU0 interface is electrically connected to the bridge chip (6) via a bus; The PEU0_8:15 interface of the PEU0 interface is electrically connected to the 10 Gigabit network card (4) via a bus. The PEU1_0:7 interface of the PEU1 interface is electrically connected to the FPGA module (2) via a bus; The processor (7) is electrically connected to the BMC single chip computer (3) via a UART serial port (11); The processor (7) is electrically connected to the front panel via an RGMII interface; The bridge chip (6) is integrated with a plurality of GPIO interfaces, and the bridge chip (6) is electrically connected to the front panel via the GPIO interfaces; The FPGA module (2) is electrically connected to the P0 port; The 10 Gigabit network card (4) is electrically connected to the front panel; The P0 port is electrically connected to the BMC single chip computer (3); The P0 port is electrically connected to the bridge plate (6); The bridge chip (6) is electrically connected to the BMC single chip computer (3) via a GPIO interface; The BMC single chip computer (3) comprises a plurality of GPIO interfaces, an ADC voltage conversion interface and an IIC bus.

2. The 10G service board according to claim 1, characterized in that: The slot identification interface on the P0 port is electrically connected to a GPIO interface on the BMC microcontroller (3); The GPIO interface on the P0 port is electrically connected to a GPIO interface on the BMC single chip computer (3); The IPMB interface on the P0 port is electrically connected to the IIC bus on the BMC microcontroller (3); The indicator light on the P0 port is electrically connected to a GPIO interface on the BMC microcontroller (3); The reset input terminal of the P0 port is electrically connected to a GPIO interface on the bridge chip (6).

3. The 10G service board according to claim 1, characterized in that: A UART serial port (11) on the processor (7) is electrically connected to an RJ45 interface on the front panel after being externally connected to the first chip; another UART serial port (11) on the processor (7) is electrically connected to the BMC single chip computer (3).

4. The 10G service board according to claim 1, characterized in that: The RGMII interface on the processor (7) is electrically connected to the second chip, and the second chip is electrically connected to an RJ45 interface on the front panel.

5. The 10G service board according to claim 1, characterized in that: The processor (7) is integrated with a plurality of DDR4-3200 channels, supporting real-time encryption of DDR storage data.

6. The 10G service board according to claim 1, characterized in that: The PEU1_8:15 interface of the PEU1 interface is electrically connected to the isolation card socket through a bus.

7. The 10G service board according to claim 1, characterized in that: The USB interface (14) on the front panel is electrically connected to the USB interface (14) on the bridge chip (6); the reset interface on the front panel is electrically connected to a GPIO interface on the bridge chip (6); and the indicator light on the front panel is electrically connected to a GPIO interface on the bridge chip (6).

8. The 10G service board according to claim 1, characterized in that: The bridge chip (6) is integrated with a DP interface, and the DP interface is electrically connected to the VGA interface.

9. The 10G service board according to claim 1, characterized in that: An I2C1 interface on the processor (7) is connected to an external clock signal.

10. The 10G service board according to claim 1, characterized in that: The FPGA module (2) includes a JFM7K325T chip; the processor (7) uses a Feiteng D2000 chip; the bridge chip (6) is a Feiteng X100 series chip; the 10 Gigabit network card (4) uses a WX1820AL chip; and the BMC microcontroller (3) is a GD32F103 series chip.

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