Semiconductor packaging structure
By designing grooves on the first substrate of the semiconductor package structure to accommodate the first electronic component, the problem of difficulty in joining the upper and lower plates in the prior art is solved, and higher packaging structure flexibility and yield are achieved, and the heat dissipation performance is improved.
Patent Information
- Application Number
- CN202421383203.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-06-17
- Publication Date
- 2025-04-18
- Estimated Expiration
- 2034-06-17
AI Technical Summary
The existing semiconductor packaging structures have different color problems and yield losses in the process of putting the upper and lower plates, and the bonding of the upper and lower plates is difficult, which affects the heat dissipation performance of the packaging layer.
A semiconductor package structure is designed, wherein the first substrate has grooves for accommodating the first electronic component, providing an additional thickness margin, and ensuring effective bonding of the upper and lower plates through the design of the electrical connection and the packaging layer.
By increasing the storage space between the substrates, the problem of the inability to bond the upper and lower plates is solved, the flexibility and yield of the packaging structure are improved, and the heat dissipation performance of the packaging layer is improved.
Smart Images
Figure CN222775309U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to a semiconductor packaging structure. Background Art
[0002] See also Figure 1 The prior art currently wants to place components [such as but not limited to integrated passive devices (IPDs) and land side capacitors (LSCs)] on the upper board 2 (such as an interposer, SI) of a hybrid bonded package-on-package (HBPOP) 1. The current packaging structure requires design and verification of the process for placing components on the upper board 2, and also requires additional tools (increasing costs). For example, the process includes: for the upper plate 2, first bonding the first solder ball 3, then performing a cutting process to obtain a singulated upper plate 2, and placing the singulated upper plate 2 in a tray; for the lower plate 4 (for example, a wafer), first performing a grinding process to flatten the upper surface of the lower plate 4, performing a flip chip bonding (FCB) process to bond the first electronic component 5 to the lower plate 4, and filling the bottom filling layer 6; then performing a thermal compression bonding (TCB, Thermal Compression Bonding) process to bond the upper plate 2 to the lower plate 4 to form a packaging layer 7, for example, performing an FCB process to bond the second electronic component 8 to the upper plate 2 to form a second solder ball 9, and performing a cutting process to obtain a singulated HBPOP 1.
[0003] Since the pads of IPDs may have different colors during the packaging process (because they undergo many thermal processes before placement, such as reflow and baking, and the copper surface is easily oxidized), the substrate design needs to consider gold plating of the bump pads (not easily oxidized by heat), which will increase the cost. In addition, the solder resist opening of the existing bump pads is too small, which may cause gold plating leakage and yield loss. In addition, placing components above the upper plate 2 is not conducive to the subsequent heat dissipation structure design. Therefore, it is hoped that this structure can be improved.
[0004] See also Figure 2 In the prior art, the second electronic component 8 can be completed on the same surface as the first solder ball 3 during the semi-finished process of the upper plate 2 (that is, it can be completed at the beginning of the process after unpacking, and the oxidation effect is relatively small), and then the upper and lower plates are assembled. However, due to the stacking of electronic components on both sides, the ball height of the first solder ball 3 is insufficient and cannot be joined to the upper plate 2 and the lower plate 4. Utility Model Content
[0005] In view of the problems existing in the related art, the purpose of the present invention is to provide a semiconductor packaging structure to at least increase the accommodation space between substrates.
[0006] To achieve the above-mentioned purpose, the utility model provides a semiconductor packaging structure, comprising: a first substrate and a second substrate electrically connected, the first substrate having a first surface facing the second substrate and a second surface facing away from the second substrate, wherein the first substrate has a groove, the groove is recessed from the first surface toward the second surface; and at least one first electronic component is located in the groove and electrically connected to the second substrate. The surface of the first electronic component facing the first substrate and the surface facing the second substrate are staggered with the first surface.
[0007] In some embodiments, a sidewall of the at least one first electronic component overlaps with a sidewall of the groove in a horizontal direction.
[0008] In some embodiments, the semiconductor package structure further includes: an electrical connector for electrically connecting the first substrate and the second substrate, and a side wall of at least one first electronic component overlaps with the electrical connector in a horizontal direction.
[0009] In some embodiments, a surface of the at least one first electronic component facing the second substrate does not extend beyond a surface of the first substrate adjacent to the second substrate.
[0010] In some embodiments, the semiconductor packaging structure further includes: a packaging layer located between the first substrate and the second substrate, and a portion of the packaging layer fills the groove.
[0011] In some embodiments, the encapsulation layer encapsulates at least one first electronic component.
[0012] In some embodiments, the semiconductor package structure further includes: a first bottom filling layer located between the at least one first electronic component and the first substrate.
[0013] In some embodiments, the first underfill layer is encapsulated by the encapsulation layer.
[0014] In some embodiments, the first underfill layer covers at least a portion of a sidewall of the at least one first electronic component.
[0015] In some embodiments, a side surface of the encapsulation layer is aligned with a side surface of the first substrate and a side surface of the second substrate.
[0016] In some embodiments, the semiconductor package structure further includes: a second electronic component located between the at least one first electronic component and the second substrate, and the second electronic component is electrically connected to the second substrate.
[0017] In some embodiments, the encapsulation layer encapsulates the second electronic component.
[0018] In some embodiments, a portion of the encapsulation layer is located between the at least one first electronic component and the second electronic component.
[0019] In some embodiments, the semiconductor package structure further includes: a second bottom filling layer located between the second electronic component and the second substrate.
[0020] In some embodiments, the second underfill layer is encapsulated by the encapsulation layer.
[0021] In some embodiments, the second underfill layer covers at least a portion of a sidewall of the second electronic component.
[0022] An embodiment of the present application also provides a semiconductor packaging structure, comprising: a first substrate and a second substrate electrically connected, the first substrate having a first surface facing the second substrate, and a second surface facing away from the second substrate, wherein the first substrate has a groove, the groove being recessed from the first surface toward the second surface; and a plurality of first electronic components located in the groove and electrically connected to the second substrate, the surfaces of the plurality of first electronic components facing the second substrate having different heights.
[0023] In some embodiments, the plurality of first electronic components do not extend beyond a top surface of the recess.
[0024] In some embodiments, the semiconductor packaging structure further includes: a second electronic component located between the plurality of first electronic components and the second substrate, the second electronic component electrically connected to the second substrate; an electrical connector connecting the first substrate and the second substrate, the second electronic component overlapping the electrical connector in a horizontal direction.
[0025] In some embodiments, the electrical connectors are connected to portions of the first substrate located on both sides of the groove.
[0026] The beneficial technical effects of the utility model are:
[0027] The first substrate of the present application is provided with a groove for accommodating the first electronic component, providing a margin for the thickness of the first electronic component, and there is no need to worry about the problem that the upper and lower plates cannot be joined as in the prior art. On the basis of ensuring that the first substrate and the second substrate can be joined, flexibility is provided for the selection of the thickness of the first electronic component. BRIEF DESCRIPTION OF THE DRAWINGS
[0028] Figure 1 A prior art hybrid bonded package-on-package is shown.
[0029] Figure 2 Some other embodiments of the prior art hybrid package-on-package are shown.
[0030] Figure 3 A semiconductor package structure according to an embodiment of the present application is shown.
[0031] Figure 4 Shown with Figure 3 Semiconductor package structures according to different embodiments.
[0032] Figure 5 A first substrate and a second substrate are shown.
[0033] Figure 6 A first substrate is shown bonded to a second substrate.
[0034] Figure 7 Shown with Figure 3 , Figure 4 Semiconductor packages according to various embodiments.
[0035] Figure 8 Shows Figure 3 , Figure 4 A simplified structural diagram of the embodiment shown.
[0036] Fig. 9 Shows Figure 7 A simplified structural diagram of the embodiment shown.
[0037] Fig.10 A bottom view of the first substrate is shown.
[0038] Fig.11 A prior art solution for a chip die is shown.
[0039] Fig.12 A technical solution for 3D packaging of stacked chips is shown.
[0040] Fig.13 A carrier core layer is shown.
[0041] Fig.14 The formation of a first metal layer is shown.
[0042] Fig.15 The formation of a first dielectric layer is shown.
[0043] Fig.16 The formation of a first wiring layer is shown.
[0044] Fig.17 The formation of a second dielectric layer is shown.
[0045] Fig.18 Removal of the carrier core layer is shown.
[0046] Fig.19 The formation of a second wiring layer and pads is shown.
[0047] Fig. 20 The formation of a solder resist layer is shown.
[0048] Fig.21 Etching away the first metal layer is shown. DETAILED DESCRIPTION
[0049] In order to better understand the spirit of the embodiments of the present application, some preferred embodiments of the present application are further described below.
[0050] The embodiments of the present application will be described in detail below. In the full text of the present application specification, the same or similar components and components with the same or similar functions are represented by similar reference numerals. The embodiments of the accompanying drawings described herein are illustrative, graphical, and are used to provide a basic understanding of the present application. The embodiments of the present application should not be interpreted as limiting the present application.
[0051] As used herein, the terms "substantially," "substantially," "essentially," and "about" are used to describe and account for small variations. When used in conjunction with an event or circumstance, the terms may refer to instances where the event or circumstance occurred precisely as well as instances where the event or circumstance occurred very approximately.
[0052] In this specification, unless otherwise specified or limited, relative terms such as "central", "longitudinal", "lateral", "front", "rear", "right", "left", "inner", "outer", "lower", "higher", "horizontal", "vertical", "above", "below", "above", "below", "top", "bottom" and their derivative terms (such as "horizontally", "downwardly", "upwardly", etc.) should be interpreted as referring to the directions described in the discussion or depicted in the drawings. These relative terms are only used for convenience of description and do not require that the present application be constructed or operated in a specific direction.
[0053] For convenience of description, “first”, “second”, “third”, etc. may be used herein to distinguish different components in one figure or a series of figures. “First”, “second”, “third”, etc. are not intended to describe the corresponding components.
[0054] Figure 3 The semiconductor package structure 100 according to an embodiment of the present application is shown, comprising: a first substrate 11 and a second substrate 12 electrically connected, the first substrate 11 having a first surface 111 ( Figure 3 The lower surface shown), and the second surface 112 facing away from the second substrate 12 ( Figure 3 The first substrate 11 has a groove 110, the groove 110 is recessed from the first surface 111 to the second surface 112; and at least one first electronic component 21 is located in the groove 110 and is electrically connected to the second substrate 12, and the surface 212 ( Figure 3 The upper surface shown) and the surface 211 facing the second substrate 12 ( Figure 3The first substrate 11 of the present application is provided with a groove 110 for accommodating the first electronic component 21, providing a margin for the thickness of the first electronic component 21, and there is no need to worry about the problem that the upper and lower plates cannot be joined as in the prior art. On the basis of ensuring that the first substrate 11 and the second substrate 12 can be joined, flexibility is provided for the selection of the thickness of the first electronic component 21.
[0055] In some embodiments, a sidewall of the at least one first electronic component 21 overlaps with a sidewall of the groove 110 in a horizontal direction.
[0056] In some embodiments, the semiconductor package structure 100 further includes an electrical connector 30 (e.g., a solder ball) for electrically connecting the first substrate 11 and the second substrate 12, and the sidewall of at least one first electronic component 21 overlaps with the electrical connector 30 in the horizontal direction. Figure 3 The lower surface 211 is shown to extend beyond the first surface 111 of the first substrate 11 .
[0057] In some embodiments, a surface 211 of the at least one first electronic component 21 facing the second substrate 12 does not extend beyond the first face 111 of the first substrate 11 adjacent to the second substrate 12 .
[0058] In some embodiments, the semiconductor package structure 100 further includes: a package layer 40 located between the first substrate 11 and the second substrate 12 , and a portion of the package layer 40 is filled in the groove 110 .
[0059] In some embodiments, the encapsulation layer 40 encapsulates at least one first electronic component 21 .
[0060] In some embodiments, the semiconductor package structure 100 further includes: a first bottom filling layer 51 located between the at least one first electronic component 21 and the first substrate 11 .
[0061] In some embodiments, the first underfill layer 51 is encapsulated by the encapsulation layer 40 .
[0062] In some embodiments, the first underfill layer 51 covers at least a portion of a sidewall of the at least one first electronic component 21 .
[0063] In some embodiments, the side surfaces of the encapsulation layer 40 are aligned with the side surfaces of the first substrate 11 and the second substrate 12 .
[0064] In some embodiments, the semiconductor package structure 100 further includes: a second electronic component 22, located between at least one first electronic component 21 and the second substrate 12, and the second electronic component 22 is electrically connected to the second substrate 12. The first substrate 11 and the second substrate 12 of the embodiment of the present application can accommodate the stacked first electronic component 21 and the second electronic component 22, while avoiding the problem of the upper and lower boards being unable to be joined in the prior art.
[0065] In some embodiments, the packaging layer 40 encapsulates the second electronic component 22 .
[0066] In some embodiments, a portion of the encapsulation layer 40 is located between the at least one first electronic component 21 and the second electronic component 22 .
[0067] In some embodiments, the semiconductor package structure 100 further includes a second bottom filling layer 52 located between the second electronic component 22 and the second substrate 12 .
[0068] In some embodiments, the second underfill layer 52 is encapsulated by the encapsulation layer 40 .
[0069] In some embodiments, the second underfill layer 52 covers at least a portion of a sidewall of the second electronic component 22 .
[0070] The embodiment of the present application also provides a semiconductor packaging structure 100, including: a first substrate 11 and a second substrate 12 that are electrically connected, the first substrate 11 having a first surface 111 facing the second substrate 12, and a second surface 112 facing away from the second substrate 12, wherein the first substrate 11 has a groove 110, and the groove 110 is recessed from the first surface 111 toward the second surface 112; and a plurality of first electronic components 21, which are located in the groove 110 and electrically connected to the second substrate 12, and the surfaces 211 of the plurality of first electronic components 21 facing the second substrate 12 have different heights. The first substrate 11 of the embodiment of the present application includes a groove 110, and the depth of the groove 110 can be controlled. When accommodating a plurality of first electronic components 11 of different heights, the height of the accommodation in the height direction can be controlled without leveling, thereby avoiding the risks that may occur when grinding and leveling electronic components of different heights.
[0071] In some embodiments, the plurality of first electronic components 21 do not extend beyond the top surface of the groove 110 (i.e., the first surface 111 of the first substrate 11). In some embodiments, the plurality of first electronic components 21 extend beyond the top surface of the groove 110. In some embodiments, a portion of the plurality of first electronic components 21 does not extend beyond the top surface of the groove 110, and another portion extends beyond the top surface of the groove 110.
[0072] In some embodiments, the semiconductor packaging structure 100 also includes: a second electronic component 22, located between multiple first electronic components 21 and the second substrate 12, and the second electronic component 22 is electrically connected to the second substrate 12; an electrical connector 30, connecting the first substrate 11 and the second substrate 12, and the second electronic component 22 overlaps with the electrical connector 30 in the horizontal direction.
[0073] In some embodiments, the electrical connector 30 is connected to the portions of the first substrate 11 located on both sides of the groove 110. That is, the electrical connector 30 is disposed around the first electronic component 21 and the second electronic component 22.
[0074] In some embodiments, the semiconductor package structure 100 is a HBPOP, and the first electronic component 21 is an IPD, a LSC, etc.
[0075] Figure 4 Shown with Figure 3 In a different embodiment, the first underfill layer 51 is not included.
[0076] form Figure 4 The process of the semiconductor package 100 shown includes: Figure 5 , providing a first substrate 11 and a second substrate 12, and forming a groove 110 in the first substrate 11. Figure 6 For example, a FCB process is performed to bond the first electronic component 21 to the first substrate 11; an electrical connector 30 is formed on the first substrate 11; then a cutting process is performed to obtain a singulated first substrate 11, and a semi-finished product is obtained, and the singulated first substrate 11 is placed in a tray; for the second substrate 12 (for example, a wafer), a grinding process is first performed to flatten the upper surface of the second substrate 12, for example, a flip chip bonding (FCB) process is performed to bond the second electronic component 22 to the second substrate 12, and a second bottom filling layer 52 is filled; then, for example, a TCB process is performed to bond the first substrate 11 to the second substrate 12. See Figure 4 , forming a packaging layer 40 , forming a second electrical connection member 90 (eg, a solder ball), and performing a sawing process to obtain a singulated semiconductor package 100 .
[0077] Figure 7 Shown with Figure 3 , Figure 4 The semiconductor package of different embodiments does not include the second electronic component 22, and the first electronic component 21 is directly electrically connected to the second substrate 12. In this embodiment, the first electronic component 21 can be an interposer with a larger thickness. Since the groove 110 of the first substrate 11 makes up for the thickness of the first electronic component 21, the problem of the upper and lower plates being unable to be joined as in the prior art is avoided.
[0078] Figure 8 Shows Figure 3 , Figure 4 The schematic structural diagram of the embodiment shown in the figure shows that the electrical connector 30 can be formed on the first substrate 11 and the second substrate 12 in advance, respectively, and then fused together by a reflow process. Fig. 9 Shows Figure 7 A simplified structural diagram of the embodiment shown.
[0079] Fig.10 A bottom view of the first substrate 11 is shown, wherein a size comparison between the groove 110 and the first substrate 11 is shown.
[0080] The embodiments of the present application can also be applied to chiplets. Fig.11 The prior art solution of the chip particles is shown. The design on the strip substrate 12 is preferably arranged side by side, but the size of the strip substrate 19 will be too large, and the yield of the strip substrate 19 will be poor. If the solution of the present application is used, it can be as follows Fig.12 3D packaging stacking can reduce the XY (horizontal) dimensions of the semiconductor packaging structure 100. In some embodiments, the first electronic component 21 and the second electronic component 22 are chip dies, and the third electronic component 23 is DDR (Double Data Rate SDRAM).
[0081] The embodiment of the present application also provides a method for forming the first substrate 11 .
[0082] Fig.13 A carrier core layer 310 is shown.
[0083] Fig.14 It is shown that the first metal layer 330 is formed on both sides of the carrier core layer 310 by, for example, an electroplating process. In some embodiments, the first metal layer 330 is a copper layer.
[0084] Fig.15 Shown in Fig.14 A first dielectric layer 340 is formed on both sides of the structure shown. In some embodiments, the first dielectric layer 340 is a prepreg (PP).
[0085] Fig.16 Shown in Fig.15 The first circuit layer 350 is formed on both sides of the structure, and the first circuit layer 350 is electrically connected to the first metal layer 330. In some embodiments, the first circuit layer 350 is formed by drilling holes through a laser process and copper plating through an electroplating process.
[0086] Fig.17 Shown in Fig.16A second dielectric layer 360 is formed on both sides of the structure shown. In some embodiments, the second dielectric layer 360 is a prepreg (PP).
[0087] Fig.18 The structure is shown with the carrier core layer 310 and its underside removed.
[0088] Fig.19 Shown in Fig.18 The second circuit layer 370 and the pad (third circuit layer) 380 electrically connected to the first circuit layer 350 are formed on both sides of the structure. In some embodiments, the second circuit layer 370 and the pad 380 are formed by performing a laser process to drill holes and performing an electroplating process to plate copper. The pad 380 can be directly connected in series with the first circuit layer 350.
[0089] Fig. 20 It is shown that a solder resist layer 390 is formed, and the second wiring layer 370 and the pad 380 are subjected to surface treatment, such as ENEPIG.
[0090] Fig.21 The first metal layer 330 is etched away to obtain the groove 110, and the manufacturing of the first substrate 11 is completed. The surface of the groove 110 exposes the first circuit layer 350 formed by laser drilling, which serves as a bump pad electrically connected to the first electronic component 21. The surface treatment of the bump pad can be Cu or Ni / Au.
[0091] The embodiments of the present application break away from the intermediate cavity design that can only accommodate the system-on-a-chip (SoC) die frame, and can make use of the circuit series design of the intermediate element to place more elements [for example: IPD, multilayer ceramic capacitor (MLCC), integrated circuit die, high bandwidth memory (HBM) die, functional die, etc.] in the same space. In addition, the embodiments of the present application solve the difficulty of placing the IPD on the first substrate 11.
[0092] The embodiment of the present application hollows out the first substrate 11 to increase the accommodation space in the height direction, which solves the problem of the upper and lower plates being unable to be joined in the prior art. In some embodiments, the depth of the groove 110 of the present application is at least 50 μm, which can reduce the height of the first electronic component 21 on the side of the electrical connector 30, and even achieve an embedded result, so that the space of the packaging layer 40 can accommodate the main core (the second electronic component 22) and the first electronic component 21 at the same time, which can further reduce the thickness of the semiconductor package 100. The electrical connector 30 and the first electronic component 21 of the embodiment of the present application are placed at one time, reducing the impact of excessive thermal processes. The embodiment of the present application, for example Fig.21The design shown is a design with more than or equal to 3 circuit layers, so as to form a groove (cavity) 110 on the basis of ensuring the electrical connection requirements. The depth of the groove 110 of the present application can be designed according to the thickness of the component to be placed.
[0093] The above description is only the preferred embodiment of the utility model, and is not intended to limit the utility model. For those skilled in the art, the utility model can have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the utility model shall be included in the protection scope of the utility model.
Claims
1. A semiconductor packaging structure, characterized in that: include: A first substrate and a second substrate electrically connected, wherein the first substrate has a first surface facing the second substrate and a second surface facing away from the second substrate, wherein the first substrate has a groove, and the groove is recessed from the first surface toward the second surface; as well as At least one first electronic component is located in the groove and electrically connected to the second substrate, and a surface of the first electronic component facing the first substrate and a surface facing the second substrate are staggered from the first surface.
2. The semiconductor package structure according to claim 1, wherein: A side wall of the at least one first electronic component overlaps with a side wall of the groove in a horizontal direction.
3. The semiconductor package structure according to claim 2, characterized in that: Also includes: An electrical connector is used to electrically connect the first substrate and the second substrate, and the side wall of the at least one first electronic component overlaps with the electrical connector in the horizontal direction.
4. The semiconductor package structure according to claim 1, wherein: A surface of the at least one first electronic component facing the second substrate does not extend beyond a surface of the first substrate adjacent to the second substrate.
5. The semiconductor package structure according to claim 1, wherein: Also includes: The packaging layer is located between the first substrate and the second substrate, and a portion of the packaging layer is filled in the groove.
6. The semiconductor package structure according to claim 5, characterized in that: The side surface of the encapsulation layer is aligned with the side surface of the first substrate and the side surface of the second substrate.
7. The semiconductor package structure according to claim 5, characterized in that: Also includes: The second electronic component is located between the at least one first electronic component and the second substrate, and the second electronic component is electrically connected to the second substrate.
8. The semiconductor package structure according to claim 7, characterized in that: Also includes: The second bottom filling layer is located between the second electronic component and the second substrate.
9. The semiconductor package structure according to claim 8, characterized in that: The second bottom filling layer is covered by the packaging layer.
10. The semiconductor package structure according to claim 8, wherein: The second bottom filling layer covers at least a portion of a side wall of the second electronic component.