Multi-chip packaging structure

Abstract

The utility model provides a multi-chip packaging structure, which relates to the technical field of chip packaging and comprises a field programmable gate array (FPGA) chip. The fan-out type packaging chip is integrated with a plurality of functional chips; the fan-out type packaging chip is placed on the substrate, the FPGA chip is placed on the fan-out type packaging chip, and the substrate is filled with a first plastic packaging layer which covers the FPGA chip and the fan-out type packaging chip. The beneficial effects of the technical scheme are that the Fan-out packaging technology is used for packaging the plurality of functional chips, the plurality of functional chips can be integrated on a single Fan-out fan-out packaging chip, and the functional chips can be laid in the fan-out packaging chip, so that the number of stacked layers of the chips is greatly reduced, and the number of stacked chips is reduced. And the packaging volume for integrating a plurality of chips with different sizes is reduced. Meanwhile, according to the utility model, the Fan-out packaging technology is combined with the chip system-in-package technology, so that the packaging process flow is simplified, and the reliability of the packaged chip is high.

Description

Technical Field

[0001] The utility model belongs to the technical field of chip packaging, and in particular relates to a multi-chip packaging structure. Background Art

[0002] Chip packaging has evolved from the earliest bare die packaging, where the chip is directly exposed to the external environment without packaging protection, to chip-level packaging (Chip-Level Packaging), surface mount technology (Surface Mount Technology, SMT), system-level packaging (System-Level Packaging) and three-dimensional packaging technology (3D Packaging). With the continuous evolution of chip packaging technology, future chip packaging technology will develop towards no packaging and less packaging technology to achieve higher integration and performance. The development trend of chip packaging has continuously promoted the performance and function of products to a higher level, and has had a significant impact on modern computers, automation, communications and other fields.

[0003] System in a Package is an important packaging technology that integrates multiple functional wafers (such as processors, memory, etc.) into one package based on application scenarios, the number of packaging substrate layers, and other factors, thereby realizing a packaging solution with basic complete functions. In SiP packaging, bare chips can be arranged and combined as needed, and matched through different internal interconnect technologies to achieve different system functions. SiP packaging has the advantages of high integration and miniaturization, and is more flexible and efficient than traditional packaging technology.

[0004] Although multi-chip SiP packaging has some advantages, it also has some disadvantages that need to be overcome in practical applications: 1) Large size: Since multiple chips need to be integrated in the package, the volume of the multi-chip SiP package is relatively large, which is not conducive to miniaturization and lightweight; 2) Complex packaging process: When multiple chips of different sizes need to be integrated and stacked in a package, the wire bonding packaging process is difficult to support; 3) Reliability risk: There may be mutual interference between the multiple chips in the multi-chip SiP package, and the internal thermal management and electrical performance are also relatively complex, which may affect its reliability.

[0005] Therefore, it is necessary to develop a new chip packaging method based on multi-chip SIP packaging, which can solve the problems of large size, complex process and low reliability in the existing multi-chip packaging process. Utility Model Content

[0006] The utility model provides a multi-chip packaging structure, which has the advantages of simple structure, uncomplicated manufacturing process and reliability and stability.

[0007] Other purposes and advantages of the present invention can be further understood from the technical features disclosed in the present invention.

[0008] In order to achieve one or part or all of the above purposes or other purposes, a technical solution of the utility model provides a multi-chip packaging structure, the packaging structure includes an FPGA chip; a fan-out packaging chip integrating multiple functional chips; the fan-out packaging chip is placed on a substrate, the FPGA chip is placed on the fan-out packaging chip, and the substrate is filled with a first plastic packaging layer covering the FPGA chip and the fan-out packaging chip. The beneficial effect of this technical solution is that the utility model packages multiple functional chips using Fan-out packaging technology, multiple functional chips can be integrated on a single Fan-out fan-out packaging chip, and these functional chips can be tiled in the fan-out packaging chip, thereby greatly reducing the number of layers of chip stacking and reducing the packaging volume of multiple chips of different sizes. At the same time, the utility model combines the Fan-out packaging technology with the chip system-level packaging process, so that the packaging process is simplified and the reliability of the packaged chip is high.

[0009] There is a chip bonding layer between the FPGA chip and the fan-out package chip, and the chip bonding layer covers the upper surface of the fan-out package chip.

[0010] The chip bonding layer is an insulating bonding layer.

[0011] The FPGA chip and the fan-out package chip are both square, the length of the FPGA chip is longer than the length of the fan-out package chip; the fan-out package chip is placed in the middle of the FPGA chip.

[0012] The substrate is square, and the length of the substrate is longer than the length of the FPGA chip and the length of the fan-out package chip; the fan-out package chip and the FPGA chip are placed in the middle of the substrate.

[0013] The FPGA chip and the substrate are bonded and connected by bonding wires.

[0014] The fan-out packaging chip includes a packaging wafer, a re-passivation layer, a re-wiring layer, a functional chip, a second plastic packaging layer, and solder balls or copper pillar bumps; the functional chip is located in the packaging wafer, and the solder balls or copper pillar bumps are connected to the re-wiring layer on the packaging wafer; the solder balls or copper pillar bumps are connected to the substrate.

[0015] A glue filling layer is also provided at the connection between the solder balls or copper pillar bumps on the fan-out package chip and the substrate.

[0016] The first plastic encapsulation layer covers the substrate, and the first plastic encapsulation layer is equal in size and shape to the substrate.

[0017] A plurality of solder balls are also arranged under the substrate.

[0018] Compared with the prior art, the beneficial effects of the utility model mainly include: 1. High integration, integrating multiple chips in one package, realizing a highly integrated circuit system, which helps to reduce the size of the device, improve performance, and reduce costs; 2. It makes the package design more flexible and freer, and the package performance is more reliable. 3. Fan-out packaging technology breaks through the limitation of the number of I / O pins. Fan-out packaging can reconstruct the wafer through advanced packaging technology to increase the area of ​​a single package body, and then use the advanced manufacturing process of wafer-level packaging to complete multi-layer rewiring and bump preparation. After cutting and separation, a package body that can be interconnected with external electrical performance is obtained. 4. The utility model uses Fan-out packaging technology to package multiple functional chips. Multiple functional chips can be integrated on a single Fan-out fan-out package chip, and these functional chips can be tiled in the fan-out package chip, thereby greatly reducing the number of chip stacking layers and reducing the package volume of multiple chips of different sizes. At the same time, the utility model combines the Fan-out packaging technology with the chip system-level packaging process, so that the packaging process is simplified and the reliability of the packaged chip is high.

[0019] In order to make the above and other purposes, features and advantages of the present invention more obvious and understandable, preferred embodiments are given below with reference to the accompanying drawings for detailed description as follows. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the specific embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0021] Figure 1 This is a schematic diagram of the multi-chip packaging structure of the utility model.

[0022] Figure 2 This is a schematic diagram of connecting multiple functional chips on the fan-out package chip of the utility model.

[0023] Figure 3 This is a schematic diagram of the fan-out package chip structure of the utility model.

[0024] In the figure, 1 is the substrate; 2 is the glue filling layer; 3 is the fan-out packaged chip; 31 is the packaged wafer; 32 is the operational amplifier chip; 33 is the DAC chip; 34 is the ADC chip; 35 is the interface transceiver chip; 36 is the flash memory chip; 37 is the rewiring layer; 38 is the solder ball; 39 is the second plastic packaging layer; 310 is the functional chip die; 311 is the repassivation layer; 4 is the chip bonding layer; 5 is the FPGA chip; 6 is the bonding wire; 7 is the first plastic packaging layer; 8 is the solder ball. DETAILED DESCRIPTION

[0025] The above and other technical contents, features and effects of the present invention will be clearly presented in the following detailed description of a preferred embodiment with reference to the drawings. The directional terms mentioned in the following embodiments, such as up, down, left, right, front or back, etc., are only referenced to the directions of the attached drawings. Therefore, the directional terms used are used to illustrate and not to limit the present invention.

[0026] Embodiment 1 provides a multi-chip packaging structure, see Figure 1 The multi-chip packaging structure includes a substrate 1, on which an FPGA chip 5 and a fan-out packaging chip 3 are arranged, and the fan-out packaging chip 3 integrates multiple functional chips. The specific structure of the fan-out packaging chip 3 is shown in Figure 2 as well as Figure 3 , see Figure 2 In this embodiment 1, 6 functional chips are taken as an example. The packaging wafer 31 of the fan-out packaging chip 3 is square. The size of the packaging wafer 31 of the fan-out packaging chip 3 in this embodiment 1 is 8*8mm. There are 2 operational amplifier chips 32 with a power of 600mW (size 1.39*1.39mm), 1 14-bit 80MSPS single-channel analog-to-digital converter ADC chip 34 (size 1.974*2.034mm), 1 14-bit 125MSPS single-channel DAC chip 33 (1.63*1.83mm), a 422 interface transceiver RS422 chip 35 (size 1.4*1.24mm), and a 32M flash memory chip 36 (1.341.1.622mm) on the packaging wafer 31 of the fan-out packaging chip 3. The sizes of the above-mentioned functional chips are different, but laying these functional chips on the packaging wafer 31 can greatly reduce the number of layers of chip stacking. At the same time, it can also solve the problem of inconvenience in stacking these functional chips of different sizes caused by different sizes when stacking.

[0027] See also Figure 3 , Figure 33 is a schematic diagram of the structure of the fan-out packaged chip 3, including a functional chip die 310 and a packaged wafer 31. A redistribution layer 37 (RDL) is manufactured by physical sputtering, photolithography and wiring technology on the packaged wafer 31. The redistribution layer 37 is arranged in the second plastic layer 39 and the repassivation layer 311 on the upper part of the packaged wafer 31. The repassivation layer 311 can protect the redistribution layer 37. A plurality of solder balls 38 or copper pillar bump structures interconnected with the outside are formed on the redistribution layer 37 by electroplating solder joint processing technology. These solder balls 38 or copper pillar bump structures are used to connect the fan-out packaged chip 3 with the substrate 1. The fan-out packaged chip 3 is filled with a second plastic layer 39 on the side loaded with the functional chip die 310. After the plastic packaging is completed, the second plastic layer needs to be ground to the chip thickness required by the design. When the fan-out packaged chip 3 is installed on the substrate 1, it is soldered on the substrate 1 using a flip chip process. That is, when the fan-out packaged chip 3 is soldered to the substrate 1, the functional chip die 310 loaded on the fan-out packaged chip 3 is located inside the packaging wafer 31, and the solder ball 38 or copper pillar bump structure arranged on the opposite side of the functional chip die 310 on the fan-out packaged chip 3 is connected to the substrate 1.

[0028] In order to protect the solder ball 38 or copper pillar bump structure connecting the fan-out type packaged chip 3 and the substrate 1, a filling layer is provided at the connection between the solder ball 38 or copper pillar bump structure of the fan-out type packaged chip 3 and the substrate. The filling layer is filled with glue, which can protect the solder ball 38 or copper pillar bump structure.

[0029] There is also an FPGA chip 5 above the fan-out package chip 3. The packaging structure of the FPGA chip 5 and the fan-out package chip 3 is a system-level package (Sip). The FPGA chip 5 is stacked on top of the second plastic packaging layer 39 of the fan-out package chip 3. In order to ensure a stable connection between the FPGA chip 5 and the fan-out package chip 3, there is also a chip bonding layer 4 between the FPGA chip 5 and the fan-out package chip 3. The chip bonding layer 4 is a uniformly coated insulating glue.

[0030] The connection method between the FPGA chip 5 and the substrate 1 is wire bonding. The FPGA chip 5 is connected to the substrate 1 through the bonding wire 6. The bonding method can be ultrasonic bonding or compression bonding. After the bonding is completed, the FPGA chip 5, the fan-out package chip 3 and the first plastic sealing layer 7 are filled on the substrate. The first plastic sealing layer 7 and the second plastic sealing layer 39 are generally resin plastic sealing layers. The first plastic sealing layer 7 completely covers the substrate 1. After the plastic sealing is completed, the first plastic sealing layer 7 needs to be cut so that the size of the first plastic sealing layer 7 is the same as that of the substrate 1.

[0031] In the present embodiment 1, the FPGA chip 5, the substrate 1 and the fan-out package chip 3 are all square, the substrate 1 has the largest size, the FPGA chip 5 is smaller than the substrate 1 and larger than the fan-out package chip 3, and the FPGA chip 5 is larger than the fan-out package chip 3. After the FPGA chip 5, the fan-out package chip 3 and the substrate 1 are packaged, the solder balls 8 on the substrate 1 can be used to connect the packaged chip to an external device.

[0032] The above is a detailed introduction to a multi-chip packaging structure provided by the utility model. This article uses specific examples to illustrate the structure and working principle of the utility model. The description of the above embodiments is only used to help understand the method and core idea of ​​the utility model. It should be pointed out that for ordinary technicians in this technical field, without departing from the principle of the utility model, the utility model can also be improved and modified, and these improvements and modifications also fall within the scope of protection of the claims of the utility model.

Claims

1. A multi-chip packaging structure, characterized in that: The packaging structure comprises an FPGA chip (5); Fan-out packaged chips that integrate multiple functional chips (3); The fan-out packaged chip (3) is placed on a substrate (1), the FPGA chip (5) is placed on the fan-out packaged chip (3), and the substrate (1) is filled with a first plastic packaging layer (7) covering the FPGA chip (5) and the fan-out packaged chip (3).

2. The multi-chip packaging structure according to claim 1, characterized in that: A chip bonding layer (4) is provided between the FPGA chip (5) and the fan-out package chip (3), and the chip bonding layer (4) covers the upper surface of the fan-out package chip (3).

3. The multi-chip packaging structure according to claim 2, characterized in that: The chip bonding layer (4) is an insulating bonding layer.

4. The multi-chip packaging structure according to claim 2, characterized in that: The FPGA chip (5) and the fan-out package chip (3) are both square, and the length of the FPGA chip (5) is longer than the length of the fan-out package chip (3); The fan-out package chip (3) is placed in the middle of the FPGA chip (5).

5. The multi-chip packaging structure according to claim 4, characterized in that: The substrate (1) is square, and the length of the substrate (1) is longer than the length of the FPGA chip (5) and the length of the fan-out package chip (3); The fan-out package chip (3) and the FPGA chip (5) are placed in the middle of the substrate (1).

6. The multi-chip packaging structure according to claim 2, characterized in that: The FPGA chip (5) and the substrate (1) are bonded and connected using bonding wires (6).

7. The multi-chip packaging structure according to claim 2, characterized in that: The fan-out packaged chip (3) comprises a packaged wafer (31), a repassivation layer (311), a rewiring layer (37), a functional chip die (310), a second plastic encapsulation layer (39), and solder balls (38) or copper pillar bumps; The functional chip is located in the packaging wafer (31), and the solder balls (38) or copper pillar bumps are connected to the redistribution layer (37) on the packaging wafer (31); The solder balls (38) or copper pillar bumps are connected to the substrate (1).

8. The multi-chip packaging structure according to claim 7, characterized in that: A glue filling layer (2) is also provided at the connection between the solder balls (38) or copper pillar bumps on the fan-out package chip (3) and the substrate (1).

9. The multi-chip packaging structure according to claim 1, characterized in that: The first plastic encapsulation layer (7) covers the substrate (1); the first plastic encapsulation layer (7) and the substrate (1) are equal in size and shape.

10. The multi-chip packaging structure according to claim 1, characterized in that: A plurality of solder balls (8) are also arranged below the substrate (1).

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