Transient voltage suppression device

Abstract

The utility model discloses a transient voltage suppression device. The device includes a substrate, a first base layer and a second base layer, the substrate coupled to the first base layer and to the second base layer, and one or more emitter layers formed in the first base layer.

Description

Technical Field

[0001] The present disclosure relates generally to the field of power semiconductor discrete devices, and in particular, to transient voltage suppressor devices, such as, for example, unidirectional transient voltage suppressor devices having a low clamping voltage. Background Art

[0002] Semiconductor devices such as transient voltage suppressors (TVS) devices can be used to protect sensitive circuit nodes from one-time and time-limited overvoltage faults. Such TVS diodes are also used in modern high-power IGBT circuits to prevent overloads in collector circuits. Requirements for such TVS diodes can include high breakdown voltages with low deviation and low temperature coefficient, and high surge current capabilities with low clamping voltages. In addition, in many applications, TVS devices can be designed to prevent repetitive surge events, making TVS devices susceptible to damage after repetitive surge events. However, current unidirectional TVS devices are able to provide low clamping voltages without compromising performance. Utility Model Content

[0003] This Summary is provided to introduce in a simplified form selected concepts that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to assist in determining the scope of the claimed subject matter.

[0004] In some embodiments, the current subject matter relates to a transient voltage suppression device, which can include a substrate, a first base layer and a second base layer, the substrate coupled to the first base layer and coupled to the second base layer, and one or more emitter layers formed in the first base layer.

[0005] In some embodiments, the current subject matter can include one or more of the following optional features. The substrate can be an n-type substrate. The first base layer can be a p base layer and the second base layer can be an N+ base layer.

[0006] In some embodiments, the coupling of the substrate and the first base layer can be configured to form a first PN junction. The coupling of the substrate and the second base layer can be configured to form a second PN junction. One or more emitter layers are N+ type layers. Forming one or more emitter layers in the first base layer can form an NPN configuration of the transient voltage suppression device.

[0007] In some embodiments, one or more emitter layers can be disposed on the positive side of the transient voltage suppression device.

[0008] In some embodiments, one or more emitter layers may be doped in the first substrate layer using one or more dopants. The one or more dopants may include at least one of phosphorus, boron, arsenic, gallium, and any combination thereof. The one or more emitter layers may have a predetermined concentration of one or more dopants in the first substrate layer. The one or more emitter layers may have a predetermined depth in the first substrate layer. The transient voltage suppression device is characterized by a clamping voltage, wherein the clamping voltage of the transient voltage suppression device may be determined as a function of at least one of the following: a predetermined concentration of one or more dopants in the first substrate layer, a predetermined depth of one or more emitter layers in the first substrate layer, and any combination thereof. Each of the one or more emitter layers may have the same concentration of one or more dopants. Alternatively or in addition, each of the one or more emitter layers has a different concentration of one or more dopants. In some embodiments, the one or more emitter layers may be arranged in a predetermined pattern in the first substrate layer.

[0009] In some embodiments, at least one of the substrate, the first base layer, and the second base layer may include at least one of the following: silicon, silicon carbide, silicon germanium, and any combination thereof.

[0010] In some embodiments, the transient voltage suppression device may be a unidirectional transient voltage suppression device.

[0011] In some embodiments, the present subject matter relates to a method (e.g., a method for manufacturing a transient voltage suppression device). The method may include providing a substrate, a first substrate layer, and a second substrate layer, coupling the first substrate layer to the substrate via a first junction, and coupling the second substrate layer to the substrate via a second junction, and forming one or more emitter layers in the first substrate layer. Forming one or more emitter layers in the first substrate layer can form an NPN configuration of the transient voltage suppression device. In addition, the transient voltage suppression device is characterized by a clamping voltage, wherein the clamping voltage of the transient voltage suppression device can be determined as a function of at least one of the following: a predetermined concentration of one or more dopants in the first substrate layer, a predetermined depth of the one or more emitter layers in the first substrate layer, and any combination thereof.

[0012] The details of one or more variations of the subject matter described herein are set forth in the accompanying drawings and the description below. Other features and advantages of the subject matter described herein will be apparent from the description and drawings, and from the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate certain aspects of the subject matter disclosed herein and, together with the description, help explain some principles associated with the disclosed embodiments.

[0014] Figure 1 An exemplary transient voltage suppressor (TVS) device is shown;

[0015] Figure 2 An exemplary unidirectional TVS device according to some embodiments of the current subject matter is shown;

[0016] Figure 3a to Figure 3c Various dopant layout configurations for the emitter layer(s) in the first substrate layer according to some embodiments of the current subject matter are shown;

[0017] Figure 4a to Figure 4b shows an example current-voltage graph; and

[0018] Figure 5 An exemplary process according to some implementations of the current subject matter is shown.

[0019] The drawings are not necessarily drawn to scale. The drawings are merely representations and are not intended to depict specific parameters of the present disclosure. The drawings are intended to depict exemplary embodiments of the subject matter and are therefore not to be considered limiting of the scope. In the drawings, the same numerals represent the same elements.

[0020] In addition, for the sake of clarity, some elements in some of the figures may be omitted and / or not shown to scale. The cross-sectional views may be in the form of "slices", or in the form of "close-up" cross-sectional views, omitting certain background lines that would otherwise be visible in a "true" cross-sectional view for the sake of clarity. In addition, for the sake of clarity, some reference numerals may be omitted in some of the figures. DETAILED DESCRIPTION

[0021] Various methods according to the present disclosure will now be described more fully below with reference to the accompanying drawings, in which embodiments of systems and methods are shown. Devices, (one or more) systems, (one or more) components, etc. may be embodied in many different forms and should not be construed as limited to the example embodiments set forth herein. Rather, these example embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of the current subject matter to those skilled in the art.

[0022] To address these and potential other deficiencies of currently available solutions, one or more embodiments of the present subject matter are directed to methods, systems, articles of manufacture, etc., which can provide unidirectional transient voltage suppressor devices with low clamping voltages that can provide improved surge performance, among other possible advantages.

[0023] Voltage transients are defined as short-duration surges of electrical energy and are the result of a sudden release of previously stored energy and / or caused by other means such as, for example, heavy inductive loads, lightning, etc. Voltage transients can be classified as predictable or repeatable transients and random transients. In electrical or electronic circuits, this energy can be released in a predictable manner via controlled switching actions, or randomly introduced into the circuit from an external source. Repeatable transients are usually caused by the operation of motors, generators, and / or the switching of reactive circuit components. On the other hand, random transients are often caused by electrostatic discharge (ESD) and lightning, which usually occur unpredictably.

[0024] ESD is characterized by very fast rise times and very high peak voltages and currents, which can be the result of an imbalance of positive and negative charges between objects. ESD generated by everyday activities can exceed the vulnerability threshold of standard semiconductor technology. In the case of lightning, even if a direct lightning strike is destructive, the voltage transients caused by lightning are not the result of a direct lightning strike. When a lightning strike occurs, the event generates a magnetic field, which in turn can cause large voltage transients in nearby power cables. For example, a cloud-to-cloud strike will affect not only overhead cables, but also buried cables. Even a lightning strike 1 mile (1.6km) away can generate 70 volts in power cables. In a cloud-to-ground lightning strike, the voltage transients generated are significantly greater.

[0025] Figure 1 An exemplary transient voltage suppressor (TVS) device 100 is shown. The TVS device 100 may be formed in a monolithic semiconductor substrate, such as silicon. In particular, the TVS device 100 may include a substrate 104, a first substrate layer 102, and a second substrate layer 106. The substrate 104 may be formed to have a first type of polarity. The substrate 104 may be formed between the first substrate layer 102 and the second substrate layer 106. The first substrate layer 102 and the second substrate layer 106 may be formed to have a second type and a third type of polarity, respectively. The second type of polarity may be opposite to the first type of polarity. Figure 1 As shown, the substrate 104 may be an N-type substrate, the first base layer 102 may be a P-type base layer, and the second base layer 106 may be an N+ base layer.

[0026] The first base layer 102 may form a PN junction with the substrate 104. The second base layer 106 may form another PN junction with the substrate 104.

[0027] Understandably, although Figure 1A device 100 based on an N-type substrate is shown, and the TVS device 100 may have a P-type substrate having an N-type first base layer and a second base layer disposed on opposite surfaces. In some embodiments, the TVS device 100 may be a unidirectional device, however, as can be appreciated, the TVS 100 may be any other type of device.

[0028] Figure 2 An exemplary unidirectional TVS device 200 is shown in accordance with some embodiments of the current subject matter. Figure 1 As shown in the device 100, the TVS device 200 can be configured to be formed in a semiconductor substrate, such as, for example, silicon. As can be appreciated, other substrate materials can be used. However, the device 200 can be configured to provide an advantageous structure that can help provide a low clamping voltage while avoiding degradation of the surge performance of the TVS device, which can be useful in various industries, such as, for example, automotive applications.

[0029] To achieve the above advantages, the TVS device 200 can be configured to include one or more emitter layers (e.g., (one or more) N+ and / or P substrate layers). In some embodiments, the TVS device 200 can be formed using a substrate (e.g., an N substrate and / or a P substrate). The substrate layer (e.g., a P substrate and / or an N substrate) can be formed on top of the substrate. The substrate layer can be thermally doped into the substrate and / or epitaxially deposited (e.g., using a P-type EPI). (One or more) emitter layers can be doped into the substrate layer and / or merged into the substrate layer using any other method. Different layers in the TVS device can be configured to form different types of junctions. For example, the substrate and substrate layer can form a PN portion, while the addition of (one or more) emitter layers can create an NPN portion, thereby making the TVS device 200 a parallel-connected combination of a PN-type and an NPN-type device.

[0030] During a negative surge pulse, the PN (i.e., substrate-base layer) portion may exhibit a high clamping voltage, while the NPN portion may exhibit a low clamping voltage due to the current gain effect of the transistor N+PN. In some embodiments, the configuration of the TVS device 200 may allow the current gain of the transistor to be tuned by adjusting the depth and / or concentration of the different base layers, which in turn may be configured to allow the clamping voltage of the TVS device 200 to be controlled.

[0031] During a positive surge pulse, the partial area covered by the emitter layer(s) may be sufficient to conduct forward current due to the low voltage drop (e.g., <1 volt (V)). By tuning the ratio of the emitter layer(s), the unidirectional TVS device 200 can be configured as a low clamping voltage device without sacrificing surge performance.

[0032] refer to Figure 2 , the TVS device 200 may include a first base layer 202 disposed on the positive side of the TVS device 200, a substrate 204, a second base layer 206 disposed on the negative side of the TVS device 200, and one or more emitter layers 208 (a, b, c . . . , n) disposed on the positive side of the TVS device 200. The substrate 204 may be formed to have a first type of polarity. The first base layer 202 may be configured to have a second type of polarity, which may be different from the first type of polarity of the substrate 204. The second base layer 206 may have a third type of polarity, which may be different from the polarity of the substrate 204 or may not be different from the polarity of the substrate 204. (One or more) emitter layers 208 may be formed in the first base layer 202. (One or more) each emitter layer 208 may be configured as a separate layer (one or more) therebetween in the first base layer 206. The polarity of the emitter layer(s) 208 may be similar to the polarity of the substrate 204 and / or the second base layer 206 and may be different from the polarity of the first base layer 202. Each emitter layer 208 may be doped into the first base layer 202 and / or formed and / or incorporated into the first base layer 202 in any other manner.

[0033] For example, Figure 2 As shown, the polarity of the substrate (e.g., the polarity of the first type) can be N-type. The polarity of the first base layer 202 can be P-type. The polarity of the second base layer 206 can be N+ type. The polarity of (one or more) emitter layers 208 can be N+ type. As can be understood, other arrangements of polarity are possible. In some examples (non-limiting embodiments), the substrate 204, the first base layer 202 and the second base layer 206 can be formed using silicon, silicon carbide, silicon germanium and / or any other material. (One or more) emitter layers 208 can be formed using one or more dopants, such as, for example, phosphorus, boron, arsenic, gallium and / or any other desired material. Each emitter layer 208 can be formed using the same dopant material and / or different dopant materials.

[0034] In some embodiments, the combination of the polarities of the emitter layer(s) 208, the first base layer 202, and the substrate 204 can create an NPN configuration, which can be advantageous for creating a lower clamping voltage for the TVS device 200. The doping and / or depth of the emitter layer(s) 208 can be selected depending on the desired clamping voltage of the TVS device 200. The clamping voltage can be referred to as the voltage at which the TVS device 200 can be configured to conduct its full rated current (e.g., hundreds of amperes, thousands of amperes, etc.). For example, an increase in the doping concentration and / or depth of the emitter layer(s) 208 can be configured to reduce the clamping voltage of the TVS 200 and a decrease in the doping concentration and / or depth of the emitter layer(s) 208 can be configured to increase the clamping voltage of the TVS 200.

[0035] Alternatively or in addition, the polarity and / or depth / doping concentration of the emitter layer(s) 208 may be selected based on a desired breakdown voltage of the TVS device 200. The breakdown voltage may be referred to as the maximum reverse voltage that may be applied without causing an exponential increase in leakage current in the TVS device 200. For example, a higher doping concentration in the emitter layer(s) 208 may result in a TVS device 200 having a lower breakdown voltage; alternatively, a lower doping concentration in the emitter layer(s) 208 may result in a TVS device 200 having a higher breakdown voltage. As may be appreciated, other relationships between the doping concentration in the emitter layer(s) 208 and the breakdown voltage and / or clamping voltage of the TVS device 200 are possible.

[0036] The doping concentration in the emitter layer(s) 208 may be uniform. Alternatively or in addition, the concentration may be non-uniform. This may allow the clamping voltage of the TVS device 200 to be varied. The emitter layer(s) 208 may also have a predetermined thickness. The thickness of the emitter layer(s) 208 may be less than the thickness of the substrate 204. The thickness of the emitter layer(s) 208 may also be less than the thickness of the first base layer 202.

[0037] Additionally, as may be appreciated, other types of doping of the layers 204 - 206 and / or the emitter layer(s) 208 (and / or any other components of the TVS device 200 ) are possible.

[0038] In some embodiments, all layers 202-208 may be made of the same material, such as silicon. Alternatively or in addition, at least one of the layers 202-208 may be made of a different material. The layers 202-208 may be configured to have the same and / or different dopant materials and / or corresponding concentrations.

[0039] In some embodiments, the emitter layer(s) 208 may be configured to form a PN junction with the first substrate layer 202. Another PN junction may be formed between the substrate layer 204 and the first substrate layer 202. The junction may be configured to create an NPN configuration between the emitter layer(s) 208 (N+), the first substrate layer 202 (P), and the substrate 204 (N). As may be appreciated, any other concentration configuration may be possible (e.g., PNP, etc.).

[0040] Figure 3a to Figure 3c Various dopant layout configurations of the emitter layer(s) 208 in the first substrate layer 202 are shown according to some embodiments of the current subject matter. For example, Figure 3a A layout configuration 302 is shown in which each emitter layer 208 is arranged to have a square shape. Figure 3b A layout configuration 304 is shown in which each emitter layer 208 is arranged to have a circular shape. Figure 3c A layer configuration 306 is shown in which the emitter layer 208 is positioned around the edge of the first substrate layer 202. As can be appreciated, any desired dopant layout configuration is possible. One or more emitter layers 208 can be doped and / or formed in the substrate layer 202 in the same and / or different configurations (e.g., circular, square, rectangular, etc.).

[0041] Figure 4a to Figure 4b An example current-voltage graph is shown. Figure 4a A graph 402 showing the clamping voltage of a conventional TVS device is shown. Figure 4b A TVS device (eg Figure 2 FIG. 4 is a graph 404 showing the clamping voltage of the TVS device 200 shown in FIG. Figure 4b As shown, the TVS device 200 of the present subject matter has a significantly reduced clamping voltage.

[0042] Figure 5 An exemplary process 500 for manufacturing a transient voltage suppressor device according to some embodiments of the current subject matter is shown. The process 500 can be used to manufacture, for example, Figure 2 The TVS device 200 is shown.

[0043] At 502, a substrate, a first substrate layer, and a second substrate layer may be provided. For example, the substrate may be substrate 204; the first substrate layer may be first substrate layer 202; and the second substrate layer may be second substrate layer 206. The substrate may be an n-type substrate. The first substrate layer may be a p-substrate layer and the second substrate layer may be an N+ substrate layer.

[0044] At 504, the substrate can be coupled to the first base layer on one side (eg, the positive side of the TVS device). The substrate can also be coupled to the second base layer on the opposite side (eg, the negative side of the TVS device), such as Figure 2 In some embodiments, the substrate may be configured to cover and / or surround at least a portion of each of the first base layer and the second base layer. In addition, the coupling of the substrate and the first base layer may be configured to form a first PN junction.

[0045] At 506, one or more emitter layers may be formed in the first substrate layer. For example, the emitter layer may include (one or more) emitter layer 208, such as Figure 2 As shown. In some exemplary non-limiting embodiments, the emitter layer may be an n-type layer, such as, for example, an N+ layer. The emitter layer may be any other type of layer and may be configured according to the specific arrangement and / or type of the substrate and / or base layer and / or the specific application and / or use. In some embodiments, the emitter layer may be doped in the first base layer and / or formed in the first base layer in any other manner. The emitter layer may have a predetermined concentration of dopant and / or depth, one or more of which may depend on the desired clamping voltage. Dopants may include, but are not limited to, for example, phosphorus, boron, arsenic, gallium and / or any other desired material. Each emitter layer 208 may be formed using the same dopant material and / or different dopant materials. The substrate, the first base layer and / or the second base layer may include silicon, silicon carbide, silicon germanium and / or any other material.

[0046] The components and features of the above-mentioned devices can be implemented using any combination of discrete circuits, application specific integrated circuits (ASICs), logic gates, and / or single chip architectures. In addition, the features of the devices can be implemented using microcontrollers, programmable logic arrays, and / or microprocessors, or any combination of the foregoing, where appropriate. It should be noted that hardware, firmware, and / or software elements may be collectively or individually referred to herein as "logic" or "circuitry."

[0047] It will be understood that the exemplary devices shown in the above block diagrams may represent a functional descriptive example of many potential implementations. Therefore, the division, omission or inclusion of block functions depicted in the accompanying drawings does not mean that the hardware components, circuits, software and / or elements used to implement these functions must be divided, omitted or included in the embodiments.

[0048] Some embodiments may be described using the expression "one embodiment" or "an embodiment" and its derivatives. These terms mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. The phrase "in one embodiment" (or its derivatives) appearing in different places in the specification does not necessarily refer to the same embodiment. In addition, unless otherwise stated, the above-mentioned features are considered to be usable together in any combination. Therefore, any features discussed separately can be adopted in combination with each other, unless it is noted that these features are incompatible with each other.

[0049] It is emphasized that the abstract of the present disclosure is provided to allow the reader to quickly determine the nature of the present technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. In addition, in the foregoing detailed description, it can be seen that various features are grouped together in a single embodiment for the purpose of simplifying the present disclosure. The disclosure method should not be interpreted as reflecting the intention that the claimed embodiment requires more features than those explicitly stated in each claim. On the contrary, as reflected in the following claims, the creative subject lies in less than all the features of a single disclosed embodiment. Therefore, the following claims are incorporated into the detailed description, wherein each claim exists independently as a separate embodiment. In the appended claims, the terms "including" and "wherein" are used as the plain English equivalents of the corresponding terms "including" and "wherein", respectively. In addition, the terms "first", "second", "third", etc. are used only as labels and are not intended to impose numerical requirements on their objects. In addition, the use of "including", "comprising" or "having" and its variants herein is intended to cover the items listed thereafter and their equivalents and additional items. Therefore, the terms "including", "comprising" or "having" and their variants are open expressions and can be used interchangeably herein.

[0050] For convenience and clarity, terms such as "top," "bottom," "upper," "lower," "vertical," "horizontal," "lateral," "cross," "radial," "inner," "outer," "left," and "right" may be used herein to describe the relative placement and orientation of features and components, each relative to the geometry and orientation of other features and components appearing in the perspective, exploded perspective, and cross-sectional views provided herein. The terminology is not intended to be limiting and includes the words specifically mentioned, derivatives thereof, and words of similar meaning.

[0051] What has been described above includes examples of the disclosed architecture. Of course, it is not possible to describe every conceivable combination of components and / or methods, but one of ordinary skill in the art may recognize that many further combinations and permutations are possible. Therefore, the novel architecture is intended to embrace all such changes, modifications, and variations that fall within the spirit and scope of the appended claims.

[0052] The foregoing description of example embodiments has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the disclosure to the precise form disclosed. Many modifications and variations are possible in light of the disclosure. It is intended that the scope of the disclosure is not limited by this specific embodiment, but rather by the claims appended hereto. Future applications claiming priority to the present application may claim the disclosed subject matter in different ways, and may generally include any set of one or more limitations as variously disclosed or otherwise presented herein.

[0053] All directional references (e.g., proximal, distal, up, down, upward, downward, left, right, lateral, longitudinal, front, back, top, bottom, above, below, vertical, horizontal, radial, axial, clockwise, and counterclockwise) are used for identification purposes only to assist the reader in understanding the present disclosure and do not create limitations, particularly with respect to the position, orientation, or use of the present disclosure. Connection references (e.g., attach, couple, connect, and engage) should be interpreted broadly and may include intermediate members between a collection of elements and relative movement between elements, unless otherwise specified. Therefore, a connection reference does not necessarily mean that two elements are directly connected and are in a fixed relationship to each other.

[0054] Additionally, identifying references (e.g., primary, secondary, first, second, third, fourth, etc.) are not intended to imply importance or priority, but are used to distinguish one feature from another. The drawings are for illustrative purposes only, and the dimensions, positions, order, and relative sizes reflected in the drawings attached hereto may vary.

[0055] The present disclosure is not limited in scope by the specific embodiments described herein. In fact, various other embodiments of the present disclosure and modifications to the present disclosure, in addition to those described herein, will be apparent to those of ordinary skill in the art from the foregoing description and the accompanying drawings. Therefore, such other embodiments and modifications are intended to fall within the scope of the present disclosure. In addition, the present disclosure has been described herein in the context of specific embodiments in specific environments for specific purposes. Those of ordinary skill in the art will recognize that usefulness is not limited thereto, and the present disclosure can be beneficially implemented in any number of environments for any number of purposes. Therefore, the claims set forth below should be interpreted according to the full breadth and spirit of the present disclosure as described herein.

Claims

1. A transient voltage suppression device, characterized in that: include: a substrate, a first base layer, and a second base layer, the substrate being coupled to the first base layer and coupled to the second base layer; as well as One or more emitter layers are formed in the first base layer.

2. The transient voltage suppression device according to claim 1, characterized in that: The substrate is an n-type substrate.

3. The transient voltage suppression device according to claim 2, characterized in that: The first base layer is a p base layer and the second base layer is an N+ base layer.

4. The transient voltage suppression device according to claim 1, characterized in that: The coupling of the substrate and the first base layer is configured to form a first PN junction; and The coupling of the substrate and the second base layer is configured to form a second PN junction.

5. The transient voltage suppression device according to claim 4, characterized in that: The one or more emitter layers are N+ type layers.

6. The transient voltage suppression device according to claim 5, characterized in that: Forming the one or more emitter layers in the first substrate layer forms an NPN configuration of the transient voltage suppression device.

7. The transient voltage suppression device according to claim 1, characterized in that: The one or more emitter layers are disposed on a positive side of the transient voltage suppression device.

8. The transient voltage suppression device according to claim 1, characterized in that: The one or more emitter layers have a predetermined depth in the first base layer.

9. The transient voltage suppression device according to claim 1, characterized in that: The one or more emitter layers are arranged in a predetermined pattern in the first substrate layer.

10. The transient voltage suppression device according to claim 1, characterized in that: The transient voltage suppression device is a unidirectional transient voltage suppression device.

Images