Semiconductor device
By adopting a double-layer P-type cap structure and partition layer in GaN high-electron mobility transistor, the low gate breakdown voltage and high leakage current problems caused by traditional P-type caps are solved, and higher reliability and efficiency are achieved.
Patent Information
- Application Number
- CN202421512736.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-06-28
- Publication Date
- 2025-04-18
- Estimated Expiration
- 2034-06-28
AI Technical Summary
In traditional gallium nitride high electron mobility transistors, the higher concentration of the P-type cap layer results in a lower gate breakdown voltage and a higher gate leakage current, affecting the reliability and performance of the device.
A double-layer P-type capping layer structure is adopted, wherein the first P-type capping layer is used to deplete two-dimensional electronic gas, the second P-type capping layer is used to reduce gate current, and a partition layer is provided between the two layers to reduce the formation of the peak electric field.
It improves the gate breakdown voltage of the device, reduces the gate leakage current, and improves the reliability and performance of the device.
Smart Images
Figure CN222776516U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to a semiconductor power device. Background Art
[0002] Compared with silicon materials, gallium nitride materials have larger energy band gaps, higher electron mobility, saturated electron velocity and breakdown electric field. Gallium nitride high electron mobility transistors are common gallium nitride power devices and are widely used in high-frequency applications such as radio frequency and microwave.
[0003] An existing GaN high electron mobility transistor structure is as follows Figure 1 As shown, the device shown in 1a is provided with a buffer layer located above the substrate layer, a channel layer located above the buffer layer, a barrier layer located above the channel layer, a traditional P-type cap layer 104 located above the barrier layer, and a gate metal layer 106 located above the traditional P-type cap layer 104. The channel layer and the barrier layer form a heterojunction, and a two-dimensional electron gas (2DEG) is formed on the surface of the channel layer below the heterojunction. One of the main functions of the traditional P-type cap layer 104 is to form a Schottky contact with the gate metal layer 106 above, reducing the gate current when the gate is positively pressurized. Another main function of the traditional P-type cap layer 104 is to deplete the two-dimensional electron gas located below the traditional P-type cap layer 104 to form an enhancement device. In order to reduce the chance of the enhancement device being mistakenly turned on, the threshold voltage needs to reach a sufficiently high value. In order to achieve a higher threshold voltage, the traditional P-type cap layer 104 generally requires a higher concentration to enhance the ability to deplete the two-dimensional electron gas located below it. However, as shown in 1b, the traditional depletion region 109 in the higher concentration traditional P-type cap layer 104 is shallower when the gate is positively pressurized, and a peak electric field is formed at the corner position 110 on the surface of the traditional P-type cap layer 104, resulting in a lower gate breakdown voltage and a higher gate leakage current of the device, affecting the reliability and performance of the device. Utility Model Content
[0004] In order to solve the above-mentioned problems, the utility model provides a semiconductor device, which includes a substrate layer located at the bottom of the device, a buffer layer located above the substrate layer, a channel layer located above the buffer layer, a barrier layer located above the channel layer, a P-type cap layer located above the barrier layer, a gate metal layer located above the P-type cap layer, and a source metal layer and a drain metal layer located on both sides of the gate metal layer, respectively. The channel layer and the barrier layer form a heterojunction and form a two-dimensional electron gas on the surface of the channel layer below the heterojunction; the P-type cap layer includes a first P-type cap layer located above the barrier layer and a second P-type cap layer located above the first P-type cap layer, and a separation layer is further provided near the side between the first P-type cap layer and the second P-type cap layer, the first P-type cap layer is used to deplete the two-dimensional electron gas on the surface of the channel layer below it when the device is turned off, the second P-type cap layer is used to reduce the gate current when the gate is positively pressurized, and the separation layer is used to reduce the peak electric field formed at the corner position of the surface of the second P-type cap layer.
[0005] Furthermore, the thickness of the first P-type cap layer is in the range of 10-1000 nm, the thickness of the second P-type cap layer is in the range of 1-100 nm, and the thickness of the separation layer is in the range of 1-100 nm.
[0006] Furthermore, after the thickness of the separation layer is increased, a groove may be formed in the middle of the surface of the second P-type cap layer.
[0007] Furthermore, the sidewalls of the separation layer are vertical sidewalls, the sidewalls of the groove are vertical sidewalls to form right-angle corners, and the peak electric field is newly formed at the right-angle corners.
[0008] Furthermore, the sidewalls of the separation layer are inclined sidewalls, and the sidewalls of the groove are inclined sidewalls to form obtuse corners. Compared with vertical sidewalls, the inclined sidewalls further reduce the peak electric field formed at the obtuse corners.
[0009] Furthermore, the separation layer extends to the source metal layer and the drain metal layer located on both sides of the gate metal layer respectively and covers the side wall of the first P-type cap layer and the surface of the barrier layer located thereunder.
[0010] The P-type cap layer of the utility model is provided with two layers, the high concentration of the first P-type cap layer of the lower layer ensures that the threshold voltage of the device can reach a higher value, reducing the chance of the enhancement type device being mistakenly turned on, and the thickness of the second P-type cap layer of the upper layer is thinner. When the gate is positively pressurized, the upper P-type cap layer will be completely depleted, reducing the peak electric field formed at the corner of the surface of the upper P-type cap layer. Therefore, the gate breakdown voltage of the device is higher, and the gate leakage current is also lower, which improves the reliability and performance of the device. BRIEF DESCRIPTION OF THE DRAWINGS
[0011] Figure 1 It is a cross-sectional schematic diagram of an existing high electron mobility transistor structure.
[0012] Figure 2 The figure is a cross-sectional schematic diagram of a device structure according to an embodiment of the present invention.
[0013] Figure 3 It is a cross-sectional schematic diagram of a device structure according to another embodiment of the utility model.
[0014] Figure 4 It is a cross-sectional schematic diagram of a device structure according to another embodiment of the utility model.
[0015] Figure 5 It is a cross-sectional schematic diagram of a device structure according to another embodiment of the utility model.
[0016] Figure 6 It is a cross-sectional schematic diagram of a device structure according to another embodiment of the utility model.
[0017] Figure 7 This is an embodiment of a method for forming a device structure of the utility model. DETAILED DESCRIPTION
[0018] The present invention is described in detail below in conjunction with the accompanying drawings and embodiments. It should be noted that the corresponding position words described in this document, such as "upper", "lower", "left", "right", "front", "back", "vertical", "horizontal", and "vertical", correspond to the relative positions of the reference diagrams. The specific implementation does not limit the fixed direction. The devices in the accompanying drawings are not necessarily drawn to a specific scale. The straight lines shown as the boundaries of the doped regions and grooves in the accompanying drawings, as well as the sharp angles formed by the boundaries, are generally not straight lines and precise angles in actual applications.
[0019] Reference Figure 2 2a is a cross-sectional schematic diagram of a device structure of the first embodiment of the utility model, the structure comprising:
[0020] a substrate layer 200 at the bottom;
[0021] a buffer layer 201 located above the substrate layer 200;
[0022] A channel layer 202 located above the buffer layer 201;
[0023] a barrier layer 203 located above the channel layer 202;
[0024] A first P-type cap layer 204 a located above the barrier layer 203 ;
[0025] A second P-type cap layer 204 b located above the first P-type cap layer 204 a ;
[0026] A separation layer 205 located between the first P-type cap layer 204a and the second P-type cap layer 204b and close to the side edge thereof;
[0027] A gate metal layer 206 located above the second P-type cap layer 204 b ;
[0028] A source metal layer 207 located on the left of the gate metal layer 206 and a drain metal layer 208 located on the right;
[0029] In the above structure, the channel layer 202 and the barrier layer 203 form a heterojunction, and a two-dimensional electron gas (2DEG) is formed on the surface of the channel layer 202 located below the heterojunction, forming a current channel between the source metal layer 207 and the drain metal layer 208 when the device is turned on.
[0030] In the above structure, the first P-type cap layer 204 a depletes the two-dimensional electron gas on the surface of the channel layer 202 thereunder when the device is turned off, thereby forming an enhancement-mode device.
[0031] In the above structure, the second P-type cap layer 204 b forms a Schottky contact with the gate metal layer 206 located thereon, so as to reduce the gate current when the gate is subjected to a positive pressure.
[0032] In the above structure, the doping concentration of the first P-type cap layer 204a and the second P-type cap layer 204b is the same, and the doping concentration range is 1×10 16 – 1x10 21 cm -3 ;
[0033] In the above structure, the thickness of the first P-type cap layer 204a is in the range of 10-1000 nm, and the thickness of the second P-type cap layer 204b is smaller, in the range of 1-100 nm.
[0034] The thickness of the spacer layer 205 is in the range of 1-100 nm. The material of the spacer layer 205 includes materials such as gallium oxide (GaO), gallium oxynitride (GaON), aluminum nitride (AlN) whose energy band gap is greater than the energy band gap of the material of the first P-type cap layer or a combination thereof, and is used to separate the first P-type cap layer 204a and the second P-type cap layer 204b, so that the second P-type cap layer 204b will be completely depleted when the gate is positively pressed; as shown in 2b, the second P-type cap layer 204b will be completely depleted when the gate is positively pressed, reducing the peak electric field formed at the corner position 110 on the surface of the second P-type cap layer 204b, reducing the gate leakage current of the device and increasing the gate breakdown voltage of the device. At the same time, the position of the highest electric field is moved from the corner position 110 on the surface of the second P-type cap layer 204b to the plane position 211 in the middle of the surface of the second P-type cap layer 204b.
[0035] In the above structure, the side walls of the first P-type cap layer 204a and the second P-type cap layer 204b are formed by etching, and there are many defects on the surface of the wall. The highest electric field position is moved from the corner 110 of the second P-type cap layer 204b surface to the plane position 211 in the middle of the second P-type cap layer 204b surface, increasing the distance between the highest electric field and the surface defects of the side walls of the second P-type cap layer 204b, further reducing the gate leakage current of the device and increasing the gate breakdown voltage of the device.
[0036] Example 2
[0037] A variation of the device implementation of the utility model is as follows Figure 3 As shown, and Figure 2 The difference between the embodiments is that the doping concentration of the second P-type cap layer 204b is lower than that of the first P-type cap layer 204a. Figure 2 The doping concentration of the second P-type cap layer 204b is small. In addition, the thickness of the second P-type cap layer 204b is relatively large. Figure 2 The thickness of the second P-type cap layer 204b is large.
[0038] In the above structure, under the same gate forward bias and the second P-type cap layer can be completely depleted, the lower the doping concentration of the second P-type cap layer 204b, the greater the allowable thickness of the second P-type cap layer 204b, and the greater the thickness of the second P-type cap layer 204b, the easier the process control. At the same time, the lower the doping concentration of the second P-type cap layer 204b, the more difficult the process control. When designing the second P-type cap layer 204b, it is necessary to strike a balance between thickness and doping concentration.
[0039] Example 3
[0040] A variation of the device implementation of the utility model is as follows Figure 4 As shown, and Figure 3 The difference between the embodiments is that the thickness of the separation layer 205 between the first P-type cap layer 204a and the second P-type cap layer 204b is relatively large. Figure 3 The thickness of the spacer layer 205 is large. Since the sidewalls of the spacer layer 205 are vertical or nearly vertical, when the spacer layer 205 is thicker, the middle position of the surface of the second P-type cap layer 204b above the spacer layer 205 is concave to form a right angle or nearly right angle corner 212.
[0041] In the above structure, under the same gate forward bias, the thicker the spacer layer 205 is, the smaller the electric field formed at the surface corner 110 of the second P-type cap layer 204b is, and the larger the electric field formed at the surface corner at the right angle corner 212 of the second P-type cap layer 204b is. When designing the thickness of the P-type cap layer 204b, it is necessary to balance the peak electric fields appearing at the surface corners 110 and 212 of the second P-type cap layer 204b.
[0042] Example 4
[0043] In order to avoid the above problems, a modified device implementation of the present invention is as follows: Figure 5 As shown, and Figure 4 The difference of the embodiment is that the sidewall of the spacer layer 205 between the first P-type cap layer 204a and the second P-type cap layer 204b is inclined instead of vertical. The middle position of the surface of the second P-type cap layer 204b above the spacer layer 205 is concave to form an obtuse corner 222, which is smaller than Figure 4 The right-angled or nearly right-angled corner 212 formed on the surface of the second P-type cap layer 204 b of the embodiment is closer to a plane.
[0044] In the above structure, under the same gate forward bias, the electric field formed at the obtuse corner 222 of the second P-type cap layer 204b is larger than that at the Figure 4 The electric field formed at the right-angle corner 212 of the second P-type cap layer 204 b of the embodiment is small, the gate leakage current of the device is small, and the gate breakdown voltage is high.
[0045] In the above structure, the sidewall inclination angle of the spacer layer 205 depends on the process conditions. The larger the sidewall inclination angle of the spacer layer 205, the larger the angle of the obtuse corner 222 on the surface of the second P-type cap layer 204b located above it, and the closer it is to the plane. Under the same gate forward bias, the smaller the electric field formed by the obtuse corner 222 on the surface of the second P-type cap layer 204b, the smaller the gate leakage current of the device, and the higher the gate breakdown voltage.
[0046] Example 5
[0047] A variation of the device implementation of the utility model is as follows Figure 6 As shown, and Figure 2 The difference between the embodiments is that the separation layer 205 extends to the source metal layer 207 to the left and to the drain metal layer 208 to the right, and covers the sidewall of the first P-type cap layer 204 a and the surface of the barrier layer 203 thereunder.
[0048] In the above structure, the separation layer 205 helps to repair the sidewalls of the first P-type cap layer 204a and the surface defects of the barrier layer 203 thereunder, thereby reducing the gate leakage current of the device and increasing the gate breakdown voltage of the device.
[0049] Those skilled in the art should know that the structural features mentioned in the above-mentioned embodiments of the present invention can be combined with each other to form more device structures of the embodiments of the present invention.
[0050] Example 6
[0051] According to the structural features of the above-mentioned embodiments of the present invention, combined with the existing GaN high electron mobility transistor manufacturing process, a variety of methods for forming the device embodiments of the present invention can be obtained. An exemplary method for forming the device embodiment of the present invention is as follows: Figure 7 Shown:
[0052] In the first step, a buffer layer 201 is formed on the substrate layer 200, a channel layer 202 is formed on the buffer layer 201, and then a barrier layer 203 is formed on the channel layer 202, as shown in FIG7a.
[0053] The material of the substrate layer 200 is usually silicon (Si), and may also be other suitable materials such as gallium nitride (GaN), silicon carbide (SiC), and sapphire.
[0054] The buffer layer 201 may include one material or a combination of multiple materials such as aluminum gallium nitride (AlGaN), aluminum nitride (AlN), gallium nitride (GaN), etc. The one material or the combination of multiple materials may include doping elements such as carbon (C) and iron (Fe), which is beneficial to reduce leakage current and crystal layer dislocation.
[0055] The material of the channel layer 202 is usually gallium nitride (GaN), but may also be other materials, and the energy band gap of the channel layer 202 is smaller than the energy band gap of the material of the barrier layer 203 located thereon.
[0056] The material of the barrier layer 203 is usually aluminum gallium nitride (AlGaN), but may also be other materials, and the energy band gap of the barrier layer 203 is larger than the energy band gap of the material of the channel layer 202 located therebelow.
[0057] The above structure can be formed by chemical vapor deposition, physical vapor deposition, epitaxial growth and other processes.
[0058] In the second step, a preliminary first P-type cap layer 294 a is formed on the barrier layer 203 , and then a preliminary separation layer 295 is formed on the preliminary first P-type cap layer 294 a , as shown in FIG7 b .
[0059] The material of the preliminary first P-type cap layer 294 a is usually doped gallium nitride (GaN), and may also be doped aluminum gallium nitride (AlGaN) or other materials, wherein the material contains magnesium (Mg) or other suitable P-type doping elements.
[0060] The material of the preliminary separation layer 295 includes gallium oxide (GaO), gallium oxynitride (GaON), aluminum nitride (AlN), etc., whose energy band gap is larger than the energy band gap of the material of the first P-type cap layer, or a combination thereof.
[0061] The above structure can be formed by chemical vapor deposition, physical vapor deposition, epitaxial growth and other processes.
[0062] In the third step, photolithography, dry etching, wet etching and other process steps are performed on the surface of the preliminary separation layer 295 to form a patterned two-step separation layer 285, as shown in 7c.
[0063] In the fourth step, a preliminary second P-type cap layer 294b is formed on the surface of the second-step separation layer 285. A portion of the preliminary second P-type cap layer 294b is connected to the preliminary first P-type cap layer 294a located therebelow through the patterned separation layer 285, as shown in 7d.
[0064] The material of the preliminary second P-type cap layer 294 b is the same as that of the preliminary first P-type cap layer 294 a , and the doping concentration of the preliminary second P-type cap layer 294 b is equal to or less than the doping concentration of the first P-type cap layer 294 a .
[0065] In the fifth step, a preliminary gate metal layer 296 is formed on the surface of the preliminary second P-type cap layer 294b, as shown in 7e.
[0066] The preliminary gate metal layer 296 may be formed by processes such as evaporation and sputtering, and its constituent materials may include but are not limited to metals such as titanium (Ti), nickel (Ni), tungsten (W), aluminum (Al), copper (Cu), platinum (Pt), gold (Au), their alloys, their compounds or other appropriate materials.
[0067] Typically, the preliminary gate metal layer 296 forms a Schottky contact with the preliminary second P-type cap layer 294 b thereunder.
[0068] In the sixth step, photolithography, dry etching, wet etching and other process steps are performed on the surface of the preliminary gate metal layer 296 to form a patterned gate metal layer 206, a patterned second P-type cap layer 204b, a patterned separation layer 205 and a patterned first P-type cap layer 204a, as shown in 7f.
[0069] In the eighth step, a source metal layer 207 is formed on the left side of the gate metal layer 206 and a drain metal layer 208 is formed on the right side thereof, as shown in FIG7g.
[0070] The source metal layer 207 and the drain metal layer 208 may be formed by processes such as evaporation and sputtering, and their constituent materials may include but are not limited to metals such as titanium (Ti), nickel (Ni), tungsten (W), aluminum (Al), copper (Cu), platinum (Pt), gold (Au), their alloys, their compounds or other appropriate materials.
[0071] The method of forming the patterned source metal layer 207 and the drain metal layer 208 may include photolithography, dry etching, wet etching and other process steps.
[0072] Typically, the source metal layer 207 and the drain metal layer 208 form ohmic contacts with the channel layer 202 thereunder.
[0073] Those skilled in the art should know that the above manufacturing steps only list key steps and do not show the complete steps of forming a device. Specific detailed manufacturing steps can be obtained based on common manufacturing process steps and common sense knowledge in the field and can be appropriately increased, decreased or changed.
Claims
1. A semiconductor device, comprising a substrate layer at the bottom of the device, a buffer layer above the substrate layer, a channel layer above the buffer layer, a barrier layer above the channel layer, a P-type cap layer above the barrier layer, a gate metal layer above the P-type cap layer, and a source metal layer and a drain metal layer respectively located on both sides of the gate metal layer, wherein the channel layer and the barrier layer form a heterojunction and a two-dimensional electron gas is formed on the surface of the channel layer below the heterojunction; characterized in that: The P-type cap layer includes a first P-type cap layer located above the barrier layer and a second P-type cap layer located above the first P-type cap layer. A separation layer is also provided near the side between the first P-type cap layer and the second P-type cap layer. The first P-type cap layer is used to deplete the two-dimensional electron gas on the surface of the channel layer below it when the device is turned off. The second P-type cap layer is used to reduce the gate current when the gate is positively pressurized. The separation layer is used to reduce the peak electric field formed at the corner position of the surface of the second P-type cap layer.
2. The semiconductor device according to claim 1, wherein The thickness of the first P-type cap layer is in the range of 10-1000 nm, the thickness of the second P-type cap layer is in the range of 1-100 nm, and the thickness of the separation layer is in the range of 1-100 nm.
3. The semiconductor device according to claim 1, wherein The middle position of the surface of the second P-type cap layer is concave to form a groove.
4. The semiconductor device according to claim 3, characterized in that The sidewalls of the separation layer are vertical sidewalls, the sidewalls of the grooves are vertical sidewalls to form right-angle corners, and the peak electric field is newly formed at the right-angle corners.
5. The semiconductor device according to claim 3, wherein: The sidewalls of the separation layer are inclined sidewalls, and the sidewalls of the grooves are inclined sidewalls to form obtuse corners, so as to reduce the peak electric field formed at the obtuse corners.
6. The semiconductor device according to claim 1, wherein: The separation layer extends to the source metal layer and the drain metal layer located on both sides of the gate metal layer respectively and covers the side wall of the first P-type cap layer and the surface of the barrier layer located therebelow.