MOSFET layout and MOSFET device

Abstract

According to the MOSFET layout and the MOSFET device provided by the invention, the gate resistance adjusting region is arranged in the third gate metal connecting region, and the polycrystalline silicon partial voltage of different trench gates can be adjusted through layout structure optimization, so that the actual voltage of the trench gates can be adjusted.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of semiconductor technology and, in particular, to a MOSFET layout and a MOSFET device. Background Art

[0002] The gate material of MOSFET devices is generally heavily doped polysilicon. When the MOSFET device is working, the gate voltage needs to be connected from the gate metal layer to the gate polysilicon in the gate trench. In the prior art, the gate control channel is uniformly set and the gate current cannot be controlled and adjusted. Summary of the invention

[0003] In order to solve or alleviate the problems in the prior art, the present application provides a MOSFET layout and a MOSFET device to solve the technical problem in the prior art that the gate control channel is uniformly set and the gate current size cannot be controlled and adjusted.

[0004] In a first aspect, the present application provides a MOSFET layout, including: a gate metal connection region, a gate metal region, a gate contact hole region, a source contact hole region, and a source metal region;

[0005] The source metal region is arranged in the area surrounded by the gate metal connection region, the source contact hole region is arranged on the source metal region, and the source metal region is spaced apart from the gate metal region;

[0006] The gate metal connection region includes a first gate metal connection region, a second gate metal connection region and a third gate metal connection region in sequence;

[0007] The first gate metal connection region and the second gate metal connection region are arranged at opposite sides of the source metal region, the gate metal region crosses the source metal region and contacts the first gate metal connection region and the second gate metal connection region respectively, forming the first gate metal contact region and the second gate metal contact region respectively, and the gate contact hole regions on the first gate metal contact region and the second gate metal contact region are arranged alternately;

[0008] The third gate metal connection region is provided with a gate resistance adjustment region;

[0009] A gate lead-out region is disposed at the junction of the second gate metal connection region and the third gate metal connection region.

[0010] Compared with the prior art, the MOSFET layout provided in the present application has a gate resistance adjustment area in the third gate metal connection area, and can adjust the polysilicon voltage division of different trench gates by optimizing the layout structure, thereby adjusting the actual trench gate acceptance voltage.

[0011] In a second aspect, the present application further provides a MOSFET device, prepared according to the layout described in the first aspect, specifically comprising: a device body, a dielectric layer and a gate metal layer;

[0012] The dielectric layer is arranged on the upper surface of the device body, the gate metal layer is arranged on the upper surface of the dielectric layer, and the gate metal layer is connected to the metal arranged in the gate contact hole in the dielectric layer;

[0013] A gate resistance adjustment region is arranged on the gate metal layer.

[0014] As a preferred embodiment of the present application, the gate resistance adjustment region is provided with a resistive material.

[0015] As a preferred embodiment of the present application, the resistive material is a resistive metal or polysilicon having electrical resistance.

[0016] Compared with the prior art, the beneficial effects of the MOSFET provided in the present application are the same as the beneficial effects of the technical solution provided in the first aspect, which will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. Some specific embodiments of the present application will be described in detail in an illustrative and non-restrictive manner with reference to the drawings. The same reference numerals in the drawings indicate the same or similar components or parts. It should be understood by those skilled in the art that these drawings are not necessarily drawn to scale. In the drawings:

[0018] Figure 1 It is a schematic diagram of a MOSFET layout provided by the present application;

[0019] Figure 2 It is a structural schematic diagram of a MOSFET device provided by the present application; DETAILED DESCRIPTION

[0020] In order to enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only embodiments of a part of the present application, not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work should fall within the scope of protection of the present application.

[0021] First, as Figure 1As shown, the present application provides a MOSFET layout, including: a gate metal connection region, a gate metal region 7, a gate contact hole region 6, a source contact hole region 5 and a source metal region 4;

[0022] The source metal region 4 is arranged in the area surrounded by the gate metal connection region, the source contact hole region 5 is arranged on the source metal region 4, and the source metal region 4 is spaced apart from the gate metal region 7;

[0023] The gate metal connection region comprises a first gate metal connection region 1, a second gate metal connection region 2 and a third gate metal connection region 3 in sequence;

[0024] The first gate metal connection region 1 and the second gate metal connection region 2 are arranged on opposite sides of the source metal region 4, the gate metal region 7 crosses the source metal region 4 and contacts the first gate metal connection region 1 and the second gate metal connection region 2 respectively, forming a first gate metal contact region and a second gate metal contact region respectively, and the gate contact hole regions 6 on the first gate metal contact region and the second gate metal contact region are arranged alternately;

[0025] The third gate metal connection region 3 is provided with a gate resistance adjustment region 8;

[0026] A gate lead-out region 9 is provided at the junction of the second gate metal connection region 2 and the third gate metal connection region 3 , and the gate lead-out region 9 is a pin.

[0027] Second, as Figure 2 As shown, the present application also provides a MOSFET device, which is prepared according to the layout described in the first aspect, and specifically includes: a device body 10, a dielectric layer 11 and a gate metal layer 12;

[0028] The dielectric layer is disposed on the upper surface of the device body 10, the gate metal layer 12 is disposed on the upper surface of the dielectric layer 11, and the gate metal connection layer 12 is connected to the metal disposed in the gate contact hole 4 in the dielectric layer 11;

[0029] A gate resistance adjustment region 8 is disposed on the gate metal layer 12 .

[0030] Preferably, the gate resistance adjustment region 8 is provided with a resistive material.

[0031] Preferably, the resistive material is a resistive metal or polysilicon having electrical resistance.

[0032] The MOSFET layout and MOSFET device provided in the present application have a gate resistance adjustment area in the third gate metal connection area, and the polysilicon voltage division of different trench gates can be adjusted by optimizing the layout structure, thereby adjusting the actual trench gate voltage.

[0033] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A MOSFET layout, characterized in that: include: A gate metal connection region, a gate metal region, a gate contact hole region, a source contact hole region and a source metal region; The source metal region is arranged in the area surrounded by the gate metal connection region, the source contact hole region is arranged on the source metal region, and the source metal region is spaced apart from the gate metal region; The gate metal connection region includes a first gate metal connection region, a second gate metal connection region and a third gate metal connection region in sequence; The first gate metal connection region and the second gate metal connection region are arranged at opposite sides of the source metal region, the gate metal region crosses the source metal region and contacts the first gate metal connection region and the second gate metal connection region respectively, forming the first gate metal contact region and the second gate metal contact region respectively, and the gate contact hole regions on the first gate metal contact region and the second gate metal contact region are arranged alternately; The third gate metal connection region is provided with a gate resistance adjustment region; A gate lead-out region is disposed at the junction of the second gate metal connection region and the third gate metal connection region.

2. A MOSFET device, characterized in that: The layout preparation according to claim 1 specifically comprises: a device body, a dielectric layer and a gate metal layer; The dielectric layer is arranged on the upper surface of the device body, the gate metal layer is arranged on the upper surface of the dielectric layer, and the gate metal layer is connected to the metal arranged in the gate contact hole in the dielectric layer; A gate resistance adjustment region is arranged on the gate metal layer.

3. A MOSFET device as claimed in claim 2, characterized in that: The gate resistance adjustment region is provided with a resistive material.

4. A MOSFET device as claimed in claim 3, characterized in that: The resistive material is resistive metal or polysilicon having electrical resistance.

Images