Trench gate silicon carbide VDMOS with gate protection structure
By designing the trench gate structure and building a reverse pn junction and protective layer in the silicon carbide VDMOS device, the problem of low voltage resistance of the device is solved, and effective protection and reliability of the gate are achieved.
Patent Information
- Application Number
- CN202421461062.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-06-25
- Publication Date
- 2025-04-18
- Estimated Expiration
- 2034-06-25
AI Technical Summary
The gate voltage withstandability of silicon carbide VDMOS devices is low, and the gate voltage fluctuates greatly in harsh working environments, affecting the reliability of the device.
A trench gate silicon carbide VDMOS with a gate protection structure is designed. By constructing a reverse pn junction and a protective layer inside the device, the thickness and doping concentration of the pn junction are controlled, and a source discharge structure inside the device is formed to effectively protect the gate.
By constructing a protection structure, the electric field concentration at the corners of the gate dielectric layer is suppressed, the gate reliability of the device is improved, and while ensuring device performance, the device's voltage withstandability is enhanced.
Smart Images
Figure CN222776521U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to a trench gate silicon carbide VDMOS with a gate protection structure. Background Art
[0002] Silicon carbide MOSFET is a typical representative of silicon carbide power devices, and is widely used in electric vehicles, aerospace, power conversion and other fields. The development of device structure and preparation process has promoted the reduction of device on-resistance and the improvement of reliability. However, due to the characteristics of silicon carbide materials, the quality of the silicon dioxide gate dielectric generated is lower than that of silicon process and the gap in the work function of the material has requirements on the thickness of the insulating layer of the gate dielectric. Its gate withstand voltage is low. In relatively harsh working environments, the gate voltage of the device is affected by the outside world, the voltage fluctuation range is large, and its reliability is threatened. Utility Model Content
[0003] The technical problem to be solved by the utility model is to provide a trench gate silicon carbide VDMOS with a gate protection structure to improve gate reliability.
[0004] The utility model is implemented as follows: a trench gate silicon carbide VDMOS with a gate protection structure, comprising:
[0005] Silicon carbide substrate,
[0006] A drift layer, wherein the lower side of the drift layer is connected to the upper side of the silicon carbide substrate;
[0007] A well region, wherein a lower side of the well region is connected to an upper side of the drift layer;
[0008] An N-type source region, wherein the lower side of the N-type source region is connected to the upper side of the well region;
[0009] A P-type source region, wherein the lower side of the P-type source region is connected to the upper side of the well region, and the inner side of the P-type source region is connected to the outer side of the N-type source region;
[0010] A gate dielectric layer, wherein the bottom of the gate dielectric layer is connected to the upper side of the drift layer, and the outer side of the gate dielectric layer is respectively connected to the inner side of the well region and the inner side of the N-type source region; a groove is provided in the gate dielectric layer;
[0011] A protective layer, wherein the lower side of the protective layer is connected to the upper side of the P-type source region;
[0012] A source metal layer, the source metal layer is connected to the P-type source region and the N-type source region respectively;
[0013] A gate metal layer, the gate metal layer is disposed in the groove, and the gate metal layer is connected to the protection layer;
[0014] and a drain metal layer connected to the lower side of the silicon carbide substrate.
[0015] Furthermore, it also includes an insulating layer, a first interconnect metal and a second interconnect metal; the insulating layer is respectively connected to the inner side of the protective layer, the outer side of the source metal layer, the inner side of the source metal layer, the outer side of the gate dielectric layer, the upper side of the source metal layer, the upper side of the gate dielectric layer and the upper side of the gate metal layer; the first interconnect metal is respectively connected to the gate metal layer and the protective layer; the second interconnect metal layer is connected to the source metal layer.
[0016] Furthermore, the silicon carbide substrate and the protective layer are both N-type, and the well region is P-type.
[0017] Furthermore, the distance between the source metal layer and the protection layer is 100 nm; the distance between the source metal layer and the gate dielectric layer is 100 nm.
[0018] The advantages of the utility model are:
[0019] 1. The device adopts a trench gate structure, and the breakdown that may occur due to electric field concentration at the corner of the gate dielectric layer is suppressed by controlling the thickness of the well region;
[0020] Second, a reverse pn junction, i.e., a silicon carbide Zener diode, is constructed between the gate-source electrodes inside the device. By controlling the thickness and doping concentration of the pn junction, the device is ensured to avalanche and break down when the gate-source voltage exceeds the gate protection voltage, forming a source region discharge structure inside the device to effectively protect the gate.
[0021] 3. The constructed protection layer does not affect the current path of the normal operation of the device, that is, it can improve the gate reliability of the device while ensuring that the device performance is not degraded. BRIEF DESCRIPTION OF THE DRAWINGS
[0022] The present invention will be further described below in conjunction with the embodiments with reference to the accompanying drawings.
[0023] Figure 1 The utility model is a schematic diagram of a trench gate silicon carbide VDMOS with a gate protection structure.
[0024] Figure 2 for Figure 1 Sectional view along line A-A'.
[0025] Figure 3 for Figure 1 Cross-sectional view along line B-B'.
[0026] Figure 4 The utility model is a flow chart of a method for preparing a trench gate silicon carbide VDMOS with a gate protection structure.
[0027] Figure 5 This is a cross-sectional view of the process of a trench gate silicon carbide VDMOS with a gate protection structure according to the utility model. Figure 1 .
[0028] Figure 6 This is a cross-sectional view of the process of a trench gate silicon carbide VDMOS with a gate protection structure according to the utility model. Figure 2 .
[0029] Figure 7 This is a cross-sectional view of the process of a trench gate silicon carbide VDMOS with a gate protection structure according to the utility model. Figure 3 .
[0030] Figure 8 This is a cross-sectional view of the process of a trench gate silicon carbide VDMOS with a gate protection structure according to the utility model. Figure 4 .
[0031] Fig. 9 This is a cross-sectional view of the process of a trench gate silicon carbide VDMOS with a gate protection structure according to the utility model. Figure 5 .
[0032] Fig.10 This is a cross-sectional view of the process of a trench gate silicon carbide VDMOS with a gate protection structure according to the utility model. Figure 6 .
[0033] Fig.11 This is a cross-sectional view of the process of a trench gate silicon carbide VDMOS with a gate protection structure according to the utility model. Figure 7 .
[0034] Fig.12 This is a cross-sectional view of the process of a trench gate silicon carbide VDMOS with a gate protection structure according to the utility model. Figure 8 .
[0035] Fig.13 This is a cross-sectional view of the process of a trench gate silicon carbide VDMOS with a gate protection structure according to the utility model. Figure 9 .
[0036] Fig.14 This is a cross-sectional view of the process of a trench gate silicon carbide VDMOS with a gate protection structure according to the utility model. Figure 10 .
[0037] Fig.15 This is a cross-sectional view of the process of a trench gate silicon carbide VDMOS with a gate protection structure according to the utility model. Figure 10 one.
[0038] Fig.16 This is a cross-sectional view of the process of a trench gate silicon carbide VDMOS with a gate protection structure according to the utility model. Figure 10 two.
[0039] Fig.17 This is a cross-sectional view of the process of a trench gate silicon carbide VDMOS with a gate protection structure according to the utility model. Figure 10 three. DETAILED DESCRIPTION
[0040] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.
[0041] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.
[0042] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "in contact with ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or part discussed below can be represented as a second element, component, region, layer or part.
[0043] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of one element or feature described in the figures to other elements or features. It should be understood that, in addition to the orientations described in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.
[0044] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.
[0045] like Figures 15 to 17 As shown, the embodiment of the present application provides a trench gate silicon carbide VDMOS with a gate protection structure, including:
[0046] Silicon carbide substrate 101,
[0047] A drift layer 102, wherein the lower side of the drift layer 102 is connected to the upper side of the silicon carbide substrate 101;
[0048] A well region 103, wherein the bottom side of the well region 103 is connected to the top side of the drift layer 102;
[0049] An N-type source region 104, wherein the lower side of the N-type source region 104 is connected to the upper side of the well region 103;
[0050] A P-type source region 105, wherein the lower side of the P-type source region 105 is connected to the upper side of the well region 103, and the inner side of the P-type source region 105 is connected to the outer side of the N-type source region 104;
[0051] A gate dielectric layer 106, wherein the bottom of the gate dielectric layer 106 is connected to the upper side of the drift layer 102, and the outer side of the gate dielectric layer 106 is respectively connected to the inner side of the well region 103 and the inner side of the N-type source region 104; a groove 1061 is provided in the gate dielectric layer 106;
[0052] A protection layer 107, wherein the lower side of the protection layer 107 is connected to the upper side of the P-type source region 105;
[0053] A source metal layer 108 , wherein the source metal layer 108 is connected to the P-type source region 105 and the N-type source region 104 ;
[0054] A gate metal layer 109 , wherein the gate metal layer 109 is disposed in the groove 1061 , and the gate metal layer 109 is connected to the protection layer 107 ;
[0055] An insulating layer 110, a first interconnecting metal 111 and a second interconnecting metal 112; the insulating layer 110 is respectively connected to the inner side of the protective layer 107, the outer side of the source metal layer 108, the inner side of the source metal layer 108, the outer side of the gate dielectric layer 106, the upper side of the source metal layer 108, the upper side of the gate dielectric layer 106 and the upper side of the gate metal layer 109; the first interconnecting metal 111 is respectively connected to the gate metal layer 109 and the protective layer 107; the second interconnecting metal layer 112 is connected to the source metal layer 108;
[0056] and a drain metal layer 113 , wherein the drain metal layer 113 is connected to the lower side of the silicon carbide substrate 101 .
[0057] like Figures 3 to 17 As shown, the method for preparing the above-mentioned trench gate silicon carbide VDMOS comprises the following steps:
[0058] Step 1: depositing metal on the lower side of the silicon carbide substrate 101 to form a drain metal layer 113; epitaxially growing a drift layer 102 on the silicon carbide substrate 101, wherein the drift layer 102 has a thickness of 3-6 μm;
[0059] Step 2: Form a well region 103 by ion implantation into the drift layer 102, wherein the ion implantation energy is 10-300kev and the depth is 0-900nm;
[0060] Step 3, forming a barrier layer a, etching the barrier layer a to form a through hole, and performing ion implantation into the well region 103 to form an N-type source region 104, wherein the ion implantation energy is 10-200kev and the depth is 0-600nm;
[0061] Step 4, removing the barrier layer a, re-forming the barrier layer a, etching the barrier layer a to form a through hole, and performing ion implantation into the well region 103 to form a P-type source region 105, wherein the ion implantation energy is 10-200kev and the depth is 0-600nm;
[0062] Step 5: remove the original barrier layer a, re-form the barrier layer a, etch the barrier layer a to form a through hole, and etch the well region 103 to the upper side of the drift layer 102, the etching depth is 900nm, and oxidize to form a gate dielectric layer 106;
[0063] Step 6: remove the original barrier layer a, re-form the barrier layer a, etch the barrier layer a to form a through hole, deposit metal, and form a gate metal layer 109;
[0064] Step 7, remove the original barrier layer a, re-form the barrier layer a, etch the barrier layer a to form a through hole, and etch the P-type source region 105 and the N-type source region 104 to a depth of 300 nm; deposit silicon dioxide to form a first insulating region 1101;
[0065] Step 8, remove the original barrier layer a, re-form the barrier layer a, etch the barrier layer a to form a through hole, perform ion implantation on the P-type source region 105 to form a protective layer 107, the implantation energy is 10-100kev, and the depth is 300nm;
[0066] Step 9, remove the original barrier layer a, re-form the barrier layer a, etch the barrier layer a to form a through hole, and etch the P-type source region 105 and the N-type source region 104 to a depth of 300 nm, perform metal deposition, and form a source metal layer 108;
[0067] Step 10, removing the original barrier layer a, re-forming the barrier layer a, etching the barrier layer a to form a through hole, depositing silicon dioxide, forming a second insulating region 1102, the insulating layer 110 includes a first insulating region 1101 and a second insulating region 1102;
[0068] Step 11, remove the original barrier layer a, re-form the barrier layer a, etch the barrier layer a to form a through hole, deposit metal to form a first interconnection metal 111 and a second interconnection metal 112, remove the barrier layer, and complete the preparation.
[0069] The silicon carbide substrate 101 and the protective layer 107 are both N-type, the well region 103 is P-type, and the doping concentration of the silicon carbide substrate 101 is 2e18 cm -3 The doping concentration of the drift layer 102 is 6e16cm -3 The doping concentration of the well region 103 is 1e17 cm -3 The doping concentration of the N-type source region 104 is 2e18cm -3 The doping concentration of the P-type source region 105 is 1e19cm -3 The doping concentration of the protective layer 107 is 6e18cm -3, the gate dielectric layer 106 and the insulating layer 110 are silicon dioxide; the concentration of the N-type silicon carbide substrate 101 is to ensure the formation of a low-resistance ohmic contact with the drain metal layer 113 and reduce the overall on-resistance of the device; the doping concentration of the N-type drift layer 102 is a compromise between the reverse withstand voltage and the on-resistance of the device; the doping concentrations of the N-type source region 104 and the P-type source region 105 are to form an ohmic contact with the source metal layer 108 and reduce the contact resistance; the doping concentration of the N-type protection layer 107 is to control the reverse breakdown voltage of the pn junction with the P-type source region 105 to 18V, so as to achieve protection of the device gate voltage.
[0070] The thickness of the N-type silicon carbide substrate 101 of the device is 1 μm, and the thickness of the N-type drift layer 102 is 3-6 μm, which are adjusted within the above range according to different requirements for the withstand voltage characteristics of the device. The P-type well region 103 extends from the bottom of the P-type source region 105 and the N-type source 104 to the position flush with the bottom of the gate. The thickness of the P-type well region 103 is 300 nm. Such a flush structure can not only reduce the on-resistance of the device, but also effectively suppress the electric field concentration at the corner of the gate, thereby protecting the gate. The thickness of the N-type source region 104 and the P-type source region 105 is 300 nm, the bottom thickness of the gate dielectric layer 106 is 70 nm, and the side wall thickness is 50 nm. The thickness of the N-type protective layer 107 is equal to that of the source metal, both of which are 300 nm. The distance between the source metal layer 108 and the N-type protective layer 107 is 100 nm; the distance between the source metal layer 108 and the gate dielectric layer 106 is 100 nm, which is to form insulation and protection between different structures of the device.
[0071] When a positive voltage is applied to the device gate, the P-type well region 103 near the gate is inverted, forming a conductive channel from the N-type source region 104 to the N-type drift layer 102, and the device is turned on. When no voltage is applied to the gate, the device is turned off, and the pn junction formed by the N-type drift layer 102 and the P-type well region 103 withstands voltage.
[0072] Although the specific implementation methods of the present invention are described above, those skilled in the art should understand that the specific embodiments described are only illustrative and are not intended to limit the scope of the present invention. Equivalent modifications and changes made by those skilled in the art in accordance with the spirit of the present invention should be included in the scope of protection of the claims of the present invention.
Claims
1. A trench gate silicon carbide VDMOS with a gate protection structure, characterized in that: include: Silicon carbide substrate, A drift layer, wherein the lower side of the drift layer is connected to the upper side of the silicon carbide substrate; A well region, wherein a lower side of the well region is connected to an upper side of the drift layer; An N-type source region, wherein the lower side of the N-type source region is connected to the upper side of the well region; A P-type source region, wherein the lower side of the P-type source region is connected to the upper side of the well region, and the inner side of the P-type source region is connected to the outer side of the N-type source region; A gate dielectric layer, wherein the bottom of the gate dielectric layer is connected to the upper side of the drift layer, and the outer side of the gate dielectric layer is respectively connected to the inner side of the well region and the inner side of the N-type source region; a groove is provided in the gate dielectric layer; A protective layer, wherein the lower side of the protective layer is connected to the upper side of the P-type source region; A source metal layer, the source metal layer is connected to the P-type source region and the N-type source region respectively; A gate metal layer, the gate metal layer is disposed in the groove, and the gate metal layer is connected to the protection layer; and a drain metal layer connected to the lower side of the silicon carbide substrate.
2. A trench gate silicon carbide VDMOS with a gate protection structure according to claim 1, characterized in that: It also includes an insulating layer, a first interconnect metal and a second interconnect metal; the insulating layer is respectively connected to the inner side of the protective layer, the outer side of the source metal layer, the inner side of the source metal layer, the outer side of the gate dielectric layer, the upper side of the source metal layer, the upper side of the gate dielectric layer and the upper side of the gate metal layer; the first interconnect metal is respectively connected to the gate metal layer and the protective layer; the second interconnect metal layer is connected to the source metal layer.
3. The trench gate silicon carbide VDMOS with a gate protection structure according to claim 1, characterized in that: The silicon carbide substrate and the protective layer are both N-type, and the well region is P-type.
4. The trench gate silicon carbide VDMOS with a gate protection structure according to claim 1, characterized in that: The distance between the source metal layer and the protection layer is 100 nm; the distance between the source metal layer and the gate dielectric layer is 100 nm.