Chip packaging structure
By designing a chip packaging structure including transmission waveguides and coupling structures in an optical quantum computing chip, the problem of difficulty in improving chip computing power and data transmission capabilities in the prior art is solved, and more efficient data transmission and lower packaging costs are achieved.
Patent Information
- Application Number
- CN202421512182.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-06-28
- Publication Date
- 2025-04-18
- Estimated Expiration
- 2034-06-28
AI Technical Summary
The prior art is difficult to improve the computing power and data transmission capabilities of optical quantum computing chips without increasing the chip size, especially in controlling optical path differences in the submicron order.
By designing a chip package structure, including a first chip, a second chip and a first adapter optical chip, the first adapter optical chip includes a transmission waveguide and a coupling structure, interconnection between the first chip and the second chip is achieved, optical path difference is reduced, and packaging costs are reduced.
It realizes improving the computing power and data transmission effect of the chip without increasing the chip size, while reducing the cost of the chip packaging structure and ensuring the stability of data transmission.
Smart Images
Figure CN222776536U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of packaging, in particular to a chip packaging structure. Background Art
[0002] Quantum information technology is a new type of information technology that follows the laws of quantum mechanics - controls quantum information units - and performs information encoding, storage, transmission, and processing. Common material systems for integrated photonic quantum chips include silicon, silicon nitride, silicon dioxide, lithium niobate thin films, and other material systems. Integrated photonic quantum chip technology based on silicon-based material systems, especially silicon on-insulator (SOI) materials, has developed rapidly in recent years and has attracted much attention due to its advantages such as compatibility with CMOS processes, strong nonlinear effects, high integration density, and large-scale production. Facing future large-scale photonic quantum computing and quantum information processing applications, silicon-based integrated photonic quantum chip technology has made a series of progress in device integration scale, quantum computing application realization, and other aspects, showing great development potential.
[0003] However, due to the limitation of the writing field size of current semiconductor lithography machines, the size of silicon photonic chips for optical quantum computing cannot be further expanded, which limits the size of on-chip networks. On the other hand, the entangled state generated by the on-chip solution for generating two-path or even multi-path NOON states (Number-Path Entangled State) requires that the length difference between each path to the off-chip modulation unit be kept within the coherence length, and the optical path difference needs to be controlled at the sub-micron level. The on-chip entangled state preparation unit and other control modules cannot control this length difference using traditional fiber coupling or lens coupling. Utility Model Content
[0004] The embodiment of the utility model provides a chip packaging structure, which reduces the cost of the chip packaging structure, ensures the data transmission capability of the chip, and improves the computing capability of the chip without increasing the chip size.
[0005] According to one aspect of the present invention, a chip packaging structure is provided, comprising:
[0006] A first chip, a second chip and a first switching optical chip; the first switching optical chip comprises a first transmission waveguide, a first coupling structure and a second coupling structure, and the first transmission waveguide is arranged between the first coupling structure and the second coupling structure;
[0007] The first chip is coupled to the first coupling structure, and the second chip is coupled to the second coupling structure.
[0008] Optionally, the first coupling structure and the second coupling structure include grating structures;
[0009] The first chip overlaps with the first coupling structure in a vertical direction, and the second chip overlaps with the second coupling structure in the vertical direction.
[0010] Optionally, the first chip includes a first grating structure, and the second chip includes a second grating structure;
[0011] The first grating structure overlaps with the first coupling structure in a vertical direction, and the second grating structure overlaps with the second coupling structure in a vertical direction.
[0012] Optionally, the first coupling structure and the second coupling structure include pattern spot converter structures;
[0013] The first chip and the first coupling structure are arranged in a horizontal direction, and the second chip and the second coupling structure are arranged in the horizontal direction.
[0014] Optionally, it further includes a substrate; the first chip, the second chip and the first transfer optical chip are arranged on the substrate;
[0015] The substrate includes a base plate, a semiconductor cooling sheet or a heat sink.
[0016] Optionally, the first coupling structure includes a spot converter structure, and the first chip and the first coupling structure are arranged in a horizontal direction; the second coupling structure includes a grating structure;
[0017] The second chip overlaps with the second coupling structure in a vertical direction.
[0018] Optionally, the chip packaging structure further includes a third chip and a fourth chip, the first chip and the second chip are arranged opposite to each other, and the third chip and the fourth chip are arranged opposite to each other;
[0019] The first chip is coupled to the third chip via the first switching optical chip;
[0020] The first chip is coupled to the fourth chip via the first switching optical chip.
[0021] Optionally, the first switching optical chip also includes a second transmission waveguide, a third coupling structure and a fourth coupling structure, the second transmission waveguide is arranged between the third coupling structure and the fourth coupling structure, and the first transmission waveguide and the second transmission waveguide form a cross-waveguide structure; the third chip is coupled to the third coupling structure, and the fourth chip is coupled to the fourth coupling structure.
[0022] Optionally, the chip packaging structure further includes a second transfer optical chip;
[0023] The second switching optical chip includes a third transmission waveguide, a fifth coupling structure and a sixth coupling structure,
[0024] The fifth coupling structure and the sixth coupling structure include grating structures;
[0025] The third chip overlaps with the fifth coupling structure in a vertical direction, and the fourth chip overlaps with the sixth coupling structure in the vertical direction.
[0026] Optionally, the second chip is coupled to the third chip via the first switching optical chip;
[0027] The second chip is coupled to the fourth chip through the first switching optical chip.
[0028] The chip packaging structure provided by the embodiment of the utility model includes a first chip, a second chip and a first switching optical chip, the first chip is coupled with the first coupling structure, the second chip is coupled with the second coupling structure, and the first switching optical chip is used to realize the interconnection between the first chip and the second chip, thereby reducing the optical path difference of chip transmission and improving the transmission effect of the chip. At the same time, the manufacturing cost of the first switching optical chip is low, the error is small, the cost of the chip packaging structure can be reduced, the data transmission capability of the chip is guaranteed, and the computing capability of the chip is improved without increasing the chip size.
[0029] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present utility model, nor are they intended to limit the scope of the present utility model. Other features of the present utility model will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS
[0030] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.
[0031] Figure 1 A schematic diagram of a top view of a first chip packaging structure provided by an embodiment of the utility model;
[0032] Figure 2 A schematic front view of the first chip packaging structure provided by an embodiment of the utility model;
[0033] Figure 3 A schematic front view of the structure of a first chip provided in an embodiment of the utility model;
[0034] Figure 4 for Figure 3 A schematic diagram of the top view structure of the optical waveguide layer;
[0035] Figure 5 A schematic front view of the structure of the first second chip provided in an embodiment of the utility model;
[0036] Figure 6 A schematic diagram of the front view structure of the first switching optical chip provided in an embodiment of the utility model;
[0037] Figure 7 A schematic diagram of a top view of a second chip packaging structure provided by an embodiment of the utility model;
[0038] Figure 8 A schematic front view of the second chip packaging structure provided by an embodiment of the utility model;
[0039] Fig. 9 A schematic front view of the structure of a second first chip provided by an embodiment of the utility model;
[0040] Fig.10 for Fig. 9 A schematic diagram of the top view structure of the optical waveguide layer;
[0041] Fig.11 A schematic front view of the structure of a second chip provided by an embodiment of the utility model;
[0042] Fig.12 A schematic diagram of the front view structure of a second switching optical chip provided in an embodiment of the utility model;
[0043] Fig.13 for Fig.12 A schematic diagram of the top view structure of the optical waveguide layer;
[0044] Fig.14 A schematic front view of the structure of a third chip packaging structure provided by an embodiment of the utility model;
[0045] Fig.15 A schematic top view of a fourth chip packaging structure provided by an embodiment of the utility model;
[0046] Fig.16 A schematic top view of a fifth chip packaging structure provided by an embodiment of the utility model;
[0047] Fig.17 for Fig.16 Schematic diagram of the three-dimensional structure of the cross-waveguide structure;
[0048] Fig.18 This is a schematic top view of the sixth chip packaging structure provided in an embodiment of the utility model. DETAILED DESCRIPTION
[0049] In order to enable those skilled in the art to better understand the solution of the utility model, the technical solution in the embodiment of the utility model will be clearly and completely described below in conjunction with the drawings in the embodiment of the utility model. Obviously, the described embodiment is only a part of the embodiment of the utility model, not all of the embodiments. Based on the embodiment of the utility model, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the utility model.
[0050] It should be noted that the terms "first", "second", etc. in the specification and claims of the utility model and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the utility model described here can be implemented in an order other than those illustrated or described here. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.
[0051] Figure 1 A schematic diagram of a top view of a first chip packaging structure provided by an embodiment of the utility model, Figure 2 This is a schematic diagram of the front view of the first chip packaging structure provided by the embodiment of the utility model, referring to Figure 1-Figure 2 The chip packaging structure includes a first chip 10, a second chip 20 and a first transfer optical chip 30. The first transfer optical chip 30 includes a first transmission waveguide 31, a first coupling structure 32 and a second coupling structure 33. The first transmission waveguide 31 is arranged between the first coupling structure 32 and the second coupling structure 33; the first chip 10 is coupled to the first coupling structure 32, and the second chip 20 is coupled to the second coupling structure 33.
[0052] Among them, the first chip 10 is provided with a coupling structure corresponding to the first coupling structure 32, and the second chip 20 is provided with a coupling structure corresponding to the second coupling structure 33. The first chip 10 is coupled to the first coupling structure 32, and the second chip 20 is coupled to the second coupling structure 33. Therefore, the optical signal transmitted by the first chip 10 can be transmitted to the first transmission waveguide 31 through the first coupling structure 32, and then transmitted to the second chip 20 through the second coupling structure 33, so that the interconnection is realized between the first chip 10 and the second chip 20. Since the first switching optical chip 30 can be mass-produced through a semiconductor process compatible with a CMOS process, the cost is low, and the error is low, and the error accuracy can be controlled within microns, the first switching optical chip 30 is used to realize the interconnection between the first chip 10 and the second chip 20, which can reduce the optical path difference of chip transmission.
[0053] The chip packaging structure provided by the embodiment of the utility model includes a first chip, a second chip and a first switching optical chip, the first chip is coupled with the first coupling structure, the second chip is coupled with the second coupling structure, and the first switching optical chip is used to realize the interconnection between the first chip and the second chip, thereby reducing the optical path difference of chip transmission and improving the transmission effect of the chip. At the same time, the manufacturing cost of the first switching optical chip is low, the error is small, the cost of the chip packaging structure can be reduced, the data transmission capability of the chip is guaranteed, and the computing capability of the chip is improved without increasing the chip size.
[0054] For example, reference Figure 1-Figure 2 , the first coupling structure 32 and the second coupling structure 33 include a grating structure; the first chip 10 overlaps with the first coupling structure 32 in the vertical direction, and the second chip 20 overlaps with the second coupling structure 33 in the vertical direction. When the chip packaging structure is a vertical coupling structure, the first coupling structure 32 overlaps with the first chip 10 in the vertical direction, and the grating structure of the first coupling structure 32 transmits signals to the first chip 10, the second coupling structure 33 overlaps with the second chip 20 in the vertical direction, and the grating structure of the second coupling structure 33 transmits signals to the second chip 20. The chip packaging structure with a vertical coupling structure has low cost, simple manufacturing, and is easy to align and package, thereby ensuring the effect of the chip packaging structure while improving the manufacturing efficiency of the chip packaging structure.
[0055] Figure 3 A schematic front view of the structure of a first chip provided in an embodiment of the utility model; Figure 4 for Figure 3 A schematic diagram of the top view structure of the optical waveguide layer; Figure 5 This is a front view structural diagram of the first second chip provided in an embodiment of the utility model, Figure 6 The schematic diagram of the front view structure of the first switching optical chip provided by the embodiment of the utility model is shown in FIG. Figure 3-Figure 6, the first chip 10 includes a first grating structure 11, and the second chip 20 includes a second grating structure 21; the first grating structure 11 overlaps with the first coupling structure 32 in the vertical direction, and the second grating structure 21 overlaps with the second coupling structure 33 in the vertical direction. The first chip 10 includes a first grating structure 11, a first substrate 12, a first lower cladding layer 13 and a first upper cladding layer 14, and the first grating structure 11 overlaps with the first coupling structure 32 in the vertical direction; the second chip 20 includes a second grating structure 21, a second substrate 22, a second lower cladding layer 23 and a second upper cladding layer 24, and the second grating structure 21 overlaps with the second coupling structure 33 in the vertical direction, which facilitates the transmission of optical signals, improves the chip transmission effect, and reduces the optical path error between chip interconnections.
[0056] Figure 7 A schematic diagram of a top view of a second chip packaging structure provided by an embodiment of the utility model; Figure 8 This is a schematic diagram of the front view of the second chip packaging structure provided by the embodiment of the utility model, referring to Figure 7-Figure 8 , the first coupling structure 32 and the second coupling structure 33 include a pattern spot converter structure; the first chip 10 and the first coupling structure 32 are arranged in the horizontal direction, and the second chip 20 and the second coupling structure 33 are arranged in the horizontal direction. When the chip packaging structure is horizontally coupled, the first coupling structure 32 and the second coupling structure 33 include a pattern spot converter structure. The pattern spot converter can be used to improve the quality and efficiency of signal transmission. It can match the pattern spots of the waveguides on both sides of the coupler to avoid losses caused by mismatching the pattern spots of the waveguides on both sides. The first chip 10 and the pattern spot converter structure of the first coupling structure 32 perform signal transmission. The pattern spot converter structure performs pattern matching between the first transmission waveguide 31 and the first chip 10, improves coupling efficiency, and reduces signal transmission loss. The second chip 20 and the pattern spot converter structure of the second coupling structure 33 perform signal transmission. The pattern spot converter structure performs pattern matching between the first transmission waveguide 31 and the second chip 20, and improves the stability of signal transmission. The chip packaging structure with a horizontal coupling structure is set to improve coupling efficiency, reduce loss, ensure stable signal transmission, and improve the stability of the chip packaging structure.
[0057] Fig. 9 A schematic front view of the structure of a second first chip provided by an embodiment of the utility model; Fig.10 for Fig. 9 A schematic diagram of the top view structure of the optical waveguide layer; Fig.11 A schematic front view of the structure of a second chip provided by an embodiment of the utility model; Fig.12 A schematic diagram of the front view structure of a second switching optical chip provided in an embodiment of the utility model; Fig.13 for Fig.12 Schematic diagram of the top view of the optical waveguide layer, see Figure 9-13The first chip 10 includes a first substrate 12, a first lower cladding layer 13, a first upper cladding layer 14 and a first end face coupling structure 15, and the first end face coupling structure 15 and the first coupling structure 32 are arranged in a horizontal direction. The second chip 20 includes a second substrate 22, a second lower cladding layer 23, a second upper cladding layer 24 and a second end face coupling structure 25, and the second end face coupling structure 25 and the second coupling structure 33 are arranged in a horizontal direction, thereby improving the efficiency of signal transmission and reducing loss.
[0058] Exemplarily, the first adapter optical chip 30 provided in the embodiment of the utility model can perform simplex signal transmission. In other embodiments, the first adapter optical chip 30 can also perform duplex signal transmission. It is suitable for a chip packaging structure in which multiple chips are interconnected, reducing the optical path error between multiple chip channels while improving the versatility of the chip packaging structure.
[0059] Exemplarily, the chip packaging structure further includes a substrate 80. The first chip 10, the second chip 20 and the first transfer optical chip 30 are arranged on the substrate 80; the substrate 80 includes a base plate, a semiconductor cooling plate or a heat sink. The substrate 80 provides support for the chip packaging structure and has the characteristics of good electrical conductivity and good thermal conductivity.
[0060] Fig.14 A schematic diagram of the front view of the third chip packaging structure provided by the embodiment of the utility model, referring to Fig.14 , the first coupling structure 32 includes a pattern spot converter structure, the first chip 10 and the first coupling structure 32 are arranged in the horizontal direction; the second coupling structure 33 includes a grating structure; the second chip 20 and the second coupling structure 33 overlap in the vertical direction. The first switching optical chip 30 has both a pattern spot converter structure and a grating structure coupling structure. The first chip 10 and the first coupling structure 32 are arranged in the horizontal direction. The first chip 10 is mixed with an electrical chip and is not suitable for interconnection with the first coupling structure 32 of the grating structure. Therefore, the first coupling structure 32 of the pattern spot converter structure is set, and the second chip 20 is suitable for the second coupling structure 33 of the grating structure. The second coupling structure 33 of the grating structure is set to ensure that the first chip 10 can be interconnected with the second chip 20 to ensure signal transmission. The first switching optical chip 30 with different coupling structures is suitable for the case where the chip packaging structure area is small or the first chip 10 and the second chip 20 are of different types, so as to ensure that the first chip 10 and the second chip 20 can achieve stable signal transmission in different situations.
[0061] Fig.15 A schematic diagram of a top view of a fourth chip packaging structure provided by an embodiment of the present utility model, referring to Fig.15, the chip packaging structure also includes a third chip 40 and a fourth chip 50, the first chip 10 and the second chip 20 are arranged oppositely, and the third chip 40 and the fourth chip 50 are arranged oppositely; the first chip 10 and the third chip 40 are coupled through the first transfer optical chip 30; the first chip 10 and the fourth chip 50 are coupled through the first transfer optical chip 30. When multiple chips are interconnected, it is necessary to transmit signals from the master chip to the slave chip. The first transfer optical chip 30 is set, and the signal of the first chip 10 can be transmitted to the second chip 20, the third chip 40 and the fourth chip 50 through different transmission paths. The second chip 20, the third chip 40 and the fourth chip 50 can be provided with a grating structure to transmit signals through the first transfer optical chip 30. In other embodiments, the second chip 20, the third chip 40 and the fourth chip 50 can also be provided with an end face coupling structure to transmit signals through the coupling port. As an example, the first chip 10 may be a quantum state generation chip, the second chip 20, the third chip 40 and the fourth chip 50 may be quantum computing chips, the quantum state generation chip generates multi-path quantum entangled states, and sends the quantum entangled states to the quantum computing chip through the first switching optical chip 30.
[0062] Fig.16 A schematic top view of a fifth chip packaging structure provided by an embodiment of the utility model; Fig.17 for Fig.16 Schematic diagram of the three-dimensional structure of the cross-waveguide structure. Figure 16-Figure 17 The first switching optical chip 30 also includes a second transmission waveguide 34, a third coupling structure 35 and a fourth coupling structure 36. The second transmission waveguide 34 is arranged between the third coupling structure 35 and the fourth coupling structure 36. The first transmission waveguide 31 and the second transmission waveguide 34 form a cross waveguide structure 60. The third chip 40 is coupled to the third coupling structure 35, and the fourth chip 50 is coupled to the fourth coupling structure 36. When any interconnection is realized between multiple chips, any two chips have mutually connected optical waveguide channels. The third chip 40 and the fourth chip 50 transmit data through the cross waveguide structure 60, the third coupling structure 35 and the fourth coupling structure 36. When the light or photon passes through the cross waveguide structure 60, it basically does not turn and maintains straight transmission. Therefore, the two perpendicular optical signals will not interfere with each other, ensuring the stability of the signal transmission of the chip packaging structure.
[0063] Fig.18 A schematic diagram of a top view of a sixth chip packaging structure provided by an embodiment of the present invention, referring to Fig.18The chip packaging structure also includes a second transfer optical chip 70; the second transfer optical chip 70 includes a third transmission waveguide 71, a fifth coupling structure 72 and a sixth coupling structure 73, and the fifth coupling structure 72 and the sixth coupling structure 73 include grating structures; the third chip 40 overlaps with the fifth coupling structure 72 in the vertical direction, and the fourth chip 50 overlaps with the sixth coupling structure 73 in the vertical direction. The second transfer optical chip 70 is set, and the third chip 40 and the fourth chip 50 transmit signals through the third transmission waveguide 71, the fifth coupling structure 72 and the sixth coupling structure 73. The first coupling structure 32 and the second coupling structure 33 include a pattern spot converter structure. The first chip 10 and the second chip 20 transmit signals through the first transmission waveguide 31, the first coupling structure 32 and the second coupling structure 33. Two transfer optical chips are set to isolate the signal transmission between the first chip 10 and the second chip 20 from the signal transmission between the third chip 40 and the fourth chip 50, reduce the light deviation caused by the cross waveguide structure 60, and ensure the transmission stability of the chip packaging structure.
[0064] For example, reference Figure 16-18 , the second chip 20 is coupled to the third chip 40 through the first switching optical chip 30; the second chip 20 is coupled to the fourth chip 50 through the first switching optical chip 30. At this time, any interconnection can be achieved between the first chip 10, the second chip 20, the third chip 40 and the fourth chip 50, and signal transmission can be generated between any two chips.
[0065] The above specific implementations do not constitute a limitation on the protection scope of the present utility model. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present utility model shall be included in the protection scope of the present utility model.
Claims
1. A chip packaging structure, characterized in that: include: A first chip, a second chip and a first switching optical chip; The first switching optical chip includes a first transmission waveguide, a first coupling structure and a second coupling structure, wherein the first transmission waveguide is arranged between the first coupling structure and the second coupling structure; The first chip is coupled to the first coupling structure, and the second chip is coupled to the second coupling structure.
2. The chip packaging structure according to claim 1, characterized in that: The first coupling structure and the second coupling structure include grating structures; The first chip overlaps with the first coupling structure in a vertical direction, and the second chip overlaps with the second coupling structure in the vertical direction.
3. The chip packaging structure according to claim 2, characterized in that: The first chip includes a first grating structure, and the second chip includes a second grating structure; The first grating structure overlaps with the first coupling structure in a vertical direction, and the second grating structure overlaps with the second coupling structure in a vertical direction.
4. The chip packaging structure according to claim 1, characterized in that: The first coupling structure and the second coupling structure include pattern spot converter structures; The first chip and the first coupling structure are arranged in a horizontal direction, and the second chip and the second coupling structure are arranged in the horizontal direction.
5. The chip packaging structure according to claim 1, characterized in that: It also includes a substrate; the first chip, the second chip and the first transfer optical chip are arranged on the substrate; The substrate includes a base plate, a semiconductor cooling sheet or a heat sink.
6. The chip packaging structure according to claim 1, characterized in that: The first coupling structure includes a spot converter structure, and the first chip and the first coupling structure are arranged in a horizontal direction; the second coupling structure includes a grating structure; The second chip overlaps with the second coupling structure in a vertical direction.
7. The chip packaging structure according to claim 1, characterized in that: The chip packaging structure further includes a third chip and a fourth chip, the first chip and the second chip are arranged opposite to each other, and the third chip and the fourth chip are arranged opposite to each other; The first chip is coupled to the third chip via the first switching optical chip; The first chip is coupled to the fourth chip via the first switching optical chip.
8. The chip packaging structure according to claim 7, characterized in that: The first switching optical chip also includes a second transmission waveguide, a third coupling structure and a fourth coupling structure, the second transmission waveguide is arranged between the third coupling structure and the fourth coupling structure, and the first transmission waveguide and the second transmission waveguide form a cross-waveguide structure; the third chip is coupled to the third coupling structure, and the fourth chip is coupled to the fourth coupling structure.
9. The chip packaging structure according to claim 7, characterized in that: The chip packaging structure also includes a second transfer optical chip; The second switching optical chip includes a third transmission waveguide, a fifth coupling structure and a sixth coupling structure, The fifth coupling structure and the sixth coupling structure include grating structures; The third chip overlaps with the fifth coupling structure in a vertical direction, and the fourth chip overlaps with the sixth coupling structure in the vertical direction.
10. The chip packaging structure according to claim 8 or 9, characterized in that: The second chip is coupled to the third chip via the first transfer optical chip; The second chip is coupled to the fourth chip through the first switching optical chip.