Copper gate heterojunction battery

Abstract

The utility model discloses a copper gate heterojunction battery, which comprises a silicon wafer, a first thin film layer, a P-type amorphous silicon thin film layer or a P-type microcrystalline silicon thin film layer, a first conducting layer, a first seed layer, a first electro-coppering conducting layer, a second conducting layer and a first electrode, wherein the first thin film layer, the P-type amorphous silicon thin film layer or the P-type microcrystalline silicon thin film layer, the first conducting layer, the first seed layer, the first electro-coppering conducting layer and the second conducting layer are sequentially laminated and plated on one surface of the silicon wafer; the second thin film layer, the N-type amorphous silicon thin film layer or the N-type microcrystalline silicon thin film layer, the third conducting layer, the second seed layer, the second electro-coppering conducting layer and the fourth conducting layer are sequentially laminated, plated and attached to the other face of the silicon wafer, and the second electrode is located on the fourth conducting layer. According to the copper grid heterojunction battery provided by the utility model, the copper electroplating process is adopted, compared with a low-temperature silver paste printing process, the cost and the material consumption are reduced, meanwhile, the conductive layer is additionally plated on the copper electroplating conductive layer, the combining capacity of the conductive layer and the copper grid line formed by the copper electroplating process is enhanced, the grid separation rate of the copper grid line is reduced, and the cost is further reduced.

Description

Technical Field

[0001] The utility model relates to the technical field of photovoltaic cell manufacturing, in particular to a copper grid heterojunction cell. Background Art

[0002] With the accelerated transformation of the global energy structure, renewable energy, especially solar power generation technology, is facing unprecedented development opportunities. Among them, photovoltaic cells are key components for converting solar energy into electrical energy, and their conversion efficiency and cost control have become core issues of concern in the industry. In recent years, heterojunction cell technology (Heterojunction with Intrinsic Thin-layer Solar Cell, HJT) has gradually become one of the important development directions of high-efficiency photovoltaic cells due to its high efficiency, low temperature coefficient and excellent weak light response.

[0003] In the traditional heterojunction battery production process, a low-temperature silver paste printing process is required. However, this process consumes a lot of silver and is costly. Therefore, the silver paste can be replaced by copper grid lines, that is, the low-temperature silver paste printing process can be replaced by the copper electroplating process to reduce costs and consumables. However, the copper electroplating process currently used has poor adhesion between the copper grid lines and the silicon wafers of the heterojunction battery, resulting in a high grid detachment rate and poor cost reduction effect. Utility Model Content

[0004] Therefore, the technical problem to be solved by the present invention is to overcome the problem of poor adhesion between the copper grid line and the silicon wafer of the heterojunction battery in the copper electroplating process in the prior art, resulting in a high grid detachment rate and poor cost reduction effect, thereby providing a copper grid heterojunction battery.

[0005] The utility model provides a copper-grid heterojunction battery, comprising a silicon wafer, a first thin film layer, a P-type amorphous silicon thin film layer or a P-type microcrystalline silicon thin film layer, a first conductive layer, a first seed layer, a first electroplated copper conductive layer, a second conductive layer, and a first electrode located on the second conductive layer, which are sequentially stacked and plated on one side of the silicon wafer, a second thin film layer, an N-type amorphous silicon thin film layer or an N-type microcrystalline silicon thin film layer, a third conductive layer, a second seed layer, a second electroplated copper conductive layer, a fourth conductive layer, and a second electrode located on the fourth conductive layer.

[0006] The utility model improves the capture and conversion efficiency of light energy through the stacked plating structure of the silicon wafer, and adopts the first electroplated copper conductive layer and the second electroplated copper conductive layer as the basis for the electroplating copper process, which reduces the cost and consumables compared with the traditional low-temperature silver paste printing process. At the same time, an additional conductive layer is plated on the first electroplated copper conductive layer and the second electroplated copper conductive layer, which enhances the bonding ability of the conductive layer with the copper grid line formed by the electroplating copper process, reduces the debonding rate of the copper grid line, further reduces the cost, forms a good contact ability, and improves the carrier mobility.

[0007] In an optional embodiment, the first electrode and the second electrode are both copper gates, and both include main gate lines and auxiliary gate lines. The main gate lines are arranged at intervals along the first direction of the silicon wafer, and the auxiliary gate lines are arranged at intervals along the second direction of the silicon wafer. Any main gate line intersects any auxiliary gate line perpendicularly.

[0008] The electrodes of the utility model all use copper grids, which reduces costs and consumables compared to traditional silver paste. In addition, since the resistivity of copper is lower than that of silver, the photoelectric conversion efficiency of the battery can be improved. At the same time, the main grid lines and the auxiliary grid lines intersect vertically to form a grid layout, so that carriers at different positions can be quickly transmitted to the main grid lines through the auxiliary grid lines, thereby reducing the recombination loss of carriers and improving the current collection efficiency.

[0009] In an optional implementation, the first electrode and the second electrode each include 5 main grid lines, the interval between two adjacent main grid lines is 34.6 mm, the width of any main grid line is 35 μm, and any main grid line includes 7 welding strips and welding points.

[0010] The width of the main grid line adopted by the utility model is 35 μm, which is much smaller than the size of the silicon wafer of the heterojunction battery, thereby effectively reducing the shielding of incident light, improving the light absorption rate, and further improving the photoelectric conversion efficiency.

[0011] In an optional implementation, the first electrode and the second electrode each include 47 secondary grid lines, the interval between two adjacent secondary grid lines is 1.94 mm, and the width of any secondary grid line is 18 μm.

[0012] The utility model collects the current generated on the surface of the battery through the secondary grid lines and guides it to the main grid lines. The layout of 47 secondary grid lines can effectively collect current and improve the current collection efficiency. The width of the secondary grid lines is 18μm, which is conducive to improving the light capture efficiency and thus improving the photoelectric conversion efficiency.

[0013] In an optional embodiment, the raw materials of the first seed layer and the second seed layer are both selected from the group consisting of copper, nickel, and copper-nickel alloy, and the thickness range of both is 100 nm-110 nm.

[0014] The utility model determines the raw materials of the seed layer from copper, nickel and copper-nickel alloy to ensure that the seed layer has good conductivity and stability, and sets the seed layer to a thickness of 100nm to 110nm, which will neither increase unnecessary material consumption due to excessive thickness nor affect the conductivity effect due to excessive thinness. At the same time, it can reduce reflection and absorption of light, which is beneficial to improving light absorption efficiency.

[0015] In an optional implementation, the thickness of the first conductive layer and the third conductive layer are both in the range of 70 nm-80 nm, and the thickness of the second conductive layer and the fourth conductive layer are both in the range of 20 nm-30 nm.

[0016] The utility model sets the thickness of the first conductive layer and the third conductive layer so that the first conductive layer and the third conductive layer can provide a greater current carrying capacity and reduce resistance loss, and are plated on the seed layer to provide a good bonding force and conductivity basis for the seed layer, thereby ensuring efficient current transmission. At the same time, the thickness of the second conductive layer and the fourth conductive layer is set so that the bonding ability of the conductive layer with the copper grid line formed by the copper electroplating process can be further enhanced, and the detachment rate of the copper grid line can be reduced, thereby reducing costs.

[0017] In an optional embodiment, the first electroplated copper conductive layer and the second electroplated copper conductive layer are both obtained by horizontal electroplating using an electrochemical deposition method.

[0018] The utility model obtains two electroplated copper conductive layers by horizontal electroplating, and can obtain electroplated copper conductive layers with uniform thickness and smooth surface. The horizontal electroplating adopts electrochemical deposition method, which has high deposition rate and material utilization rate, thereby reducing costs.

[0019] In an optional embodiment, a first protective film is plated between the first electroplated copper conductive layer and the second conductive layer, and the first protective film is removed after the second conductive layer is plated, and a second protective film is plated between the second electroplated copper conductive layer and the fourth conductive layer, and the second protective film is removed after the fourth conductive layer is plated.

[0020] The utility model can effectively prevent the copper grid line obtained by copper electroplating based on the copper electroplating conductive layer from being subjected to physical wear or chemical corrosion in the subsequent process flow by coating a protective film between the copper electroplating conductive layer and the conductive layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the specific implementation methods of the utility model or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings in the following description are some implementation methods of the utility model. For ordinary technicians in this field, the detailed technical solutions of this embodiment can be known based on these drawings without paying any creative work.

[0022] Figure 1 It is a schematic diagram of the structure of a copper-grid heterojunction battery provided by an embodiment of the utility model;

[0023] Figure 2 It is a schematic diagram of the copper grid line provided by the embodiment of the utility model;

[0024] Figure 3 It is a schematic diagram of the process of manufacturing a copper-grid heterojunction battery provided in an embodiment of the utility model.

[0025] Description of Reference Numerals

[0026] 100, silicon wafer; 111, first thin film layer; 121, P-type amorphous silicon thin film layer or P-type microcrystalline silicon thin film layer; 131, first conductive layer; 141, first seed layer; 151, second conductive layer; 161, first electroplated copper conductive layer; 112, second thin film layer; 122, N-type amorphous silicon thin film layer or N-type microcrystalline silicon thin film layer; 132, third conductive layer; 142, second seed layer; 152, fourth conductive layer; 162, second electroplated copper conductive layer. DETAILED DESCRIPTION

[0027] The technical solution of the utility model will be described clearly and completely below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the utility model, not all of the embodiments. Based on the embodiments of the utility model, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the utility model.

[0028] In the description of the present invention, it should be noted that the terms "first", "second" and "third" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance.

[0029] Heterojunction cell technology has gradually become one of the important development directions of high-efficiency photovoltaic cells due to its high efficiency, low temperature coefficient and excellent weak light response. In related technologies, copper grid lines can be used to replace silver paste, that is, the low-temperature silver paste printing process can be replaced by the copper electroplating process to reduce costs and consumables. However, the copper electroplating process currently used has poor adhesion between the copper grid lines and the silicon wafers of heterojunction cells, resulting in a high grid detachment rate and poor cost reduction effect.

[0030] The utility model provides a copper grid heterojunction battery, such as Figure 1 As shown, the present invention comprises a silicon wafer 100, a first thin film layer 111, a P-type amorphous silicon thin film layer or a P-type microcrystalline silicon thin film layer 121, a first conductive layer 131, a first seed layer 141, a first electroplated copper conductive layer 161, a second conductive layer 151, and a first electrode ( Figure 1 ), a second thin film layer 112, an N-type amorphous silicon thin film layer or an N-type microcrystalline silicon thin film layer 122, a third conductive layer 132, a second seed layer 142, a second electroplated copper conductive layer 162, a fourth conductive layer 152, and a second electrode ( Figure 1 not shown).

[0031] Specifically, the utility model is described by taking the structure of any surface of the silicon wafer 100 as an example. The silicon wafer 100 can be an N-type crystalline silicon wafer, with a size of half a 182N-type silicon wafer. The silicon wafer 100 provides the main place for photoelectric conversion, and the selection of N-type silicon with a lower resistivity helps to improve the efficiency of current flow. The first thin film layer 111 is intrinsic amorphous silicon or intrinsic microcrystalline silicon, which helps to improve the transmission of carriers. The first conductive layer 131 and the second conductive layer 151 are both transparent conductive oxide layers (Transparent Conductive Oxide, TCO), and the material used is tin-doped indium oxide, which is used for light transmission and conductivity. The first seed layer 141 serves as the basis of the copper electroplating process. It is pre-plated on the first conductive layer 131 before copper electroplating to improve the adhesion and conductivity of the first copper electroplating conductive layer 161. The first copper electroplating conductive layer 161 includes the electrolyte solution required for the copper electroplating process. The second conductive layer 151 further enhances the bonding ability between the first conductive layer 131 and the second conductive layer 151 and the copper gate line formed by the copper electroplating process, and reduces the gate detachment rate of the copper gate line. The structures of the two sides of the silicon wafer 100 are the same, and the introduction of the structure of the other side can refer to the above content.

[0032] In one embodiment, the first electrode and the second electrode are both copper gates, and both include main gate lines and auxiliary gate lines. The main gate lines are arranged at intervals along the first direction of the silicon wafer 100, and the auxiliary gate lines are arranged at intervals along the second direction of the silicon wafer 100. Any main gate line intersects any auxiliary gate line perpendicularly.

[0033] Specifically, the first direction is a vertical direction, and the second direction is a horizontal direction. Figure 2 Schematic diagram of copper grid line provided by the embodiment of the utility model, such as Figure 2 As shown, Figure 2 , copper grid lines on any side of a copper grid heterojunction cell are shown. Copper is electroplated on a silicon wafer 100 using an electroplating copper process to obtain a plurality of main grid lines and a plurality of secondary grid lines.

[0034] In one embodiment, the first electrode and the second electrode each include 5 main grid lines, the interval between two adjacent main grid lines is 34.6 mm, the width of any main grid line is 35 μm, and any main grid line includes 7 welding strips and welding points.

[0035] Specifically, Figure 2 As shown in the figure, the 5BB (5Bus Bar) grid line method, that is, 5 main grid lines, can more evenly distribute the current collection points, reduce the current transmission distance, and thus reduce the power loss. At the same time, since the width of the main grid line is only 35μm, the shading area on the battery surface is reduced, further improving the photoelectric conversion efficiency.

[0036] In one embodiment, the first electrode and the second electrode each include 47 secondary gate lines, the interval between two adjacent secondary gate lines is 1.94 mm, and the width of any secondary gate line is 18 μm.

[0037] Specifically, Figure 2 As shown, multiple horizontally arranged secondary grid lines are used to collect the current generated on the surface of the battery and guide it to the main grid line. The layout of 47 secondary grid lines can effectively collect current and improve the current collection efficiency. The width of the secondary grid line is 18μm, which is conducive to improving the light capture efficiency and thus improving the photoelectric conversion efficiency.

[0038] In one embodiment, the raw materials of the first seed layer 141 and the second seed layer 142 are both selected from the group consisting of copper, nickel, and copper-nickel alloy, and the thickness of each of the first seed layer 141 and the second seed layer 142 is in the range of 100 nm to 110 nm.

[0039] Specifically, copper, nickel and copper-nickel alloy all have good electrical conductivity and stability, so the first seed layer 141 and the second seed layer 142 made of one of copper, nickel and copper-nickel alloy as raw materials also have the above characteristics. In addition, the thickness of the seed layer is set to a thickness of 100nm to 110nm, which will neither increase unnecessary material consumption due to being too thick nor affect the electrical conductivity due to being too thin, and can reduce the reflection and absorption of light, which is conducive to improving the light absorption efficiency.

[0040] In one embodiment, the thickness of the first conductive layer 131 and the third conductive layer 132 are both in the range of 70 nm-80 nm, and the thickness of the second conductive layer 151 and the fourth conductive layer 152 are both in the range of 20 nm-30 nm.

[0041] Specifically, by setting the thickness of the first conductive layer 131 and the third conductive layer 132, the first conductive layer 131 and the third conductive layer 132 can provide a greater current carrying capacity, reduce resistance loss, and be plated on the seed layer, providing a good bonding force and conductivity basis for the seed layer, ensuring efficient current transmission, and at the same time setting the thickness of the second conductive layer 151 and the fourth conductive layer 152, so that the bonding ability of the conductive layer with the copper grid line formed by the copper electroplating process can be further enhanced, reducing the copper grid line detachment rate, thereby reducing costs.

[0042] In one embodiment, the first electroplated copper conductive layer 161 and the second electroplated copper conductive layer 162 are both obtained by horizontal electroplating using an electrochemical deposition method.

[0043] Specifically, by adopting horizontal electroplating to obtain two electroplated copper conductive layers, an electroplated copper conductive layer with uniform thickness and smooth surface can be obtained, and the horizontal electroplating adopts an electrochemical deposition method, which has a high deposition rate and material utilization rate, thereby reducing costs.

[0044] In one embodiment, a first protective film is plated between the first electroplated copper conductive layer 161 and the second conductive layer 151, and the first protective film is removed after the second conductive layer 151 is plated, and a second protective film is plated between the second electroplated copper conductive layer 162 and the fourth conductive layer 152, and the second protective film is removed after the fourth conductive layer 152 is plated.

[0045] Specifically, the first protective film and the second protective film are both PVC (Polyvinyl Chloride) protective films, which can effectively prevent the copper grid lines obtained by electroplating copper based on the electroplated copper conductive layer from being subjected to physical wear or chemical corrosion in the subsequent process flow.

[0046] In one embodiment, Figure 3 This is a schematic flow chart of a method for manufacturing a copper-grid heterojunction battery provided by an embodiment of the utility model, which can be specifically implemented through the following steps:

[0047] Step S1, initial coating is performed on the silicon wafer 100 of the copper-grid heterojunction battery. A 182N-type half-cut silicon wafer is selected as the raw material for preparing the copper-grid heterojunction battery in the utility model. After the silicon wafer 100 is textured, amorphous silicon or microcrystalline coated, a first thin film layer 111 and a P-type amorphous silicon thin film layer or a P-type microcrystalline silicon thin film layer 121 are coated on one side of the silicon wafer 100, and a second thin film layer 112 and an N-type amorphous silicon thin film layer or an N-type microcrystalline silicon thin film layer 122 are coated on the other side of the silicon wafer 100.

[0048] Step S2, depositing a conductive layer and a seed layer on the silicon wafer 100. The silicon wafer 100 after the initial coating is transported to the PVD (Physical Vapor Deposition Equipment), and under the vacuum conditions of different chambers, the first conductive layer 131 and the first seed layer 141 are continuously deposited on one side of the silicon wafer 100, and the third conductive layer 132 and the second seed layer 142 are continuously deposited on the other side of the silicon wafer 100. It should be noted that the deposition process on both sides of the silicon wafer 100 is carried out simultaneously. During the deposition process, the coating pressure of the PVD equipment is set to 2mT, the deposition power is set to 3kW, and the deposition temperature is set to 170°C.

[0049] Step S3, soft bake, expose and develop the silicon wafer 100. The silicon wafer 100 is transferred to the roller coating machine so that a layer of ink is coated on the seed layer on both sides of the silicon wafer 100. The ink is a photosensitive material composed of resin, monomer, solvent, inorganic filler, photoinitiator and auxiliary agent, thereby forming an ink film. Then, the drying temperature is set to 100℃-120℃, and the drying time is about 10 minutes. The dried silicon wafer 100 is exposed in a dust-free environment, the exposure time is 20s, the light intensity is 1000MJ, and the ambient temperature is 25℃. The exposed silicon wafer 100 is developed with NaCO3·10H2O, the development time is 150s, and after development, it is cleaned and dried at low temperature, and the drying temperature is 80℃.

[0050] Step S4, electroplating the silicon wafer 100 using the copper electroplating process. After the grid line pattern is formed on the ink film layer through mask exposure and development, the silicon wafer 100 is sent to the horizontal electroplating area. The chain transmission adopted by the horizontal electroplating, the roller rotation drives the silicon wafer 100 to move, and the roller on the upper side is a cathode electrode of the electroplating system formed by a conductive material. The silicon wafer 100 maintains continuous contact with the cathode electrode roller during the horizontal transmission process. By means of electrochemical deposition, the copper ions in the electroplating solution are slowly deposited on the exposed first seed layer 141 and the second seed layer 142, so that the exposed area is continuously thickened. By controlling the length of the copper plating tank and the roller transmission speed, the thickness range is controlled to be 20μm-30μm. After the copper layer is plated, as the belt moves into the solution containing tin ions, a thin tin layer is plated on the copper grid line obtained by the copper electroplating, and the thickness is between 1μm-3μm, which is used to protect the surface of the copper grid line and facilitate the welding of the main grid line. By adopting the horizontal electroplating method and matching the ink film layer, the uniformity of the electroplating is improved, and the transmission speed is faster, which improves the production efficiency. In addition, during the electroplating process, the plating solution only needs to cover the silicon wafer 100, thereby reducing the amount of plating solution used and saving costs.

[0051] Step S5, etching the silicon wafer 100. After the copper grid line electroplating is completed, the silicon wafer 100 is washed and dried on a conveyor belt and then subjected to film stripping treatment. The ink film layer is removed by spraying a potassium hydroxide solution, and the spraying time is set to 150s and the temperature is 60°C. After cleaning, the silicon wafer 100 is introduced into the feeding end of the chain etching machine, and moved into the alkaline copper etching solution through the guide rail to etch off the first seed layer 141 and the second seed layer 142 that have not been thickened, and completely expose the copper grid line and the thin tin layer plated on the copper grid line. Among them, the alkaline copper etching solution has good selective corrosion and will not etch the thin tin layer deposited before.

[0052] Step S6, cleaning the silicon wafer 100. After the etching process is completed, the silicon wafer 100 is introduced into the cleaning tank, washed with water and then dried, and the temperature is set to 80°C for 1 minute. Then, a first protective film and a second protective film are respectively plated on the two sides of the silicon wafer 100. Then, after being introduced into the PVD equipment, a second conductive layer 151 and a fourth conductive layer 152 are respectively plated on the two sides of the silicon wafer 100, which enhances the bonding ability between the conductive layer and the copper grid line, reduces the debonding rate of the copper grid line, and forms a good contact ability. Finally, the first protective film and the second protective film are removed, and the silicon wafer 100 is unloaded and packaged.

[0053] The utility model improves the capture and conversion efficiency of light energy through the stacked plating structure of the silicon wafer, and adopts the first electroplated copper conductive layer and the second electroplated copper conductive layer as the basis for the electroplating copper process, which reduces the cost and consumables compared with the traditional low-temperature silver paste printing process. At the same time, an additional conductive layer is plated on the first electroplated copper conductive layer and the second electroplated copper conductive layer, which enhances the bonding ability of the conductive layer with the copper grid line formed by the electroplating copper process, reduces the debonding rate of the copper grid line, further reduces the cost, forms a good contact ability, and improves the carrier mobility.

[0054] Obviously, the above embodiments are merely examples for the purpose of clear explanation, and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived therefrom are still within the scope of protection of the invention of the utility model.

Claims

1. A copper grid heterojunction battery, characterized in that: The invention comprises a silicon wafer, a first thin film layer, a P-type amorphous silicon thin film layer or a P-type microcrystalline silicon thin film layer, a first conductive layer, a first seed layer, a first electroplated copper conductive layer, a second conductive layer, and a first electrode located on the second conductive layer, which are sequentially stacked and plated on one side of the silicon wafer, a second thin film layer, an N-type amorphous silicon thin film layer or an N-type microcrystalline silicon thin film layer, a third conductive layer, a second seed layer, a second electroplated copper conductive layer, a fourth conductive layer, and a second electrode located on the fourth conductive layer, which are sequentially stacked and plated on the other side of the silicon wafer.

2. The copper grid heterojunction battery according to claim 1, characterized in that: The first electrode and the second electrode are both copper grids, and both include main grid lines and auxiliary grid lines. The main grid lines are arranged at intervals along the first direction of the silicon wafer, and the auxiliary grid lines are arranged at intervals along the second direction of the silicon wafer. Any main grid line intersects any auxiliary grid line perpendicularly.

3. The copper grid heterojunction battery according to claim 2, characterized in that: The first electrode and the second electrode each include 5 main grid lines, the interval between two adjacent main grid lines is 34.6 mm, the width of any main grid line is 35 μm, and any main grid line includes 7 welding strips and welding points.

4. The copper grid heterojunction battery according to claim 2, characterized in that: The first electrode and the second electrode each include 47 secondary grid lines, the interval between two adjacent secondary grid lines is 1.94 mm, and the width of any secondary grid line is 18 μm.

5. The copper grid heterojunction battery according to claim 1, characterized in that: The raw materials of the first seed layer and the second seed layer are both one of copper, nickel, and copper-nickel alloy, and the thickness range of both is 100nm-110nm.

6. The copper grid heterojunction battery according to claim 1, characterized in that: The thickness of the first conductive layer and the third conductive layer are both in the range of 70nm-80nm, and the thickness of the second conductive layer and the fourth conductive layer are both in the range of 20nm-30nm.

7. The copper grid heterojunction battery according to claim 1, characterized in that: The first electroplated copper conductive layer and the second electroplated copper conductive layer are both obtained by horizontal electroplating using an electrochemical deposition method.

8. The copper grid heterojunction battery according to claim 1, characterized in that: A first protective film is plated between the first electroplated copper conductive layer and the second conductive layer, and the first protective film is removed after the second conductive layer is plated; a second protective film is plated between the second electroplated copper conductive layer and the fourth conductive layer, and the second protective film is removed after the fourth conductive layer is plated.

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