Counter reading circuit
By designing a counter readout circuit in the image sensor, and using the combination of selector and flip-flop, the problem of high power consumption of counter and readout circuit in the image sensor is solved, thereby reducing power consumption and improving user experience.
Patent Information
- Application Number
- CN202421508934.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-06-27
- Publication Date
- 2025-04-22
- Estimated Expiration
- 2034-06-27
AI Technical Summary
The counters and their readout circuits in the image sensor use high-speed clocks, which cause large power consumption and affect overall performance.
A counter readout circuit is designed, including a first selector and a first flip-flop, through which a data output signal of a counter unit or a lower-level readout circuit is selected, and a data signal is outputted through a flip-flop, and a selector of a higher-level readout circuit is coupled to a trigger.
It effectively reduces the power consumption of the image sensor, improves the user experience, and solves the problem of large power consumption of counters and their readout circuits.
Smart Images
Figure CN222785979U_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of image sensors, and in particular to a counter readout circuit. Background Art
[0002] Image sensors have been widely used in imaging fields such as video, surveillance, industrial manufacturing, automobiles, and home appliances. The counter and its readout circuit in the image sensor are important components of its analog-to-digital circuit, which quantizes the analog quantity into a digital signal and transmits it to the digital processing module for further processing.
[0003] In the process of conceiving and forming this application, the applicant discovered that since the counters in the image sensor use high-speed clocks during counting and reading, their power consumption is relatively high. Optimizing their power consumption is of great significance to improving the overall performance of the image sensor chip. Utility Model Content
[0004] In order to alleviate the above problems, the present application provides a counter readout circuit, which is applied to a counter, wherein the counter includes a plurality of counter units; each of the counter units is connected to a counter readout circuit; the counter readout circuit includes a first selector and a first trigger:
[0005] The first input end of the first selector is connected to the corresponding counter unit, the second input end of the first selector is connected to the data output signal of the lower-level counter readout circuit, and the control end of the first selector receives a first selection signal to select the first input end or the second input end;
[0006] The output end of the first selector is connected to the input end of the first trigger, the output end of the first trigger outputs the data output signal of the counter readout circuit, and the trigger end of the first trigger is coupled to the second input end of the first selector of the higher-level counter readout circuit.
[0007] Optionally, the counter readout circuit also includes a signal trigger unit, which is connected between the trigger end of the first trigger and the second input end of the first selector of the higher-level counter readout circuit, and the signal trigger unit generates a trigger signal of the first trigger of the current-level counter readout circuit based on the first selection signal of the higher-level counter readout circuit.
[0008] Optionally, the signal trigger unit includes a second trigger, the input end of the second trigger is connected to an enable signal, the trigger end of the second trigger is connected to the second input end of the first selector of a higher-level counter readout circuit; the output end of the second trigger is coupled to the trigger end of the first trigger.
[0009] Optionally, the signal trigger unit includes an AND gate, a first input terminal of the AND gate is connected to a clock signal, a second input terminal of the AND gate is connected to an output terminal of the second trigger, and an output terminal of the AND gate is connected to a trigger terminal of the first trigger.
[0010] Optionally, the triggering mode of the first trigger and the second trigger is selected from any one of a rising edge triggering mode, a falling edge triggering mode, a level triggering mode and a pulse triggering mode.
[0011] Optionally, each of the counter units includes a multi-bit storage space; the counter readout circuit further includes a second selector, and a plurality of input terminals of the second selector are respectively connected to a single-bit storage space of a corresponding counter unit;
[0012] The control end of the second selector is connected to a second selection signal to select each bit storage space of the counter unit, and the output end of the second selector is connected to the first input end of the first selector.
[0013] Optionally, the counter readout circuit also includes a load enhancement unit, which is connected between the second input terminal of the first selector and the output terminal of the first trigger of the lower-level counter readout circuit, and / or, the load enhancement unit is connected between the output terminal of the first trigger and the second input terminal of the first selector of the higher-level counter readout circuit.
[0014] Optionally, the load enhancement unit includes a first NOT gate and a second NOT gate connected in series, the input end of the first NOT gate is connected to the data output signal, the output end of the first NOT gate is connected to the input end of the second NOT gate, and the output end of the second NOT gate outputs the processed data output signal.
[0015] The counter readout circuit provided in the present application is connected to a counter readout circuit through each counter unit; the counter readout circuit includes a first selector and a first trigger: the first input end of the first selector is connected to the corresponding counter unit, the second input end of the first selector is connected to the data output signal of the lower-level counter readout circuit, and the control end of the first selector receives a first selection signal to select the first input end or the second input end; the output end of the first selector is connected to the input end of the first trigger, the output end of the first trigger outputs the data output signal of the counter readout circuit, and the trigger end of the first trigger is coupled to the second input end of the first selector of the higher-level counter readout circuit, which can solve the problem of high power consumption of the counter and its readout circuit, effectively reduce the power consumption of the image sensor, and improve user experience. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] The drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present application, and are used together with the specification to explain the principles of the present application. In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the description of the embodiments are briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative labor.
[0017] Figure 1 This is a schematic diagram of the counter structure connection according to an embodiment of the present application.
[0018] Figure 2 FIG. 1 is a connection diagram of a counter readout circuit according to an embodiment of the present application.
[0019] Figure 3 Schematic diagram of the key node timing of the counter readout circuit according to an embodiment of the present application.
[0020] Figure 4 This is a flow chart of a control method according to an embodiment of the present application.
[0021] The realization of the purpose, functional features and advantages of this application will be further described in conjunction with the embodiments and with reference to the accompanying drawings. The above-mentioned drawings have shown clear embodiments of this application, which will be described in more detail later. These drawings and textual descriptions are not intended to limit the scope of the concept of this application in any way, but to illustrate the concept of this application to those skilled in the art by reference to specific embodiments. DETAILED DESCRIPTION
[0022] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.
[0023] It should be noted that, in this article, the terms "include", "comprises" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "includes a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element. In addition, components, features, and elements with the same name in different embodiments of the present application may have the same meaning or different meanings, and their specific meanings need to be determined by their explanation in the specific embodiment or further combined with the context of the specific embodiment.
[0024] It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.
[0025] First embodiment
[0026] The present application provides a counter readout circuit and a control method, wherein the counter readout circuit is applied to a counter. Figure 1 This is a schematic diagram of the counter structure connection according to an embodiment of the present application.
[0027] like Figure 1 As shown, the counter includes multiple counter units counter (numbered 1-n in the figure, where n is a natural number); each counter unit counter is connected to a counter readout circuit readout cell (the numbers corresponding to the counter units counter in the figure are 1-n, where n is a natural number).
[0028] For example, the counter and its readout circuit are important components of the analog-to-digital circuit, which quantizes the analog quantity into a digital signal and transmits it to the digital processing module for further processing. Since both counting and reading use a high-speed clock, their power consumption is relatively large, and optimizing their power consumption is of great significance to chip performance.
[0029] Figure 2 FIG. 1 is a connection diagram of a counter readout circuit according to an embodiment of the present application.
[0030] like Figure 2 As shown, the counter readout circuit readout cell (numbered k, where k is a natural number greater than 0 and less than or equal to n) includes a first selector MUX_1 and a first trigger DFF_1.
[0031] The first input end of the first selector MUX_1 is connected to the corresponding counter unit counter, and the second input end of the first selector MUX_1 is connected to the data output signal (such as k-1) of the lower-level counter readout circuit readout cell Figure 2 The control end of the first selector MUX_1 receives a first selection signal (such as Figure 2 The cell k address in the input module is used to select the first input terminal or the second input terminal.
[0032] The output end of the first selector MUX_1 is connected to the input end of the first flip-flop DFF_1, and the output end of the first flip-flop DFF_1 outputs the data output signal of the counter readout circuit readout cell (eg Figure 2 The trigger end of the first trigger DFF_1 is coupled to the second input end of the first selector MUX_1 of the higher-level counter readout circuit readoutcell (number k+1) to receive its first selection signal (such as Figure 2 cell k+1address).
[0033] Please continue to refer to Figure 1 , exemplarily, the counter and the counter readout circuit are divided into n groups, the data in the counter is transmitted to the corresponding readout cell, and the data of n, n-1, and so on to the data of the first group are read out in sequence through the clock readclk, so that the data in the counter can be completely transmitted.
[0034] Please continue to refer to Figure 2 , the data output signal data to cell k+1 of the readout cell k level is transmitted to the first selector MUX_1 of the higher level cell k+1. Correspondingly, the data output signal received by the first selector MUX_1 of the readout cell k level is the data from cell k-1 signal, so as to realize the connection between all levels. Specifically, taking readout cell k as an example, the x in the box in the figure represents the data obtained by the counter counting, and the value is 0 or 1. Generally, readout cell k has two working modes. The first one is when the cell k address value is 1, it can work on the data in the read group, and then according to the add <n:0>The counter data is selected to the input of DFF_1 in turn and knocked out through readclk. The second is when the cell k address takes the value of 0, it can work in the data transmission mode. The first selector MUX_1 transmits the data of the lower level readout cell k-1 to the input of DFF_1, and knocks it out through the coupling signal clkin_k of the readclk signal and the cell k+1address signal of the higher level readout cell k+1. After signal coupling, before readout cell k reads the data of cell k+1, since its cell k+1address is 0, the enable signal read_en cannot be transmitted backward, and clkin_k is always 0, that is, before reading the data of readout cell k+1, no signal will be transmitted from readout cell k to readout cell 1, so there is no power consumption. When reading the data of readout cell k+1, readout cell k+1address is 1, and read_en is transmitted to the AND gate. At this time, clkin_k is consistent with readclk, thus entering the normal working state.
[0035] During the entire working cycle of this embodiment, since each counter readout circuit unit has no power consumption loss when reading data, the entire system effectively reduces the working power consumption.
[0036] Please continue to refer to Figure 2 Optionally, the counter readout circuit readout cell further includes a signal trigger unit D0, wherein the signal trigger unit D0 is connected between the trigger end of the first trigger DFF_1 and the second input end of the first selector MUX_1 of the higher-level counter readout circuit readout cell (number k+1), and the signal trigger unit D0 is based on the first selection signal (such as Figure 2 The cell k+1address signal) generates a trigger signal (such as Figure 2 clkin_k signal).
[0037] Please continue to refer to Figure 2 Optionally, the signal trigger unit D0 includes a second trigger DFF_2, and the input end of the second trigger DFF_2 is connected to an enable signal (such as Figure 2 The trigger end of the second trigger DFF_2 is connected to the second input end of the first selector MUX_1 of the higher-level counter readout circuit readout cell (number k+1); the output end of the second trigger DFF_2 is coupled to the trigger end of the first trigger DFF_1.
[0038] For example, a trigger is an information storage device with a memory function and two stable states. It is the most basic logic unit that constitutes a variety of sequential circuits and is also an important unit circuit in digital logic circuits. Therefore, triggers are widely used in digital systems and computers. For example, a D trigger has two stable states, namely 0 and 1, and can flip from one stable state to another under the action of certain external signals.
[0039] Please continue to refer to Figure 2 Optionally, the signal trigger unit D0 includes an AND gate Q1, and a first input terminal of the AND gate Q1 is connected to a clock signal (such as Figure 2 The second input terminal of the AND gate Q1 is connected to the output terminal of the second flip-flop DFF_2, and the output terminal of the AND gate Q1 is connected to the trigger terminal of the first flip-flop DFF_1.
[0040] AND gate (English: AND gate) is also called "AND circuit", logical "product", and logical "AND" circuit. It is a basic logic gate circuit that performs "AND" operations. It has multiple input terminals and one output terminal. When all inputs are at a high level (logical 1) at the same time, the output is high, otherwise the output is low (logical 0). AND gate is a circuit that implements logical "multiplication" operations. It has more than two input terminals and one output terminal (general circuits have only one output terminal, and ECL circuits have two output terminals). Only when all input terminals are at a high level (logical "1"), the output of the circuit is high (logical "1"), otherwise the output is low (logical "0"). Exemplarily, when the clock signal and the signal output by the second trigger DFF_2 are both high, the output terminal of the AND gate Q1 will output a high level.
[0041] Please continue to refer to Figure 2 Optionally, the triggering mode of the first trigger DFF_1 and the second trigger DFF_2 is selected from any one of a rising edge triggering mode, a falling edge triggering mode, a level triggering mode and a pulse triggering mode.
[0042] Figure 3 Schematic diagram of the key node timing of the counter readout circuit according to an embodiment of the present application.
[0043] Please refer to Figure 3 , in the clock signal (such as Figure 2 When the counter readout circuit readoutcell needs to work, the enable signal (such as Figure 2 The counter readout circuit sequentially transmits the first selection signal (such as Figure 3 In the readout stage, cell k+2address and cell k+1address are adjusted to a high level. At the rising edge of the first selection signal of the counter readout circuit readout cell (number k+1) of the higher level, the coupling signal (such as Figure 2 inclkin_k).
[0044] It should be noted that, for the sake of system robustness, this embodiment adopts a rising edge triggering method. When the k+1 level counter readout circuit readout cell reads data, the k level counter readout circuit readout cell starts to work, so as to reserve a part of the margin to ensure that there is no data error problem in the first one or two clocks of the k level counter readout circuit readout cell. In another embodiment, based on better robustness considerations, more margin can also be reserved, and the k level counter readout cell starts to work more in advance. In other embodiments, it can also be based on the use of a falling edge triggering method. The k+1 level counter readout circuit readout cell finishes reading before the k level counter readout cell starts, and the system power consumption can be minimized at this time. The appropriate start time can be selected according to the actual system situation requirements, and this application does not limit this.
[0045] For example, assuming that there are n groups of counter units and counter readout circuits, and the power consumption required for a single counter readout circuit to read out the signals of this group is P, then using the technical solution of this embodiment, the power consumption required to read all the data is When the amount of data is large and the value of n is large, the power consumption required to read all the data is P×n compared to the traditional readout solution. 2 The low-power readout module circuit of this embodiment can reduce power consumption by nearly half, with significant results.
[0046] Second embodiment
[0047] Based on the above examples, please continue to refer to Figure 2 Optionally, each counter unit counter includes a multi-bit storage space x; the counter readout circuit readout cell also includes a second selector MUX_2, and multiple input terminals of the second selector MUX_2 are respectively connected to a single-bit storage space x of the corresponding counter unit counter; it can be understood that in this embodiment, a group of readout cells includes 16 counter data, and the corresponding address add <n:0>It can be set to add<3:0> to output the group of data based on the address add<3:0>. In other embodiments, a readout cell includes 8 counter data, and the corresponding address add <n:0>It can be set to add<2:0> to output the group of data based on the address add<2:0>. Therefore, in practical applications, a group of readout cells can be designed to include more or less counter data and output after configuring the corresponding address, which is not limited here.
[0048] The control terminal of the second selector MUX_2 receives the second selection signal (such as Figure 2 medium add <n:0>signal) to select each bit storage space x of the counter unit counter, and the output end of the second selector MUX_2 is connected to the first input end of the first selector MUX_1.
[0049] Exemplarily, the counter addressing is selected by the second selection signal, and the second selector is driven to conduct the corresponding storage space, so that the data of the storage space corresponding to the counter unit is output to the first selector in sequence.
[0050] Please continue to refer to Figure 2 Optionally, the counter readout circuit further includes a load enhancement unit Q0, which is connected between the second input terminal of the first selector MUX_1 and the output terminal of the first trigger DFF_1 of the lower-level counter readout circuit readout cell (numbered k-1), and / or, the load enhancement unit Q0 is connected between the output terminal of the first trigger DFF_1 and the second input terminal of the first selector MUX_1 of the higher-level counter readout circuit readout cell (numbered k+1).
[0051] For example, the signal output by the trigger may have limited power and limited load capacity, so the signal output by the first trigger may be enhanced by the load enhancement unit.
[0052] Please continue to refer to Figure 2 Optionally, the load enhancement unit Q0 includes a first NOT gate Q2 and a second NOT gate Q3 connected in series, the input end of the first NOT gate Q2 is connected to the data output signal, the output end of the first NOT gate Q2 is connected to the input end of the second NOT gate Q3, and the output end of the second NOT gate Q3 outputs the processed data output signal.
[0053] Exemplarily, by performing two non-operation flips on the signal output by the first trigger, the carrying capacity of the data output signal output by the first trigger can be effectively improved, data errors can be avoided during data transmission, and the accuracy of data transmission can be effectively improved.
[0054] Third embodiment
[0055] The present application also provides a control method applied to the counter readout circuit as described above, Figure 4 This is a flow chart of a control method according to an embodiment of the present application.
[0056] like Figure 4 As shown, in one embodiment, the control method includes:
[0057] S10: according to the cascade sequence of multiple counter readout circuits, start the trigger signal of the first trigger of the highest level counter readout circuit, select the first input end of the first selector of the highest level counter readout circuit to read the data of the counter unit corresponding to the counter readout circuit.
[0058] S20: When the reading of the counter unit corresponding to the higher-level counter readout circuit is completed, the second input terminal of the first selector of the higher-level counter readout circuit is selected, and based on the first selection signal of the higher-level counter readout circuit, the trigger signal of the first trigger of the adjacent lower-level counter readout circuit is started, and the first input terminal of the first selector of the lower-level counter readout circuit is selected to read the data of the counter unit corresponding to the lower-level counter readout circuit.
[0059] Please refer to Figure 1-Figure 3 , the data output signal data to cell k+1 of the readout cell k level is transmitted to the first selector MUX_1 of the higher level cell k+1. Correspondingly, the data output signal received by the first selector MUX_1 of the readout cell k level is the data from cell k-1 signal, so as to realize the connection between all levels. Specifically, taking readout cell k as an example, the x in the box in the figure represents the data obtained by the counter count, and the value is 0 or 1. Generally, there are two working modes for readout cell k. The first is when the cell k address value is 1, it can work in the data in the reading group, and then according to the alternating change of add<3:0>, the counter data is sequentially selected to the input end of the DFF, and knocked out through readclk; the second is when the cell k address value is 0, it can work in the data transmission mode, and the first selector MUX_1 transmits the data of the lower level readout cell k-1 to the input end of the DFF, and knocks it out through the readclk signal and the coupling signal clkin_k of the cell k+1address signal of the higher level readout cell k+1. After signal coupling, before readout cell k reads the data of cell k+1, since its cell k+1address is 0, the enable signal read_en cannot be transmitted backward, and clkin_k is always 0, that is, before reading the data of readout cell k+1, no signal is transmitted from readout cell k to readout cell 1, so there is no power consumption. When reading the data of readout cell k+1, readout cell k+1address is 1, read_en is transmitted to the AND gate, and clkin_k is consistent with readclk, thus entering the normal working state.
[0060] During the entire working cycle of this embodiment, since each counter readout circuit unit has no power consumption loss when reading data, the entire system effectively reduces the working power consumption.
[0061] Optionally, in the process of starting the trigger signal of the first trigger of the adjacent lower-level counter readout circuit based on the first selection signal of the higher-level counter readout circuit, the trigger signal of the first trigger of the lower-level counter readout circuit is triggered when the first selection signal of the higher-level counter readout circuit starts.
[0062] Please continue to refer to Figure 1-Figure 3 , in the clock signal (such as Figure 2 When the counter readout circuit readout cell needs to work, the enable signal (such as Figure 2 The counter readout circuit sequentially transmits the first selection signal (such as Figure 3 In the readout stage, cell k+2address and cell k+1address are adjusted to a high level. At the rising edge of the first selection signal of the counter readout circuit readout cell (number k+1) of the higher level, the coupling signal (such as Figure 2 inclkin_k).
[0063] For example, assuming that there are n groups of counter units and counter readout circuits, and the power consumption required for a single counter readout circuit to read out the signals of this group is P, then using the technical solution of this embodiment, the power consumption required to read all the data is When the amount of data is large and the value of n is large, the power consumption required to read all the data is P×n compared to the traditional readout solution. 2 The low-power readout module circuit of this embodiment can reduce power consumption by nearly half, with significant results.
[0064] The counter readout circuit and control method provided by the present application are characterized in that each counter unit is connected to a counter readout circuit; the counter readout circuit includes a first selector and a first trigger: the first input end of the first selector is connected to the corresponding counter unit, the second input end of the first selector is connected to the data output signal of the lower-level counter readout circuit, and the control end of the first selector receives a first selection signal to select the first input end or the second input end; the output end of the first selector is connected to the input end of the first trigger, the output end of the first trigger outputs the data output signal of the counter readout circuit, and the trigger end of the first trigger is coupled to the second input end of the first selector of the higher-level counter readout circuit, which can solve the problem of high power consumption of the counter and its readout circuit, effectively reduce the power consumption of the image sensor, and improve the user experience.
[0065] It should be noted that in the present application, step codes such as S10, S20, etc. are used for the purpose of expressing the corresponding content more clearly and concisely, and do not constitute a substantial limitation on the sequence. When implementing the step, those skilled in the art may execute S20 first and then S10, etc., but these should all be within the scope of protection of the present application.
[0066] In the embodiments of the image sensor and storage medium provided in the present application, all technical features of any of the above-mentioned method embodiments may be included, and the expanded and explained contents of the specification are basically the same as those of the above-mentioned method embodiments, and will not be repeated here.
[0067] The embodiment of the present application further provides a computer program product, which includes a computer program code. When the computer program code runs on a computer, the computer executes the methods in the above various possible implementation modes.
[0068] An embodiment of the present application also provides a chip, including a memory and a processor, the memory is used to store a computer program, and the processor is used to call and run the computer program from the memory, so that a device equipped with the chip executes the methods in various possible implementation modes as described above.
[0069] It is understood that the above scenarios are only examples and do not constitute a limitation on the application scenarios of the technical solutions provided in the embodiments of the present application. The technical solutions of the present application can also be applied to other scenarios. For example, it is known to those skilled in the art that with the evolution of the system architecture and the emergence of new business scenarios, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems.
[0070] The serial numbers of the above-mentioned embodiments of the present application are for description only and do not represent the advantages or disadvantages of the embodiments.
[0071] The steps in the method of the embodiment of the present application can be adjusted in order, combined and deleted according to actual needs.
[0072] The units in the device of the embodiment of the present application can be merged, divided and deleted according to actual needs.
[0073] In the present application, the same or similar terminology concepts, technical solutions and / or application scenario descriptions are generally described in detail only the first time they appear. When they appear again later, they are generally not repeated for the sake of brevity. When understanding the technical solutions and other contents of the present application, for the same or similar terminology concepts, technical solutions and / or application scenario descriptions that are not described in detail later, reference can be made to the previous related detailed descriptions.
[0074] In the present application, the description of each embodiment has its own emphasis. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.
[0075] The various technical features of the technical solution of the present application can be arbitrarily combined. In order to make the description concise, not all possible combinations of the various technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of the present application.
[0076] The above are only preferred embodiments of the present application, and are not intended to limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.
Claims
1. A counter readout circuit, characterized in that: Applied to a counter, the counter comprises a plurality of counter units; each of the counter units is connected to a counter readout circuit; the counter readout circuit comprises a first selector and a first trigger: The first input end of the first selector is connected to the corresponding counter unit, the second input end of the first selector is connected to the data output signal of the lower-level counter readout circuit, and the control end of the first selector receives a first selection signal to select the first input end or the second input end; The output end of the first selector is connected to the input end of the first trigger, the output end of the first trigger outputs the data output signal of the counter readout circuit, and the trigger end of the first trigger is coupled to the second input end of the first selector of the higher-level counter readout circuit.
2. A counter readout circuit according to claim 1, characterized in that: The counter readout circuit also includes a signal trigger unit, which is connected between the trigger end of the first trigger and the second input end of the first selector of the higher-level counter readout circuit. The signal trigger unit generates a trigger signal of the first trigger of the current-level counter readout circuit based on the first selection signal of the higher-level counter readout circuit.
3. A counter readout circuit according to claim 2, characterized in that: The signal trigger unit includes a second trigger, the input end of the second trigger is connected to the enable signal, the trigger end of the second trigger is connected to the second input end of the first selector of the higher-level counter readout circuit; the output end of the second trigger is coupled to the trigger end of the first trigger.
4. A counter readout circuit according to claim 3, characterized in that: The signal trigger unit includes an AND gate, a first input end of the AND gate is connected to a clock signal, a second input end of the AND gate is connected to an output end of the second trigger, and an output end of the AND gate is connected to a trigger end of the first trigger.
5. A counter readout circuit according to claim 3, characterized in that: The triggering mode of the first trigger and the second trigger is selected from any one of a rising edge triggering mode, a falling edge triggering mode, a level triggering mode and a pulse triggering mode.
6. A counter readout circuit according to any one of claims 1 to 5, characterized in that: Each counter unit includes a multi-bit storage space; the counter readout circuit also includes a second selector, and multiple input terminals of the second selector are respectively connected to a single-bit storage space of the corresponding counter unit; The control end of the second selector is connected to a second selection signal to select each bit storage space of the counter unit, and the output end of the second selector is connected to the first input end of the first selector.
7. A counter readout circuit according to any one of claims 1 to 5, characterized in that: The counter readout circuit also includes a load enhancement unit, which is connected between the second input terminal of the first selector and the output terminal of the first trigger of the lower-level counter readout circuit, and / or, the load enhancement unit is connected between the output terminal of the first trigger and the second input terminal of the first selector of the higher-level counter readout circuit.
8. A counter readout circuit according to claim 7, characterized in that: The load enhancement unit includes a first NOT gate and a second NOT gate connected in series, the input end of the first NOT gate is connected to the data output signal, the output end of the first NOT gate is connected to the input end of the second NOT gate, and the output end of the second NOT gate outputs the processed data output signal.