Small-size MOS device

Abstract

The utility model relates to the technical field of MOS semiconductors, and discloses a small-size MOS device which comprises an MOS device formed by a plurality of MOS cells connected in parallel, and each MOS cell comprises a drain electrode, a source electrode, a grid electrode and a semiconductor epitaxial layer. Wherein the semiconductor epitaxial layer comprises a sinking layer, a diffusion layer, a P well layer, an N well layer and a drift layer; the P well layer comprises a low-doped P well layer I and a low-doped P well layer II; the N-well layer comprises a low-doped N-well layer, a high-doped P-well layer I, a high-doped N-well layer I, a high-doped N-well layer II and a high-doped N-well layer III; the drift layer comprises a first drift layer, a second drift layer and a second drift layer. Phosphorus and boron elements with higher concentration are injected into the low-concentration doped semiconductor for step-by-step doping, so that the N well layer, the P well layer and the drift layer are divided into different layers, and the preparation method of ion injection not only improves the carrier accuracy of the MOS device, but also can effectively reduce the volume of the MOS device.

Description

Technical Field

[0001] The utility model relates to the technical field of MOS semiconductors, in particular to a small-size MOS device. Background Art

[0002] MOS power semiconductor devices are power electronic devices manufactured using metal oxide semiconductor technology and are used to control and regulate electrical energy. They are based on the MOS (metal oxide semiconductor) structure and mainly include types such as MOSFET (metal oxide semiconductor field effect transistor) and IGBT (insulated gate bipolar transistor). These devices are widely used in many fields, including power management, motor drives, inverters, vehicle electronics, industrial automation, etc. They have the characteristics of low switching losses, high efficiency, fast response speed and good electrical isolation, making them play an important role in high-performance power conversion systems.

[0003] The existing patent discloses a transistor and a method for forming the same (publication number CN106856169A), wherein the method comprises: providing a substrate, a gate structure is formed on the surface of the substrate; forming a first doping layer in the substrate on both sides of the gate structure; forming a first sidewall on the sidewall of the gate structure; removing the first doping layer on both sides of the first sidewall; forming a second doping layer in the substrate on both sides of the first sidewall, wherein the doping concentration of the second doping layer is higher than the doping concentration of the first doping layer. In the technology disclosed in the patent, it is difficult to accurately divide the N-well layer and the P-well layer into multiple levels when preparing the MOS semiconductor, and the design of dividing the N-well layer and the P-well layer into multiple levels can not only improve the anti-interference ability of the MOS device, but also can achieve accurate control of the load charge size. Summary of the invention

[0004] The main technical problem solved by the utility model is to provide a small-size MOS device, which solves the problems in the above-mentioned background technology.

[0005] To solve the above technical problems, according to one aspect of the utility model, more specifically, a small-size MOS device includes a MOS device composed of a plurality of mutually parallel MOS cells, wherein the MOS cell includes a drain, a source, a gate, and a semiconductor epitaxial layer;

[0006] The semiconductor epitaxial layer includes a sink layer, a diffusion layer, a P-well layer, an N-well layer and a drift layer;

[0007] The P-well layer includes a low-doped P-well layer 1 and a low-doped P-well layer 2;

[0008] The N-well layer includes a low-doped N-well layer, a highly-doped P-well layer 1, a highly-doped N-well layer 1, a highly-doped N-well layer 2, and a highly-doped N-well layer 3;

[0009] The drift layer includes a first drift layer, a second drift layer and a second drift layer.

[0010] Furthermore, a gate oxide layer is deposited between the surface of the gate and the source and the semiconductor epitaxial layer.

[0011] Furthermore, the low-doped P-well layer 1 and the low-doped P-well layer 2 between adjacent MOS cells are integrated as one.

[0012] Furthermore, the N-well layer and the diffusion layer are separated by a common barrier composed of a low-doped P-well layer 1 and a low-doped P-well layer 2.

[0013] Furthermore, the low-doped N-well layer and the highly-doped P-well layer 1 are formed by vertical ion implantation, and the highly-doped N-well layer 1, the highly-doped N-well layer 2 and the highly-doped N-well layer 3 are formed by lateral ion implantation.

[0014] Furthermore, the drift layer is located between two adjacent P-well layers, wherein when the gate is connected to a gate voltage state, a depletion layer of a JFET region is formed inside the drift layer.

[0015] Furthermore, when the gate is connected to a gate voltage, a charge channel is formed in the P-well layer near the gate, and the diffusion layer and the N-well layer are connected through the charge channel.

[0016] The beneficial effects of a small-size MOS device of the utility model are:

[0017] 1. The utility model divides the N-well layer, the P-well layer and the drift layer into different levels by injecting higher concentrations of phosphorus and boron elements into the low-concentration doped semiconductor for step-by-step doping. This ion implantation preparation method not only improves the carrier accuracy of the MOS device, but also can effectively reduce the volume of the MOS device.

[0018] 2. The present invention prepares the drift layer by injecting phosphorus elements with gradually increasing concentrations into the diffusion layer, thereby ensuring that the flow of charges in the diffusion layer is not hindered and also increasing the peak voltage tolerance of the MOS device. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The utility model is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0020] Figure 1 It is a schematic diagram of the structure of a single MOS cell in the utility model.

[0021] Figure 2 It is a structural schematic diagram of the MOS device in the utility model.

[0022] In the figure: 1. drain; 2. source; 3. gate oxide layer; 4. gate; 5. substrate layer; 6. diffusion layer; 7. low-doped P-well layer 1; 8. low-doped P-well layer 2; 9. low-doped N-well layer; 10. high-doped P-well layer 1; 11. high-doped N-well layer 1; 12. high-doped N-well layer 2; 13. high-doped N-well layer 3; 14. drift layer 1; 15. drift layer 2; 16. drift layer 3. DETAILED DESCRIPTION

[0023] The present invention will be described in detail below with reference to the accompanying drawings and in combination with embodiments. It should be noted that the embodiments and features in the embodiments of the present application can be combined with each other without conflict.

[0024] like Figure 1-2 As shown, a small-size MOS device includes a MOS device composed of multiple MOS cells connected in parallel, and the MOS cell includes a drain 1, a source 2, a gate 4, and a semiconductor epitaxial layer. Among them, the semiconductor epitaxial layer includes a sink layer 5, a diffusion layer 6, a P-well layer, an N-well layer, and a drift layer. When the gate 4 is connected to the gate voltage state, a charge channel will be formed inside the P-well layer, and this charge channel will connect the diffusion layer 6 and the N-well layer, so that the source 2 and the drain 1 are in a conductive state.

[0025] The P-well layer includes a low-doped P-well layer 1 7 and a low-doped P-well layer 2 8; the N-well layer includes a low-doped N-well layer 9, a high-doped P-well layer 1 10, a high-doped N-well layer 1 11, a high-doped N-well layer 2 12 and a high-doped N-well layer 3 13; the drift layer includes a drift layer 1 14, a drift layer 2 15 and a drift layer 16 (such as Figure 2 As shown in FIG. 1 , the low-doped N-well layer 9 and the high-doped P-well layer 10 will inhibit the diffusion of charges in the N-well layer into adjacent MOS cells, thereby ensuring the stability of the MOS device in the on state.

[0026] In this embodiment, a gate oxide layer 3 is deposited between the surface of the gate 4 and the source 2 and the semiconductor epitaxial layer. The gate oxide layer 3 can ensure the formation of a gate electric field and isolate charges from entering the gate 4 from the diffusion layer 6 .

[0027] In this embodiment, the low-doped P-well layer 1 7 and the low-doped P-well layer 2 8 between adjacent MOS cells are integrated, and the N-well layer and the diffusion layer 6 are blocked by the low-doped P-well layer 1 7 and the low-doped P-well layer 2 8 (such as Figure 2 As shown), the low-doped P-well layer 1 7 and the low-doped P-well layer 2 8 form a community that wraps the N-well layer, thereby ensuring that when the gate 4 is in a power-off state, its N-well layer and the diffusion layer 6 are in a cut-off state.

[0028] In this embodiment, the low-doped N-well layer 9 and the high-doped P-well layer 10 are formed by vertical ion implantation, and the high-doped N-well layer 11, the high-doped N-well layer 2 12 and the high-doped N-well layer 3 13 are formed by lateral ion implantation. The longitudinally distributed low-doped N-well layer 9 and the high-doped P-well layer 10 can inhibit the diffusion of charges into adjacent MOS cells, while the multi-level laterally distributed high-doped N-well layer 11, the high-doped N-well layer 2 12 and the high-doped N-well layer 3 13 can reduce the excessive intervention of the gate electric field on the N-well layer.

[0029] In this embodiment, the drift layer is located between two adjacent P-well layers, wherein when the gate 4 is connected to the gate voltage state, a depletion layer of the JFET region is formed inside the drift layer, and when the gate 4 is connected to the gate voltage state, a charge channel is formed in the P-well layer near the gate 4, and the diffusion layer 6 is connected to the N-well layer through the charge channel.

[0030] Of course, the above description is not a limitation of the present invention, and the present invention is not limited to the above examples. Changes, modifications, additions or substitutions made by ordinary technicians in this technical field within the essential scope of the present invention also fall within the protection scope of the present invention.

Claims

1. A small-size MOS device, characterized in that: A MOS device is provided which is composed of a plurality of MOS cells connected in parallel with each other, wherein the MOS cell comprises a drain (1), a source (2), a gate (4) and a semiconductor epitaxial layer; The semiconductor epitaxial layer includes a sink layer (5), a diffusion layer (6), a P-well layer, an N-well layer and a drift layer; The P-well layer includes a low-doped P-well layer 1 (7) and a low-doped P-well layer 2 (8); The N-well layer comprises a low-doped N-well layer (9), a highly-doped P-well layer 1 (10), a highly-doped N-well layer 1 (11), a highly-doped N-well layer 2 (12) and a highly-doped N-well layer 3 (13); The drift layer includes a drift layer 1 (14), a drift layer 2 (15) and a drift layer (16).

2. The small-size MOS device according to claim 1, characterized in that: A gate oxide layer (3) is deposited between the surface of the gate (4), the source (2) and the semiconductor epitaxial layer.

3. The small-size MOS device according to claim 1, characterized in that: The low-doped P-well layer 1 (7) and the low-doped P-well layer 2 (8) between adjacent MOS cells are integrated as a whole.

4. The small-size MOS device according to claim 3, characterized in that: The N-well layer and the diffusion layer (6) are separated by a common barrier formed by a low-doped P-well layer 1 (7) and a low-doped P-well layer 2 (8).

5. The small-size MOS device according to claim 1, characterized in that: The low-doped N-well layer (9) and the high-doped P-well layer 1 (10) are formed by vertical ion implantation, and the high-doped N-well layer 1 (11), the high-doped N-well layer 2 (12) and the high-doped N-well layer 3 (13) are formed by lateral ion implantation.

6. The small-size MOS device according to claim 1, characterized in that: The drift layer is located between two adjacent P-well layers, wherein when the gate (4) is connected to a gate voltage state, a depletion layer of a JFET region is formed inside the drift layer.

7. The small-size MOS device according to claim 6, characterized in that: When the gate (4) is connected to a gate voltage, a charge channel is formed in the P-well layer near the gate (4), and the diffusion layer (6) is connected to the N-well layer through the charge channel.

Images