Trench gate super-junction silicon carbide VDMOS integrated with Schottky diode

Abstract

The utility model provides a trench gate super-junction silicon carbide VDMOS integrated with a Schottky diode, which is characterized in that the lower side surface of a drift layer is connected to the upper side surface of a silicon carbide substrate, and a masking layer is arranged on the drift layer; the lower side surface of the super-junction structure layer is connected to the upper side surface of the silicon carbide substrate; the inner side surface of the super-junction structure layer is connected to the outer side surface of the drift layer; the lower side surface of the contact region is connected to the upper side surface of the super-junction structure layer; the lower side surface of the current-sharing layer is connected to the upper side surface of the drift layer. The outer side surface of the current-sharing layer is connected to the inner side surface of the contact region. The lower side of the well region is connected to the upper side of the current-sharing layer; the source region lower side is connected to the well region upper side; the outer side surface of the gate dielectric layer is connected to the inner side surface of the flow equalizing layer, the inner side surface of the well region and the inner side surface of the source region; a groove is formed in the gate dielectric layer; the gate metal layer is arranged in the groove; the source metal layer is connected with the contact region, the current sharing layer, the well region and the source region respectively; the upper side surface of the drain metal layer is connected to the silicon carbide substrate, thereby improving the voltage endurance capability of the device.

Description

Technical Field

[0001] The utility model relates to a trench gate super junction silicon carbide VDMOS with an integrated Schottky diode. Background Art

[0002] Silicon carbide MOSFET is a typical representative of silicon carbide power devices, which is widely used in electric vehicles, aerospace, power conversion and other fields. The device has achieved good characteristics within 1200V and has replaced silicon MOSFET and IGBT within 1200V. However, as the withstand voltage is further increased, it is becoming increasingly difficult for the device to maintain high operating frequency and low on-resistance. Utility Model Content

[0003] The technical problem to be solved by the utility model is to provide a trench gate super junction silicon carbide VDMOS with an integrated Schottky diode to improve the voltage resistance of the device.

[0004] The utility model is implemented as follows: a trench gate super junction silicon carbide VDMOS with integrated Schottky diode, comprising:

[0005] Silicon carbide substrate,

[0006] A drift layer, wherein the lower side of the drift layer is connected to the upper side of the silicon carbide substrate, and a masking layer is disposed on the drift layer;

[0007] A super junction structure layer, wherein the lower side of the super junction structure layer is connected to the upper side of the silicon carbide substrate, and the inner side of the super junction structure layer is connected to the outer side of the drift layer;

[0008] A contact region, wherein a lower side of the contact region is connected to an upper side of the super junction structure layer;

[0009] A current balancing layer, wherein the lower side of the current balancing layer is connected to the upper side of the drift layer, and the outer side of the current balancing layer is connected to the inner side of the contact area;

[0010] A well region, wherein the lower side of the well region is connected to the upper side of the current balancing layer;

[0011] A source region, wherein a lower side of the source region is connected to an upper side of the well region;

[0012] A gate dielectric layer, wherein the lower side of the gate dielectric layer is connected to the masking layer, and the outer side of the gate dielectric layer is connected to the inner side of the current balancing layer, the inner side of the well region, and the inner side of the source region; a groove is provided in the gate dielectric layer;

[0013] A gate metal layer, wherein the gate metal layer is disposed in the groove;

[0014] A source metal layer, the source metal layer is respectively connected to the contact area, the current balancing layer, the well area and the source area;

[0015] and a drain metal layer, wherein an upper side of the drain metal layer is connected to the silicon carbide substrate.

[0016] Furthermore, the silicon carbide substrate, drift layer, current balancing layer and source region are all N-type; and the super junction structure layer, masking layer, contact region and well region are all P-type.

[0017] Furthermore, the thickness of the current balancing layer is equal to the thickness of the contact area.

[0018] Furthermore, the thickness of the masking layer is 300 nm.

[0019] Furthermore, the bottom thickness of the gate dielectric layer is 400 nm, and the side wall thickness is 100 nm.

[0020] The advantages of the utility model are:

[0021] 1. The device adopts a vertical super junction structure, which has the characteristics of high withstand voltage and low on-resistance;

[0022] Second, the masking layer of the device can suppress the breakdown phenomenon caused by the concentrated electric field at the corner of the trench gate and improve the gate reliability;

[0023] 3. The pn junction formed by the drift layer and super junction structure layer of the device changes the device's completely longitudinal voltage-resistant structure into a longitudinal and transverse voltage-resistant structure, effectively improving the device's voltage-resistant capability without changing other characteristics;

[0024] 4. The source metal layer of the device is in direct contact with the current-balancing layer to form a Schottky junction, which reduces the body diode conduction voltage drop of the device, reduces the reverse recovery time of the device, and reduces the loss;

[0025] 5. The current-balancing layer of the device can evenly distribute the current from the source metal layer to the bottom of the source region when the device is not turned on and needs to be continuously flowing, thus avoiding current concentration and reducing device resistance.

[0026] 6. The current-sharing layer of the device can evenly distribute the current from the source area to the left and right sides when the device is turned on, avoiding current concentration and reducing device resistance;

[0027] 7. The contact area of ​​the device can form an ohmic contact with the source metal layer, reduce the resistance between the source metal layer and the super junction structure, and improve the process reliability of the super junction structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The present invention will be further described below in conjunction with the embodiments with reference to the accompanying drawings.

[0029] Figure 1The utility model is a schematic diagram of a trench gate super junction silicon carbide VDMOS with an integrated Schottky diode.

[0030] Figure 2 The utility model is a flow chart of a method for preparing a trench gate super junction silicon carbide VDMOS with an integrated Schottky diode.

[0031] Figure 3 This is a cross-sectional view of the process of manufacturing a trench gate superjunction silicon carbide VDMOS with an integrated Schottky diode according to the utility model. Figure 1 .

[0032] Figure 4 This is a cross-sectional view of the process of manufacturing a trench gate superjunction silicon carbide VDMOS with an integrated Schottky diode. Figure 2 .

[0033] Figure 5 This is a cross-sectional view of the process of manufacturing a trench gate superjunction silicon carbide VDMOS with an integrated Schottky diode. Figure 3 .

[0034] Figure 6 This is a cross-sectional view of the process of manufacturing a trench gate superjunction silicon carbide VDMOS with an integrated Schottky diode according to the utility model. Figure 4 .

[0035] Figure 7 This is a cross-sectional view of the process of manufacturing a trench gate superjunction silicon carbide VDMOS with an integrated Schottky diode. Figure 5 .

[0036] Figure 8 This is a cross-sectional view of the process of manufacturing a trench gate superjunction silicon carbide VDMOS with an integrated Schottky diode according to the utility model. Figure 6 .

[0037] Fig. 9 This is a cross-sectional view of the process of manufacturing a trench gate superjunction silicon carbide VDMOS with an integrated Schottky diode. Figure 7 .

[0038] Fig.10 This is a cross-sectional view of the process of manufacturing a trench gate superjunction silicon carbide VDMOS with an integrated Schottky diode according to the utility model. Figure 8 .

[0039] Fig.11 This is a cross-sectional view of the process of manufacturing a trench gate superjunction silicon carbide VDMOS with an integrated Schottky diode. Figure 9 .

[0040] Fig.12 This is a cross-sectional view of the process of manufacturing a trench gate superjunction silicon carbide VDMOS with an integrated Schottky diode according to the utility model. Figure 10 .

[0041] Fig.13 This is a cross-sectional view of the process of manufacturing a trench gate superjunction silicon carbide VDMOS with an integrated Schottky diode according to the utility model. Figure 10 one.

[0042] Fig.14 This is a cross-sectional view of the process of manufacturing a trench gate superjunction silicon carbide VDMOS with an integrated Schottky diode according to the utility model. Figure 10 two.

[0043] Fig.15 This is a cross-sectional view of the process of manufacturing a trench gate superjunction silicon carbide VDMOS with an integrated Schottky diode according to the utility model. Figure 10 three.

[0044] Fig.16 This is a cross-sectional view of the process of manufacturing a trench gate superjunction silicon carbide VDMOS with an integrated Schottky diode according to the utility model. Figure 10 Four. DETAILED DESCRIPTION

[0045] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0046] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0047] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "in contact with ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or part discussed below can be represented as a second element, component, region, layer or part.

[0048] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of one element or feature described in the figures to other elements or features. It should be understood that, in addition to the orientations described in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0049] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0050] like Figure 1 As shown, the embodiment of the present application provides a trench gate super junction silicon carbide VDMOS with an integrated Schottky diode, including:

[0051] Silicon carbide substrate 101,

[0052] A drift layer 102, wherein the lower side of the drift layer 102 is connected to the upper side of the silicon carbide substrate 101, and a masking layer 1021 is disposed on the drift layer 102;

[0053] A super junction structure layer 103, wherein the lower side of the super junction structure layer 103 is connected to the upper side of the silicon carbide substrate 101, and the inner side of the super junction structure layer 103 is connected to the outer side of the drift layer 102;

[0054] A contact region 104, wherein a lower side of the contact region 104 is connected to an upper side of the super junction structure layer 103;

[0055] A current balancing layer 105 , wherein the lower side of the current balancing layer 105 is connected to the upper side of the drift layer 102 , and the outer side of the current balancing layer 105 is connected to the inner side of the contact region 104 ;

[0056] A well region 106, wherein the lower side of the well region 106 is connected to the upper side of the current balancing layer 105;

[0057] A source region 107, wherein a lower side of the source region 107 is connected to an upper side of the well region 106;

[0058] A gate dielectric layer 108, wherein the lower side of the gate dielectric layer 108 is connected to the masking layer 1021, and the outer side of the gate dielectric layer 108 is connected to the inner side of the current balancing layer 105, the inner side of the well region 106, and the inner side of the source region 107; a groove 1081 is provided in the gate dielectric layer 108;

[0059] A gate metal layer 109, wherein the gate metal layer 109 is disposed in the groove 1081;

[0060] A source metal layer 110, wherein the source metal layer 110 is respectively connected to the contact region 104, the current balancing layer 105, the well region 106 and the source region 107;

[0061] and a drain metal layer 111 , wherein the upper side of the drain metal layer 111 is connected to the lower side of the silicon carbide substrate 101 .

[0062] like Figures 2 to 16 As shown, the method for preparing the above device comprises the following steps:

[0063] Step 1: depositing metal on the lower side of the silicon carbide substrate 101 to form a drain metal layer 111; epitaxially growing on the side of the silicon carbide substrate 101 to form a drift layer 102;

[0064] Step 2: forming a barrier layer a on the drift layer 102, etching the barrier layer a to form a through hole, and performing ion implantation on the drift layer 102 to form a super junction structure layer 103, wherein the ion implantation energy is 600-7000 to 10000 kev and the thickness is 20-30 microns;

[0065] Step 3: remove the original barrier layer a, re-form the barrier layer a, etch the barrier layer a to form a through hole, perform ion implantation on the drift layer 102 to form a masking layer 1021 with a thickness of 300 μm and an ion implantation energy of 600-700 kev;

[0066] Step 4: remove the original barrier layer a, re-form the barrier layer a, etch the barrier layer a to form a through hole, perform ion implantation on the drift layer 102 to form a current balancing layer 105 with a thickness of 300 nm and an ion implantation energy of 500-600 kev;

[0067] Step 5, remove the original barrier layer a, re-form the barrier layer a, etch the barrier layer a to form a through hole, and use ion implantation to form a contact area 104 with a thickness of 300 nm and an ion implantation energy of 500-600 kev;

[0068] Step 6: remove the original barrier layer a, re-form the barrier layer a, etch the barrier layer a to form a through hole, perform ion implantation on the drift layer 102 to form a well region 106 with a thickness of 300 nm and an ion implantation energy of 400-500 kev;

[0069] Step 7, remove the original barrier layer a, re-form the barrier layer a, etch the barrier layer a to form a through hole, perform ion implantation on the drift layer 102 to form a source region 107 with a thickness of 1 μm and an ion implantation energy of 70-400 kev;

[0070] Step 8, remove the original barrier layer a, re-form the barrier layer a, etch the barrier layer a, the drift layer 102, the well region 106 and the current-distributing layer 105 to form a through hole, and then perform dry oxygen oxidation to form a gate dielectric layer 108, the bottom of the gate dielectric layer 108 is connected to the masking layer 1021, and a groove 1081 is provided in the gate dielectric layer 108; the etching barrier layer a, the drift layer 102, the well region 106 and the current-distributing layer 105 can be etched by wet chemical solution, the chemical solution is a mixture of sulfuric acid and hydrogen peroxide, first configure the ratio of sulfuric acid and water to form a sulfuric acid solution, the ratio is 1:2; then configure the concentration of hydrogen peroxide, the concentration of hydrogen peroxide is 45%, and finally the sulfuric acid solution and hydrogen peroxide are mixed to form a chemical solution, the ratio of sulfuric acid solution to hydrogen peroxide is 3:2; dry etching or plasma etching can also be used;

[0071] Step 9, removing the original barrier layer a, re-forming the barrier layer a, etching the barrier layer a to form a through hole, depositing metal in the trench 1081, and forming a gate metal layer 109;

[0072] Step 10, remove the original barrier layer a, re-form the barrier layer a, etch the barrier layer a to form a through hole, and etch the drift layer 102 to the top of the contact area 104, the etching depth is 1.5 μm, and perform metal deposition to form a first source metal area 1101;

[0073] Step 11, remove the original barrier layer a, re-form the barrier layer a, etch the barrier layer a to form a through hole, and etch the drift layer 102 to the top of the source area 107, the etching depth is 200nm, and metal deposition is performed to form a second source metal area 1102. The source metal layer 110 includes a first source metal area 1101 and a second source metal area 1102. Remove the barrier layer a and complete the preparation.

[0074] The silicon carbide substrate 101, the drift layer 102, the current balancing layer 105 and the source region 107 are all N-type; the super junction structure layer 103, the masking layer 1021, the contact region 104 and the well region 106 are all P-type, and the doping concentration of the silicon carbide substrate 101 is 5e18cm -3 The doping concentration of the drift layer 102 is 6e16cm -3 The doping concentration of the current balancing layer 105 is 6e17cm -3 The doping concentration of the masking layer 1021 is 1e18cm -3 The doping concentration of the super junction structure layer 103 is 5e17cm -3 The doping concentration of the contact region 104 is 5e18cm -3 The doping concentration of the well region 106 is 5e17 cm -3 The doping concentration of the source region 107 is 8e18cm -3 .

[0075] The source metal layer 110 and the n+ current-balancing layer 105 form a Schottky contact to form a Schottky diode. The n-type drift layer 102 and the p-type super junction structure layer 103 form a super junction to improve the withstand voltage of the device. The p+ contact region 1021 is to form a good contact between the source metal layer 110 and the p-type super junction structure layer 103 to improve the process reliability of the device. The source metal layer 110 and the n+ source region 107 form an ohmic contact and form a main conductive channel that can be controlled by the gate with the p-type well region 106.

[0076] The doping concentration of the n-type silicon carbide substrate 101 is to ensure the formation of a low-resistance ohmic contact with the drain metal layer 111, thereby reducing the overall on-resistance of the device; the doping concentration of the drift layer 102 is a compromise between the on-resistance of the device and the withstand voltage of the super junction structure layer 103; the doping concentration of the current-balancing layer 105 is to form a Schottky contact with the source metal layer 110, construct a Schottky diode, reduce the reverse recovery time of the device, reduce losses, and relatively evenly redistribute the current from the source region 107 when the device is normally turned on and the Schottky junction formed by the source metal layer 110 and the device body diode when the device is freewheeling to the inside of the drift layer 102, thereby avoiding the occurrence of excessive electric field density caused by current concentration. Burning phenomenon and reducing device on-resistance; the doping concentration of the masking layer 1021 is a compromise between the electric field concentration suppression effect at the gate corner and its thickness; the doping concentration of the source region 107 is to form an ohmic contact with the source metal layer and reduce the contact resistance; the function of the super junction structure layer 103 is to form a super junction structure with the drift layer 102, and change the device structure of pure longitudinal withstand voltage to a lateral and longitudinal withstand voltage, and improve the withstand voltage of the device without reducing other parameters of the device. The contact area 104 of the device can form an ohmic contact with the source metal layer 110, reduce the resistance between the source metal layer 110 and the p-type super junction structure layer 103, and improve the process reliability of the super junction structure;

[0077] The thickness of the silicon carbide substrate 101 of the device is 1 μm, the thickness of the drift layer 102 is 20-30 μm, the thickness of the current balancing layer 105 is 300 nm, the thickness of the contact area 104 is 300 nm, the current balancing layer 105 and the top and bottom of the contact area 104 are flush, the thickness of the p-type well region is 300 nm, the thickness of the p-type masking layer is 300 nm, and the thickness of the n+ source region is 1 μm; the bottom thickness of the gate dielectric layer 108 is 400 nm, and the side wall thickness is 100 nm; the thickness from the top of the source metal layer 110 to the top of the source area 107 is 200 nm, the thickness from the top of the source metal layer 110 to the current balancing layer 105 is 1500 nm, and the width of the source metal layer 110 and the contact area 104 is 200 nm. m, the contact width between the source metal layer 110 and the current equalizing region 105 is 100nm, the device withstand voltage is 1200-3000V, the doping concentration and thickness of the well region 106 are designed to increase the gate control ability of the device to the p-type well region while taking into account the on-resistance of the device's longitudinal structure, the doping concentration and position size of the n+ current equalizing layer are designed to control the device to reduce the on-resistance of the device and suppress the negative effect of the p-type shielding layer protecting the gate, the position relationship of the n+ current equalizing layer in the p+ contact area is to ensure the consistency of the source metal layer, avoid the problem of uneven current distribution due to the inconsistency of the bottom depth of the source metal layer, and consider the comprehensive gate control ability and the reliability of the gate bottom when calculating the gate dielectric thickness;

[0078] The voltage resistance of the device is improved through the super junction structure, the p+ contact area improves the process reliability of the contact between the source metal layer and the p-type super junction structure, and the n+ current equalizing layer not only constructs a parasitic Schottky diode and reduces the loss of the device, but also realizes the current equalizing function.

[0079] When the device is turned off, the device drain is subjected to high voltage, and the device drain voltage extends to the drift layer 102. Since the super junction structure layer 103 contacts the drift layer 102 from the silicon carbide substrate 101, the potential is borne by the pn junction between the super junction structure layer 103 and the drift layer 102 from bottom to top, and the longitudinal withstand voltage structure is transformed into a longitudinal and lateral combination to achieve super junction capability. When the device gate is turned on by a positive voltage, the p-type well region 106 is inverted to n-type, forming a conductive channel of source metal layer 110-n+ source region 107-p-type well region 106 close to the gate-n-type drift layer 102-n-type silicon carbide substrate 101-drain metal layer 111. When the device is not turned on, but the source voltage of the device is higher than the drain voltage, the source metal layer 111 forms a Schottky contact with the n+ current equalizing layer 105 to form a Schottky diode. The source metal layer 110 also forms an ohmic contact with the p+ contact area 104. The p-type super junction structure layer 103 extends to form a pn junction with the n-type silicon carbide substrate 101. When the freewheeling current is small, the Schottky diode conduction voltage drop is small to complete the freewheeling. When the current increases, the Schottky junction voltage drop increases. When it is equivalent to the pn junction voltage drop, the Schottky diode and the pn junction diode jointly freewheel.

[0080] Although the specific implementation methods of the present invention are described above, those skilled in the art should understand that the specific embodiments described are only illustrative and are not intended to limit the scope of the present invention. Equivalent modifications and changes made by those skilled in the art in accordance with the spirit of the present invention should be included in the scope of protection of the claims of the present invention.

Claims

1. A trench gate super junction silicon carbide VDMOS with integrated Schottky diode, characterized in that: include: Silicon carbide substrate, A drift layer, wherein the lower side of the drift layer is connected to the upper side of the silicon carbide substrate, and a masking layer is disposed on the drift layer; A super junction structure layer, wherein the lower side of the super junction structure layer is connected to the upper side of the silicon carbide substrate, and the inner side of the super junction structure layer is connected to the outer side of the drift layer; A contact region, wherein a lower side of the contact region is connected to an upper side of the super junction structure layer; A current balancing layer, wherein the lower side of the current balancing layer is connected to the upper side of the drift layer, and the outer side of the current balancing layer is connected to the inner side of the contact area; A well region, wherein the lower side of the well region is connected to the upper side of the current balancing layer; A source region, wherein a lower side of the source region is connected to an upper side of the well region; A gate dielectric layer, wherein the lower side of the gate dielectric layer is connected to the masking layer, and the outer side of the gate dielectric layer is connected to the inner side of the current balancing layer, the inner side of the well region, and the inner side of the source region; a groove is provided in the gate dielectric layer; A gate metal layer, wherein the gate metal layer is disposed in the groove; A source metal layer, the source metal layer is respectively connected to the contact area, the current balancing layer, the well area and the source area; and a drain metal layer, wherein an upper side of the drain metal layer is connected to the silicon carbide substrate.

2. A trench gate super junction silicon carbide VDMOS with integrated Schottky diode as claimed in claim 1, characterized in that: The silicon carbide substrate, drift layer, current balancing layer and source region are all N-type; the super junction structure layer, masking layer, contact region and well region are all P-type.

3. The trench gate super junction silicon carbide VDMOS with integrated Schottky diode according to claim 1, characterized in that: The thickness of the current balancing layer is equal to the thickness of the contact area.

4. The trench gate super junction silicon carbide VDMOS with integrated Schottky diode according to claim 1, characterized in that: The thickness of the masking layer is 300 nm.

5. The trench gate super junction silicon carbide VDMOS with integrated Schottky diode according to claim 1, characterized in that: The bottom thickness of the gate dielectric layer is 400 nm, and the side wall thickness is 100 nm.

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