Chip and chip debugging system based on chip particle architecture
By introducing a debugging and conversion module into a chip based on the core-particle architecture, the problem of the inability to synchronously debug CPUs in the existing technology is solved, and efficient processor debugging and cost reduction are achieved.
Patent Information
- Application Number
- CN202421686207.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-07-16
- Publication Date
- 2025-04-25
- Estimated Expiration
- 2034-07-16
AI Technical Summary
In the prior art, chips based on core-granular architecture lack a unified hardware debugging system, resulting in the inability to synchronously debug CPUs of different architectures.
A chip based on a core-particle architecture is designed, including a debug conversion module and a processor of at least two architectures. The debugging and conversion module includes a computer debugging interface, a debugging interface management unit and a hardware state management unit. These components realize the conversion and transmission of processor status control instructions and debugging data, ensuring that processors of different architectures can be debugged simultaneously.
Synchronous debugging of processors in different architectures is realized, processor debugging efficiency is improved, and the number of debugging interfaces of the host computer is reduced, and hardware costs are reduced.
Smart Images
Figure CN222801145U_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of core-grain chip technology, and in particular to a chip and a chip debugging system based on a core-grain architecture. Background Art
[0002] In the related art, chips based on the core-grain architecture can integrate different architectures and an indefinite number of central processing units (CPUs). However, each processor has an independent hardware debugging system, and there is no unified hardware debugging system covering all CPUs on the core-grain architecture chip. Therefore, there is a problem that CPUs of different architectures on the core-grain architecture chip cannot be debugged synchronously. Utility Model Content
[0003] The embodiment of the present application provides a chip and a chip debugging system based on a core particle architecture, and the technical solution is as follows:
[0004] In a first aspect, an embodiment of the present application provides a chip based on a core grain architecture, the chip comprising a debugging conversion module and processors of at least two architectures, the debugging conversion module comprising a host computer debugging interface, a debugging interface management unit, and a hardware status management unit, the host computer debugging interface is connected to the debugging interface management unit, the host computer debugging interface is connected to the hardware status management unit, the debugging interface management unit is connected to the hardware status management unit, and the processors of each architecture are respectively connected to the debugging interface management unit, wherein:
[0005] The host computer debugging interface receives a processor state control instruction sent by the host computer, the processor state control instruction is transmitted to the hardware state management unit via the host computer debugging interface, the processor state control instruction is transmitted to the debugging interface management unit via the hardware state management unit, and the processor state control instruction is transmitted to the processor via the debugging interface management unit;
[0006] The host computer debugging interface receives processor debugging data sent by the host computer, and the processor debugging data is transmitted to the debugging interface management unit via the host computer debugging interface. The processor debugging data is converted into target debugging data corresponding to the processor via the debugging interface management unit, and the target debugging data is transmitted to the processor via the debugging interface management unit.
[0007] In combination with the first aspect, in some possible implementations, the processor includes a processor debugging interface, and the processor debugging interface is connected to the debugging interface management unit;
[0008] The processor debugging data is converted into target debugging data corresponding to the processor debugging interface by the debugging interface management unit, and the target debugging data is transmitted to the processor debugging interface by the debugging interface management unit, and the target debugging data is used to debug the processor.
[0009] In combination with the first aspect and the above-mentioned embodiments, in some possible embodiments, the processor debugging interface transmits the debugging response data corresponding to the processor to the debugging interface management unit, the debugging response data is converted into target debugging response data corresponding to the host computer debugging interface by the debugging interface management unit, the target debugging response data is transmitted to the host computer debugging interface via the debugging interface management unit, and the target debugging response data is transmitted to the host computer via the host computer debugging interface.
[0010] In combination with the first aspect and the above-mentioned embodiments, in some possible embodiments, the processor state control instruction is converted into a target processor state control instruction corresponding to the processor debug interface by the debug interface management unit, and the target processor state control instruction is transmitted to the processor debug interface via the debug interface management unit, and the target processor state control instruction is used to trigger the processor to enter a debug state or exit a debug state.
[0011] In combination with the first aspect, in some possible implementations, the processor includes a first processor of a first architecture and a second processor of a second architecture, the first processor includes a first processor debug interface, the second processor includes a second processor debug interface, the first processor debug interface is connected to the debug interface management unit, and the second processor debug interface is connected to the debug interface management unit;
[0012] The processor state control instruction is converted by the debug interface management unit into a first processor state control instruction corresponding to the first processor debug interface, the first processor state control instruction is transmitted to the first processor debug interface by the debug interface management unit, and the first processor state control instruction is used to trigger the first processor to enter a debug state or exit a debug state;
[0013] The first processor debugging interface transmits first debugging status data corresponding to the first processor to the debugging interface management unit, and the first debugging status data is transmitted to the hardware status management unit via the debugging interface management unit;
[0014] The hardware state management unit transmits the second processor state control instruction to the debugging interface management unit, the second processor state control instruction is converted by the debugging interface management unit into a third processor state control instruction corresponding to the second processor debugging interface, the third processor state control instruction is transmitted to the second processor debugging interface by the debugging interface management unit, and the third processor state control instruction is used to trigger the second processor to enter a debugging state or exit a debugging state.
[0015] In combination with the first aspect and the above-mentioned implementation manner, in some possible implementation manners, the hardware status management unit includes a first communication interface and a second communication interface, the first communication interface is connected to the host computer debugging interface, and the second communication interface is connected to the debugging interface management unit;
[0016] The processor state control instruction is transmitted to the first communication interface via the host computer debugging interface, and the processor state control instruction is transmitted to the debugging interface management unit via the second communication interface.
[0017] In combination with the first aspect and the above-mentioned implementation manner, in some possible implementation manners, the debugging interface management unit includes a first debugging interface, a second debugging interface, and at least two third debugging interfaces, the first debugging interface is connected to the host computer debugging interface, the second debugging interface is connected to the hardware state management unit, and the third debugging interface is connected to the processor of each architecture respectively;
[0018] The processor state control instruction is transmitted to the second debugging interface via the hardware state management unit, and the processor state control instruction is transmitted to the processor via the third debugging interface;
[0019] The processor debugging data is transmitted to the first debugging interface via the host computer debugging interface, the processor debugging data is converted into target debugging data corresponding to the processor via the debugging interface management unit, and the target debugging data is transmitted to the processor via the third debugging interface.
[0020] In combination with the first aspect, in some possible implementations, the debugging conversion module further includes a hardware information storage unit, and the hardware information storage unit is connected to the host computer debugging interface; wherein,
[0021] The host computer debugging interface receives a processor information acquisition instruction sent by the host computer, and the processor information acquisition instruction is transmitted to the hardware information storage unit via the host computer debugging interface. The hardware information storage unit sends processor information to the host computer debugging interface, and the hardware information storage unit transmits it to the host computer via the host computer debugging interface.
[0022] In combination with the first aspect and the above-mentioned embodiments, in some possible implementations, the hardware information storage unit includes a third communication interface, and the third communication interface is connected to the host computer debugging interface;
[0023] The processor information acquisition instruction is transmitted to the third communication interface via the host computer debugging interface, and the third communication interface sends the processor information to the host computer debugging interface.
[0024] In a second aspect, an embodiment of the present application provides a chip debugging system, comprising a host computer and a chip described in any one of the above embodiments, wherein the host computer is connected to the chip.
[0025] The beneficial effects brought by the technical solution provided by the embodiment of the present application include at least:
[0026] The chip based on core-grain architecture provided by the embodiment of the present application comprises a debugging conversion module and processors of at least two architectures, wherein the debugging conversion module comprises a host computer debugging interface, a debugging interface management unit, and a hardware status management unit, wherein the host computer debugging interface is connected to the debugging interface management unit, the host computer debugging interface is connected to the hardware status management unit, the debugging interface management unit is connected to the hardware status management unit, and the processors of each architecture are respectively connected to the debugging interface management unit, the host computer debugging interface receives a processor status control instruction sent by the host computer, the processor status control instruction is transmitted to the hardware status management unit via the host computer debugging interface, the processor status control instruction is transmitted to the debugging interface management unit via the hardware status management unit, and the processor status control instruction is transmitted to the processor via the debugging interface management unit, the host computer debugging interface receives processor debugging data sent by the host computer, the processor debugging data is transmitted to the debugging interface management unit via the host computer debugging interface, the processor debugging data is converted into target debugging data corresponding to the processor via the debugging interface management unit, and the target debugging data is transmitted to the processor via the debugging interface management unit. Based on the connection relationship between the above-mentioned chip architecture and various hardware, the embodiments of the present application can realize the function of synchronously debugging processors of at least two architectures through the debugging conversion module in the chip, thereby improving the processor debugging efficiency of the core grain architecture chip configured with processors of at least two architectures. BRIEF DESCRIPTION OF THE DRAWINGS
[0027] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without paying any creative work.
[0028] Figure 1 It is a schematic diagram of the structure of a chip based on a core-grain architecture provided in an embodiment of the present application;
[0029] Figure 2 It is a schematic diagram of the structure of another chip based on the core particle architecture provided in the embodiment of the present application;
[0030] Figure 3 It is a schematic diagram of the structure of another chip based on the core particle architecture provided in the embodiment of the present application;
[0031] Figure 4 It is a schematic diagram of the structure of another chip based on the core particle architecture provided in the embodiment of the present application;
[0032] Figure 5 This is a system architecture diagram of a chip debugging system provided in an embodiment of the present application.
[0033] Description of the drawings: 1. Chip; 10. Debug conversion module; 11. Debug interface management unit; 12. Hardware status management unit; 13. Host computer debugging interface; 14. Hardware information storage unit; 111. First debugging interface; 112. Second debugging interface; 113. Third debugging interface; 121. First communication interface; 122. Second communication interface; 20. First processor; 21. First processor debugging interface; 30. Second processor; 31. Second processor debugging interface; 2. Host computer. DETAILED DESCRIPTION
[0034] In order to make the purpose, features, and advantages of the embodiments of the present application more obvious and understandable, the technical solutions in the embodiments of the present application will be clearly and completely described in combination with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of them. Based on the embodiments in the embodiments of the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the embodiments of the present application.
[0035] In the description of the embodiments of the present application, it should be understood that the terms "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance. In the description of the embodiments of the present application, it should be noted that, unless otherwise clearly specified and limited, "including" and "having" and any of their variations are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but optionally also includes steps or units that are not listed, or optionally also includes other steps or units inherent to these processes, methods, products or devices. For those of ordinary skill in the art, the specific meanings of the above terms in the embodiments of the present application can be understood in specific circumstances. In addition, in the description of the embodiments of the present application, unless otherwise specified, "multiple" refers to two or more. "And / or", describes the association relationship of associated objects, indicating that there can be three relationships, for example, A and / or B, can represent: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the associated objects before and after are an "or" relationship.
[0036] The present application is described in detail below with reference to specific embodiments.
[0037] See also Figure 1 , is a schematic diagram of a chip structure based on a core particle architecture provided in an embodiment of the present application. Figure 1 Taking a chip including processors of two architectures (a processor of a first architecture and a processor of a second architecture, the first architecture is different from the second architecture) as an example, the structure of the chip is described.
[0038] like Figure 1 As shown, the chip 1 includes a debugging conversion module 10, a first processor 20 of a first architecture, and a second processor 30 of a second architecture; the debugging conversion module 10 includes a debugging interface management unit 11, a hardware state management unit 12, and a host computer debugging interface 13. The host computer debugging interface 13 is connected to the debugging interface management unit 11, the host computer debugging interface 13 is connected to the hardware state management unit 12, the hardware state management unit 12 is connected to the debugging interface management unit 11, the first processor 20 is connected to the debugging interface management unit 11, and the second processor 30 is connected to the debugging interface management unit 11.
[0039] Combine the following Figure 1 The structure of the chip shown and the connection relationship between the various structures in the chip are used to explain the debugging principle of the chip.
[0040] In some embodiments, the host computer debugging interface 13 receives the processor state control instruction sent by the host computer, the processor state control instruction is transmitted to the hardware state management unit 12 via the host computer debugging interface 13, the processor state control instruction is transmitted to the debugging interface management unit 11 via the hardware state management unit 12, and the processor state control instruction is transmitted to the first processor 20 and the second processor 30 via the debugging interface management unit 11; the host computer debugging interface 13 receives the processor debugging data sent by the host computer, the processor debugging data is transmitted to the debugging interface management unit 11 via the host computer debugging interface 13, the processor debugging data is converted into target debugging data corresponding to the first processor 20 via the debugging interface management unit 11, the processor debugging data is converted into target debugging data corresponding to the second processor 30 via the debugging interface management unit 11, the target debugging data corresponding to the first processor 20 is transmitted to the first processor 20 via the debugging interface management unit 11, and the target debugging data corresponding to the second processor 30 is transmitted to the second processor 30 via the debugging interface management unit 11.
[0041] The host computer refers to a computer with a processor debugging function, and the processor debugging function refers to the function of debugging processors of different architectures in a chip.
[0042] The architecture of the processor may include, but is not limited to, ARM architecture, RISC-V architecture, X86 architecture, PowerPC architecture, etc. The first architecture may be any one of ARM architecture, RISC-V architecture, X86 architecture, and PowerPC architecture, and the second architecture may be any one of ARM architecture, RISC-V architecture, X86 architecture, and PowerPC architecture, but the first architecture is different from the second architecture.
[0043] It should be noted that the number of processors integrated in the chip of the embodiment of the present application is not limited to Figure 1 As shown in the number of processors, the chip of the embodiment of the present application can also integrate processors of more than two architectures. For example, the chip of the embodiment of the present application can integrate processors of three architectures, processors of four architectures, processors of five architectures, etc.
[0044] After the host computer debugging interface receives the processor state control instruction sent by the host computer, the host computer debugging interface transmits the processor state control instruction to the hardware state management unit, so that the hardware state management unit can control at least one processor to enter or exit the debugging state according to the instruction of the host computer. The hardware state management unit can transmit the processor state control instruction to the debugging interface management unit, so that the debugging interface management unit transmits the processor state control instruction to the processor, so that the processor can enter or exit the debugging state. The processor state control instruction can be an instruction that instructs the hardware state management unit to control at least one processor to enter or exit the debugging state.
[0045] After the host computer debugging interface receives the processor debugging data sent by the host computer, the host computer debugging interface transmits the processor debugging data to the debugging interface management unit, and the debugging interface management unit can be used to convert the processor debugging data sent by the host computer into target debugging data corresponding to the processor, and send the target debugging data to the corresponding processor to realize the function of debugging the processor. Because processors of different architectures have different corresponding debugging systems, and in order to overcome the inability to synchronously debug multiple processors of different architectures, this application realizes synchronous debugging of multiple processors of different architectures by converting the processor debugging data sent by the host computer into target debugging data corresponding to the processor.
[0046] In summary, the chip based on the core-grain architecture provided in the embodiment of the present application can integrate a debugging conversion module and processors of at least two architectures. The debugging conversion module also includes a host computer debugging interface, a hardware status management unit and a debugging interface management unit. The host computer debugging interface is connected to the hardware status management unit, the host computer debugging interface is connected to the debugging interface management unit, the hardware status management unit is connected to the debugging interface management, and the debugging interface management unit is connected to the processor of each architecture. The function of synchronously debugging processors of at least two architectures can be realized through the debugging conversion module in the chip, thereby improving the processor debugging efficiency of the core-grain architecture chip configured with processors of at least two architectures.
[0047] See next Figure 2 , is a schematic diagram of the structure of another chip based on the core grain architecture provided in an embodiment of the present application. Figure 2 Taking a chip including processors of two architectures (a processor of a first architecture and a processor of a second architecture, the first architecture is different from the second architecture) as an example, the structure of the chip is described.
[0048] like Figure 2As shown, the chip 1 includes a debugging conversion module 10, a first processor 20 of a first architecture, and a second processor 30 of a second architecture; the debugging conversion module 10 includes a debugging interface management unit 11, a hardware state management unit 12, a host computer debugging interface 13, and a hardware information storage unit 14. The host computer debugging interface 13 is connected to the debugging interface management unit 11, the host computer debugging interface 13 is connected to the hardware state management unit 12, and the host computer debugging interface 13 is connected to the hardware information storage unit 14; the hardware state management unit 12 is connected to the debugging interface management unit 11, the first processor 20 is connected to the debugging interface management unit 11, and the second processor 30 is connected to the debugging interface management unit 11.
[0049] It should be noted that the number of processors integrated in the chip of the embodiment of the present application is not limited to Figure 2 As shown in the number of processors, the chip of the embodiment of the present application can also integrate processors of more than two architectures. For example, the chip of the embodiment of the present application can integrate processors of three architectures, processors of four architectures, processors of five architectures, etc.
[0050] Combine the following Figure 2 The structure of the chip shown and the connection relationship between the various structures in the chip are used to explain the debugging principle of the chip.
[0051] In some embodiments, the host computer debugging interface 13 receives the processor information acquisition instruction sent by the host computer, the host computer debugging interface 13 transmits the processor information acquisition instruction to the hardware information storage unit 14, the hardware information storage unit 14 transmits the processor information to the host computer debugging interface 13, and the host computer debugging interface 13 transmits the processor information to the host computer 2; the host computer debugging interface 13 receives the processor state control instruction sent by the host computer, the processor state control instruction is transmitted to the hardware state management unit 12 via the host computer debugging interface 13, the processor state control instruction is transmitted to the debugging interface management unit 11 via the hardware state management unit 12, and the processor state control instruction is transmitted to the debugging interface management unit 11 via the debugging interface management unit 11 The host computer debugging interface 13 receives the processor debugging data sent by the host computer, and the processor debugging data is transmitted to the debugging interface management unit 11 via the host computer debugging interface 13. The processor debugging data is converted into target debugging data corresponding to the first processor 20 via the debugging interface management unit 11. The processor debugging data is converted into target debugging data corresponding to the second processor 30 via the debugging interface management unit 11. The target debugging data corresponding to the first processor 20 is transmitted to the first processor 20 via the debugging interface management unit 11, and the target debugging data corresponding to the second processor 30 is transmitted to the second processor 30 via the debugging interface management unit 11.
[0052] The processor information acquisition instruction may be an instruction for the host computer to obtain the processor information of the processor integrated on the chip from the hardware information storage unit. The processor information may include relevant information of the processor integrated on the chip, and the processor information may specifically include but is not limited to the number of processors on the chip, the architecture of each processor, the number of computing cores of each processor, etc.
[0053] Optionally, the hardware information storage unit 14 may include a third communication interface (not shown in the figure), the third communication interface is connected to the host computer debugging interface 13, the third communication interface receives the processor information acquisition instruction sent by the host computer debugging interface 13, the third communication interface transmits the processor information to the host computer debugging interface 13, and the host computer debugging interface 13 transmits the processor information to the host computer.
[0054] The host computer obtains the processor information and can determine the processor debugging strategy through the processor information, so as to facilitate synchronous debugging of the processor on the chip through the appropriate processor debugging strategy.
[0055] See next Figure 3 , is a schematic diagram of the structure of another chip based on the core grain architecture provided in an embodiment of the present application. Figure 3 Taking a chip including processors of two architectures (a processor of a first architecture and a processor of a second architecture, the first architecture is different from the second architecture) as an example, the structure of the chip is described.
[0056] like Figure 3 As shown, the chip 1 includes a debugging conversion module 10, a first processor 20 of a first architecture, and a second processor 30 of a second architecture; the debugging conversion module 10 includes a debugging interface management unit 11, a hardware state management unit 12, and a host computer debugging interface 13; the hardware state management unit 12 includes a first communication interface 121 and a second communication interface 122; the debugging interface management unit 11 includes a first debugging interface 111, a second debugging interface 112, and two third debugging interfaces 113. The first communication interface 121 is connected to the host computer debugging interface 13, the second communication interface 122 is connected to the second debugging interface 112, the first debugging interface 111 is connected to the host computer debugging interface 13, one third debugging interface 113 is connected to the first processor 20, and another third debugging interface 113 is connected to the second processor 30.
[0057] It should be noted that the number of processors integrated in the chip of the embodiment of the present application is not limited to Figure 3The number of processors shown in the figure, the chip of the embodiment of the present application can also integrate processors of more than two architectures, for example, the chip of the embodiment of the present application can integrate processors of three architectures, processors of four architectures, processors of five architectures, etc. The number of the third debugging interface in the embodiment of the present application is also not limited to Figure 3 As shown in the number, in another embodiment, the number of the third debugging interfaces is the same as the number of processors. When the chip integrates three processors, the number of the third debugging interfaces is also three. When the chip integrates four processors, the number of the third debugging interfaces is also four.
[0058] Combine the following Figure 3 The structure of the chip shown and the connection relationship between the various structures in the chip are used to explain the debugging principle of the chip.
[0059] In some embodiments, the first communication interface 121 receives a processor state control instruction sent by the host computer debugging interface 13, the processor state control instruction is transmitted to the second debugging interface 112 via the second communication interface 122, the processor state control instruction is transmitted to two third debugging interfaces 113 via the second debugging interface 112 respectively, the processor state control instruction is transmitted to the first processor 20 via one third debugging interface 113, and the processor state control instruction is transmitted to the second processor 30 via another third debugging interface 113; the first debugging interface 111 receives processor debugging data sent by the host computer debugging interface 13, the processor debugging data is converted into target debugging data corresponding to the first processor 20 via the debugging interface management unit 11, the processor debugging data is converted into target debugging data corresponding to the second processor 30 via the debugging interface management unit 11, the target debugging data corresponding to the first processor 20 is transmitted to the first processor 20 via one third debugging interface 113, and the target debugging data corresponding to the second processor 30 is transmitted to the second processor 30 via another third debugging interface 113.
[0060] See next Figure 4 , is a schematic diagram of the structure of another chip based on the core grain architecture provided in an embodiment of the present application. Figure 4 Taking a chip including processors of two architectures (a processor of a first architecture and a processor of a second architecture, the first architecture is different from the second architecture) as an example, the structure of the chip is described.
[0061] like Figure 4As shown, the chip 1 includes a debugging conversion module 10, a first processor 20 and a second processor 30; the debugging conversion module 10 includes a debugging interface management unit 11, a hardware state management unit 12, and a host computer debugging interface 13; the first processor 20 includes a first processor debugging interface 21, and the second processor 30 includes a second processor debugging interface 31. The host computer debugging interface 13 is connected to the debugging interface management unit 11, and the host computer debugging interface 13 is connected to the hardware state management unit 12; the hardware state management unit 12 is connected to the debugging interface management unit 11, the first processor debugging interface 21 is connected to the debugging interface management unit 11, and the second processor debugging interface 31 is connected to the debugging interface management unit 11.
[0062] It should be noted that the number of processors integrated in the chip of the embodiment of the present application is not limited to Figure 4 As shown in the number of processors, the chip of the embodiment of the present application can also integrate processors of more than two architectures. For example, the chip of the embodiment of the present application can integrate processors of three architectures, processors of four architectures, processors of five architectures, etc.
[0063] In some embodiments, the hardware state management unit can receive processor state control instructions sent by the host computer debugging interface, and transmit the processor state control instructions to the debugging interface management unit. The debugging interface management unit can convert the processor state control instructions into target processor control instructions corresponding to the first processor debugging interface. The debugging interface management unit can transmit the target processor control instructions corresponding to the first processor debugging interface to the first processor debugging interface, so that the first processor enters the debugging state or exits the debugging state; the debugging interface management unit can convert the processor state control instructions into target processor control instructions corresponding to the second processor debugging interface. The debugging interface management unit can transmit the target processor control instructions corresponding to the second processor debugging interface to the second processor debugging interface, so that the second processor enters the debugging state or exits the debugging state.
[0064] The debugging interface management unit can be used to convert the processor debugging data sent by the host computer debugging interface into target debugging data corresponding to the first processor debugging interface, and can transmit the target debugging data corresponding to the first processor debugging interface to the first processor debugging interface to realize debugging of the first processor of the first architecture; the debugging interface management unit can be used to convert the processor debugging data sent by the host computer into target debugging data corresponding to the second processor debugging interface, and can transmit the target debugging data corresponding to the second processor debugging interface to the second processor debugging interface to realize debugging of the second processor of the second architecture.
[0065] Specifically, the first processor debugging interface may be an international standard test interface (Joint Test Action Group, referred to as JTAG), a serial wire debug interface (Serial Wire Debug, referred to as SWD) or other debugging interfaces. The second processor debugging interface may be an international standard test interface (Joint Test Action Group, referred to as JTAG), a serial wire debug interface (Serial Wire Debug, referred to as SWD) or other debugging interfaces.
[0066] The target debugging data corresponding to the first processor debugging interface may be debugging data that can be parsed by the first processor debugging interface. The target debugging data corresponding to the second processor debugging interface may be debugging data that can be parsed by the second processor debugging interface.
[0067] Since processors of different architectures have corresponding debugging systems that are different, in order to overcome the inability to synchronously debug multiple processors of different architectures, the present application converts the processor debugging data sent by the host computer into target debugging data corresponding to the debugging interfaces of different processors, so that processors of different architectures can synchronously receive the corresponding target debugging data, thereby achieving synchronous debugging of multiple processors of different architectures.
[0068] In some embodiments, the first processor debugging interface can transmit debugging response data corresponding to the first processor to the debugging interface management unit, the debugging response data is converted into target debugging response data corresponding to the host computer by the debugging interface management unit, and the target debugging response data is transmitted to the host computer by the debugging interface management unit. The second processor debugging interface can transmit debugging response data corresponding to the second processor to the debugging interface management unit, the debugging response data is converted into target debugging response data corresponding to the host computer by the debugging interface management unit, and the target debugging response data is transmitted to the host computer by the debugging interface management unit.
[0069] Among them, the host computer debugging interface can be different from the debugging interfaces of processors of different architectures, that is, the host computer debugging interface can be different from the debugging interface of the first processor, and the host computer debugging interface can also be different from the debugging interface of the second processor. Therefore, when the debugging interface management unit transmits the debugging response data corresponding to the processors of different architectures to the host computer debugging interface, the debugging interface management unit can convert the debugging response data into target debugging response data that can be parsed by the host computer debugging interface, so that the host computer can obtain the debugging response content of the processors of different architectures through only one host computer debugging interface.
[0070] In some other embodiments, the processor state control instruction is converted into a first processor state control instruction corresponding to the first processor debug interface by the debug interface management unit, the first processor state control instruction is transmitted to the first processor debug interface by the debug interface management unit, and the first processor state control instruction is used to trigger the first processor to enter the debug state or exit the debug state; the first processor debug interface transmits the first debug state data corresponding to the first processor to the debug interface management unit, and the first debug state data is transmitted to the hardware state management unit via the debug interface management unit; the hardware state management unit transmits the second processor state control instruction to the debug interface management unit, the second processor state control instruction is converted into a third processor state control instruction corresponding to the second processor debug interface by the debug interface management unit, the third processor state control instruction is transmitted to the second processor debug interface via the debug interface management unit, and the third processor state control instruction is used to trigger the second processor to enter the debug state or exit the debug state.
[0071] Specifically, when the host computer is debugging multiple processors of different architectures simultaneously, the hardware state management unit can first obtain the processor state control general instruction sent by the host computer through the host computer debugging interface. The processor state control general instruction can be a general instruction for instructing the hardware state management unit to control all processors to enter or exit the debugging state. The following takes the processor state control general instruction as an example of a general instruction for controlling all processors to enter the debugging state to illustrate the implementation process of the hardware state management unit first controlling the first processor to enter the debugging state, and then controlling the second processor to enter the debugging state after the first processor enters the debugging state.
[0072] After the hardware state management unit receives the general instruction for controlling all processors to enter the debugging state sent by the host computer through the host computer debugging interface, the hardware state management unit can receive the processor state control instruction sent by the host computer through the host computer debugging interface. The processor state control instruction at this time can be an instruction for instructing the hardware state management unit to control the first processor to enter or exit the debugging state. The processor state control instruction at this time can be converted into a first processor state control instruction corresponding to the first processor debugging interface by the debugging interface management unit, and the first processor state control instruction is transmitted to the first processor debugging interface by the debugging interface management unit. When the first processor state control instruction triggers the first processor to enter the debugging state, the first processor debugging interface can transmit the first debugging state data corresponding to the first processor to the debugging interface management unit, and the first debugging state data is transmitted to the hardware state management unit via the debugging interface management unit. Next, the hardware state management unit transmits the second processor state control instruction to the debugging interface management unit. The second processor state control instruction may be an instruction for controlling the second processor to enter the debugging state. The second processor state control instruction is converted by the debugging interface management unit into a third processor state control instruction corresponding to the second processor debugging interface. The third processor state control instruction is transmitted to the second processor debugging interface via the debugging interface management unit to control the second processor to enter the debugging state.
[0073] For example, the processor state control instruction may be a single-step debugging instruction, and the single-step debugging instruction may be an instruction that instructs the processor to enter the debugging state after executing an instruction. At this time, the single-step debugging instruction may be converted into a first single-step debugging instruction corresponding to the first processor debugging interface by the debugging interface management unit, and the first single-step debugging instruction may be a single-step debugging instruction that can be parsed by the first processor debugging interface. The first single-step debugging instruction may be transmitted to the first processor debugging interface by the debugging interface management unit, so that the first processor enters the debugging state after executing the first single-step debugging instruction. After the first processor enters the debugging state, the first processor may generate first debugging state data that has entered the debugging state, and the first processor debugging interface may transmit the first debugging state data to the debugging interface management unit, so that the debugging interface management unit transmits the first debugging state data to the hardware state management unit, so that the hardware state management unit sends the second processor state control instruction to the debugging interface management unit after learning that the first processor has entered the debugging state, thereby controlling the second processor to also enter the debugging state.
[0074] See next Figure 5 , is a system architecture diagram of a chip debugging system provided in an embodiment of the present application. Figure 5Taking a chip including processors of two architectures (a processor of a first architecture and a processor of a second architecture, the first architecture is different from the second architecture) as an example, the chip debugging system is described.
[0075] like Figure 5 As shown, the chip debugging system includes a chip 1 and a host computer 2; the chip 1 includes a debugging conversion module 10, a first processor 20 of a first architecture, and a second processor 30 of a second architecture; the debugging conversion module 10 includes a debugging interface management unit 11, a hardware state management unit 12, and a host computer debugging interface 13. The host computer debugging interface 13 is connected to the debugging interface management unit 11, the host computer debugging interface 13 is connected to the hardware state management unit 12, the host computer debugging interface 13 is connected to the hardware information storage unit 14, and the host computer debugging interface 13 is connected to the host computer 2; the hardware state management unit 12 is connected to the debugging interface management unit 11, the first processor 20 is connected to the debugging interface management unit 11, and the second processor 30 is connected to the debugging interface management unit 11.
[0076] It should be noted that the number of processors integrated in the chip of the embodiment of the present application is not limited to Figure 5 As shown in the number of processors, the chip of the embodiment of the present application can also integrate processors of more than two architectures. For example, the chip of the embodiment of the present application can integrate processors of three architectures, processors of four architectures, processors of five architectures, etc.
[0077] In some embodiments, the host computer debugging interface 13 receives the processor state control instruction sent by the host computer 2, the processor state control instruction is transmitted to the hardware state management unit 12 via the host computer debugging interface 13, the processor state control instruction is transmitted to the debugging interface management unit 11 via the hardware state management unit 12, and the processor state control instruction is transmitted to the first processor 20 and the second processor 30 via the debugging interface management unit 11; the host computer debugging interface 13 receives the processor debugging data sent by the host computer 2, the processor debugging data is transmitted to the debugging interface management unit 11 via the host computer debugging interface 13, the processor debugging data is converted into target debugging data corresponding to the first processor 20 via the debugging interface management unit 11, the processor debugging data is converted into target debugging data corresponding to the second processor 30 via the debugging interface management unit 11, the target debugging data corresponding to the first processor 20 is transmitted to the first processor 20 via the debugging interface management unit 11, and the target debugging data corresponding to the second processor 30 is transmitted to the second processor 30 via the debugging interface management unit 11.
[0078] based on Figure 5As shown in the system architecture diagram of the chip debugging system, the host computer debugging interface of the embodiment of the present application can receive the processor state control instructions and processor debugging data sent by the host computer. The processor state control instructions can be used to synchronously control processors of different architectures to enter or exit the debugging state, and the processor debugging data can be used to synchronously debug processors of different architectures, thereby improving the processor debugging efficiency of the core grain architecture chip configured with processors of at least two architectures. In addition, the embodiment of the present application uses a host computer debugging interface to synchronously debug processors of different architectures integrated on the chip, reducing the number of host computer debugging interfaces used and saving hardware costs when synchronously debugging processors of different architectures.
[0079] The same or similar numbers in the drawings of this embodiment correspond to the same or similar elements; in the description of this application, it should be understood that if the terms "upper", "lower", "left", "right", etc. indicate an orientation or positional relationship based on the orientation or positional relationship shown in the drawings, it is only for the convenience of describing this application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, the terms describing the positional relationship in the drawings are only used for illustrative purposes and cannot be understood as a limitation on this patent. For ordinary technicians in this field, the specific meanings of the above terms can be understood according to specific circumstances.
[0080] The above description is only a preferred embodiment of the embodiments of the present application and is not intended to limit the embodiments of the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the embodiments of the present application should be included in the protection scope of the embodiments of the present application.
Claims
1. A chip based on a core particle architecture, characterized in that: The chip includes a debugging conversion module and processors of at least two architectures, the debugging conversion module includes a host computer debugging interface, a debugging interface management unit, and a hardware status management unit, the host computer debugging interface is connected to the debugging interface management unit, the host computer debugging interface is connected to the hardware status management unit, the debugging interface management unit is connected to the hardware status management unit, and the processors of each architecture are respectively connected to the debugging interface management unit, wherein: The host computer debugging interface receives a processor state control instruction sent by the host computer, the processor state control instruction is transmitted to the hardware state management unit via the host computer debugging interface, the processor state control instruction is transmitted to the debugging interface management unit via the hardware state management unit, and the processor state control instruction is transmitted to the processor via the debugging interface management unit; The host computer debugging interface receives processor debugging data sent by the host computer, and the processor debugging data is transmitted to the debugging interface management unit via the host computer debugging interface. The processor debugging data is converted into target debugging data corresponding to the processor via the debugging interface management unit, and the target debugging data is transmitted to the processor via the debugging interface management unit.
2. The chip according to claim 1, characterized in that: The processor comprises a processor debugging interface, and the processor debugging interface is connected to the debugging interface management unit; The processor debugging data is converted into target debugging data corresponding to the processor debugging interface by the debugging interface management unit, and the target debugging data is transmitted to the processor debugging interface by the debugging interface management unit, and the target debugging data is used to debug the processor.
3. The chip according to claim 2, characterized in that: The processor debugging interface transmits the debugging response data corresponding to the processor to the debugging interface management unit, the debugging response data is converted into target debugging response data corresponding to the host computer debugging interface by the debugging interface management unit, the target debugging response data is transmitted to the host computer debugging interface by the debugging interface management unit, and the target debugging response data is transmitted to the host computer via the host computer debugging interface.
4. The chip according to claim 2, characterized in that: The processor state control instruction is converted into a target processor state control instruction corresponding to the processor debug interface by the debug interface management unit, and the target processor state control instruction is transmitted to the processor debug interface by the debug interface management unit. The target processor state control instruction is used to trigger the processor to enter the debug state or exit the debug state.
5. The chip according to claim 1, characterized in that: The processor comprises a first processor of a first architecture and a second processor of a second architecture, the first processor comprises a first processor debugging interface, the second processor comprises a second processor debugging interface, the first processor debugging interface is connected to the debugging interface management unit, and the second processor debugging interface is connected to the debugging interface management unit; The processor state control instruction is converted by the debug interface management unit into a first processor state control instruction corresponding to the first processor debug interface, the first processor state control instruction is transmitted to the first processor debug interface by the debug interface management unit, and the first processor state control instruction is used to trigger the first processor to enter a debug state or exit a debug state; The first processor debugging interface transmits first debugging status data corresponding to the first processor to the debugging interface management unit, and the first debugging status data is transmitted to the hardware status management unit via the debugging interface management unit; The hardware state management unit transmits a second processor state control instruction to the debug interface management unit, the second processor state control instruction is converted by the debug interface management unit into a third processor state control instruction corresponding to the second processor debug interface, the third processor state control instruction is transmitted to the second processor debug interface via the debug interface management unit, and the third processor state control instruction is used to trigger the second processor to enter a debug state or exit a debug state.
6. The chip according to claim 1, characterized in that: The hardware status management unit includes a first communication interface and a second communication interface, the first communication interface is connected to the host computer debugging interface, and the second communication interface is connected to the debugging interface management unit; The processor state control instruction is transmitted to the first communication interface via the host computer debugging interface, and the processor state control instruction is transmitted to the debugging interface management unit via the second communication interface.
7. The chip according to claim 1, characterized in that: The debugging interface management unit includes a first debugging interface, a second debugging interface, and at least two third debugging interfaces, wherein the first debugging interface is connected to the host computer debugging interface, the second debugging interface is connected to the hardware state management unit, and the third debugging interfaces are respectively connected to processors of each architecture; The processor state control instruction is transmitted to the second debugging interface via the hardware state management unit, and the processor state control instruction is transmitted to the processor via the third debugging interface; The processor debugging data is transmitted to the first debugging interface via the host computer debugging interface, the processor debugging data is converted into target debugging data corresponding to the processor via the debugging interface management unit, and the target debugging data is transmitted to the processor via the third debugging interface.
8. The chip according to claim 1, characterized in that: The debugging conversion module also includes a hardware information storage unit, which is connected to the host computer debugging interface; wherein, The host computer debugging interface receives a processor information acquisition instruction sent by the host computer, and the processor information acquisition instruction is transmitted to the hardware information storage unit via the host computer debugging interface. The hardware information storage unit sends processor information to the host computer debugging interface, and the hardware information storage unit transmits it to the host computer via the host computer debugging interface.
9. The chip according to claim 8, characterized in that: The hardware information storage unit includes a third communication interface, and the third communication interface is connected to the host computer debugging interface; The processor information acquisition instruction is transmitted to the third communication interface via the host computer debugging interface, and the third communication interface sends the processor information to the host computer debugging interface.
10. A chip debugging system, characterized in that: It comprises a host computer and a chip as claimed in any one of claims 1 to 9, wherein the host computer is connected to the chip.