Display device

Abstract

The utility model provides a display device. The display device comprises a time schedule controller; the memory is provided with a data write-in end and a write protection signal input end, and the data write-in end is electrically connected with the time schedule controller to receive rewritten data; and the write protection circuit is provided with a control signal input end and a write protection signal output end, the control signal input end is used for receiving a control signal, and the write protection signal output end is electrically connected with the write protection signal input end to control the level of the write protection signal input end. According to the application, the level of the write protection signal input end of the memory is controlled through the write protection circuit, and the phenomenon that data stored in the memory is rewritten due to unstable voltage of the time schedule controller is avoided.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display device. Background Art

[0002] Currently, during the power on and off process of a display device, there is a phenomenon that a timing controller (TCON) sends an erroneous instruction to a memory due to voltage instability, causing data stored in the memory to be overwritten. This will cause the timing controller to fail to work properly at the next startup and cause a black screen on the display device. Utility Model Content

[0003] The present application provides a display device, aiming to solve the above technical problems.

[0004] In a first aspect, the present application provides a display device, comprising:

[0005] Timing controller;

[0006] A memory having a data writing terminal and a write protection signal input terminal, wherein the data writing terminal is electrically connected to the timing controller; and

[0007] A write protection circuit having a control signal input terminal and a write protection signal output terminal, wherein the write protection signal output terminal is electrically connected to the write protection signal input terminal;

[0008] Wherein, the write protection circuit includes a first resistor and a first transistor;

[0009] One end of the first resistor is electrically connected to the power supply end of the display device, and the other end of the first resistor is electrically connected to the first end of the first transistor and the write protection signal output end;

[0010] The second end of the first transistor is electrically connected to the ground end of the display device, the control end of the first transistor is electrically connected to the control signal input end, and the control end of the first transistor is electrically connected to the control signal input end.

[0011] In some embodiments, when the control signal input terminal receives a high level signal, the first transistor is in a conducting state, so that the write protection signal output terminal outputs a low level signal;

[0012] When the control signal input terminal receives a low level signal, the first transistor is in a cut-off state, so that the write protection signal output terminal outputs a high level signal.

[0013] In some embodiments, the write protection circuit further includes a second resistor and a second transistor;

[0014] One end of the second resistor is electrically connected to the power supply end of the display device, and the other end of the second resistor is electrically connected to the first end of the second transistor;

[0015] The second end of the second transistor is electrically connected to the ground end of the display device, the control end of the second transistor is electrically connected to the control signal input end, the control end of the first transistor is electrically connected to the other end of the second resistor, and the control end of the second transistor is electrically connected to the control signal input end.

[0016] In some embodiments, when the control signal input terminal receives a high level signal, the second transistor is in an on state and the first transistor is in an off state, so that the write protection signal output terminal outputs a high level signal;

[0017] When the control signal input terminal receives a low level signal, the second transistor is in a cut-off state, and the first transistor is in a turn-on state, so that the write protection signal output terminal outputs a low level signal.

[0018] In some embodiments, the write protection circuit further includes a third transistor;

[0019] The first end of the third transistor is electrically connected to the other end of the second resistor, the second end of the third transistor is electrically connected to the ground end of the display device, and the control end of the third transistor is electrically connected to the control signal input end.

[0020] In some embodiments, when the control signal input terminal receives a high level signal, the third transistor is in an on state and the first transistor is in an off state, so that the write protection signal output terminal outputs a high level signal;

[0021] When the control signal input terminal receives a low level signal, the third transistor is in a cut-off state, and the first transistor is in a conducting state, so that the write protection signal output terminal outputs a low level signal.

[0022] In some embodiments, the control signal input terminal includes a first input terminal and a second input terminal;

[0023] The control end of the second transistor is electrically connected to the first input end, and the control end of the third transistor is electrically connected to the second input end.

[0024] In some embodiments, the write protection circuit further includes a fourth resistor and a fourth transistor;

[0025] A first end of the fourth transistor is electrically connected to a power supply end of the display device, and a second end of the fourth transistor is electrically connected to a first end of a fourth resistor;

[0026] The second end of the fourth resistor is electrically connected to the ground end of the display device, the control end of the first transistor is electrically connected to the first end of the fourth resistor, and the control end of the fourth transistor is electrically connected to the control signal input end.

[0027] In some embodiments, when the control signal input terminal receives a high level signal, the fourth transistor is in a conducting state, and the first transistor is in a conducting state, so that the write protection signal output terminal outputs a low level signal;

[0028] When the control signal input terminal receives a low level signal, the fourth transistor is in a cut-off state, and the first transistor is in a cut-off state, so that the write protection signal output terminal outputs a high level signal.

[0029] In some embodiments, the write protection circuit further includes a fifth resistor and a fifth transistor;

[0030] A first end of the fifth transistor is electrically connected to a power supply end of the display device, and a second end of the fifth transistor is electrically connected to a first end of a fifth resistor;

[0031] The second end of the fifth resistor is electrically connected to the ground end of the display device, the control end of the fourth transistor is electrically connected to the first end of the fifth resistor, and the control end of the fifth transistor is electrically connected to the control signal input end.

[0032] The present application electrically connects the write protection signal output terminal of the write protection circuit with the write protection signal input terminal of the memory. When the write protection circuit receives a control signal, the write protection circuit outputs a second level signal to the write protection signal input terminal and enables the memory to write the rewrite data; and when the write protection circuit does not receive a control signal, the write protection circuit outputs a first level signal to the write protection signal input terminal and restricts the memory from writing the rewrite data. In other words, the memory will rewrite the data stored therein only when the rewrite data is received at the data write terminal of the memory and the write protection circuit receives a control signal, thereby avoiding the phenomenon that the data stored in the memory is rewritten due to voltage instability of the timing controller. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 is a schematic diagram of a display device provided in an embodiment of the present application;

[0034] Figure 2 is another schematic diagram of a display device provided in an embodiment of the present application;

[0035] Figure 3 is another schematic diagram of a display device provided in an embodiment of the present application;

[0036] Figure 4 is another schematic diagram of a display device provided in an embodiment of the present application;

[0037] Figure 5 is another schematic diagram of a display device provided in an embodiment of the present application.

[0038] Among them, timing controller-10, memory-20, write protection circuit-30, data writing terminal-IN, write protection signal input terminal-Wp, control signal input terminal Vi, first input terminal Vi1, second input terminal Vi2, write protection signal output terminal Vo;

[0039] First resistor-R1, first transistor-Q1, first node-M1, second resistor-R2, second transistor-Q2, second node-M2, third transistor-Q3, fourth resistor-R4, fourth transistor-Q4, fourth node-M4, fifth transistor-Q5, fifth node-M5. DETAILED DESCRIPTION

[0040] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. The technical solutions described below are only used to explain and illustrate the ideas of the present application and should not be regarded as limiting the scope of protection of the present application.

[0041] The present application provides a display device, which is described in detail below. Figure 1 , Figure 1 A schematic diagram of a display device in an embodiment of the present application is shown, wherein the display device includes a timing controller 10, a memory 20 and a write protection circuit 30. It should be noted that: Figure 1 Only some modules of the display device are shown. In fact, the display device may also include other modules, such as a display panel, a source driver chip, and a gate driver chip, etc. These have been fully described in the relevant technology and will not be repeated in this application. At the same time, the display device of the present application may be, but is not limited to, a liquid crystal display device, an OLED display device, a quantum dot display device, a Mini-LED display device, or a Micro-LED display device, etc., and this application does not make specific limitations.

[0042] Specifically, the timing controller 10 can receive and process the LVDS (Low Voltage Differential Signaling) image data signal from the digital board or the main board, thereby converting it into a control signal and a row and column signal that can be recognized by the display panel, so as to drive the display panel for display. It is understandable that the timing controller 10 can read the data in the memory 20 and work normally, for example, converting the received image data signal into a row and column signal according to the data in the memory 20. Therefore, when the data in the memory 20 is rewritten, it may cause the timing controller 10 to fail to work normally.

[0043] The memory 20 is used to store data related to the operation of the display panel. For example, the memory 20 can store data related to the operation of the timing controller 10; for another example, the memory 20 can store data related to the operation of the source driver chip and the gate driver chip. The memory 20 has a data write terminal IN and a write protection signal input terminal Wp. The data write terminal IN is electrically connected to the timing controller 10 to receive the rewrite data. The write protection signal input terminal Wp can control whether the memory 20 writes the rewrite data. For example, when the write protection signal input terminal Wp receives a high-level signal, the memory 20 is in a writable state; when the write protection signal input terminal Wp receives a low-level signal, the memory 20 is in a non-writable state to limit the memory 20 from writing the rewrite data. Exemplarily, the memory 20 can be, but is not limited to, a random access memory, a buffer memory, a flash memory, etc.

[0044] The write protection circuit 30 is used to control the level of the write protection signal input terminal Wp of the memory 20 to control whether the memory 20 is changed to a writable state or a non-writable state. The write protection circuit 30 has a control signal input terminal Vi and a write protection signal output terminal Vo. The control signal input terminal Vi of the write protection circuit 30 is used to receive a control signal. The write protection signal output terminal Vo of the write protection circuit 30 is electrically connected to the write protection signal input terminal Wp, so that the level of the write protection signal input terminal Wp of the memory 20 is controlled by the electrical signal output by the write protection signal output terminal Vo of the write protection circuit 30.

[0045] Among them, the write protection circuit 30 includes a first resistor R1 and a first transistor Q1; one end of the first resistor R1 is electrically connected to the power supply end of the display device, and the other end of the first resistor R1 is electrically connected to the first end of the first transistor Q1 and the write protection signal output end; the second end of the first transistor Q1 is electrically connected to the ground end of the display device, the write protection signal input end Wp is electrically connected to the first node M1 between the first resistor R1 and the first transistor Q1, and the control end of the first transistor M1 is electrically connected to the control signal input end Vi. The potential of the first node M1 is controlled by turning on or off the first transistor Q1, thereby finally achieving the purpose of inputting a first level signal or a second level signal to the write protection signal input end Wp of the memory 20.

[0046] It should be noted that the first pole / first end of each transistor used in the embodiments of the present application is one of the source and the drain, the second pole / second end of each transistor is the other of the source and the drain, and the control end of each transistor is the gate. Since the source and drain of the transistor can be symmetrical in structure, the source and drain can be indistinguishable in structure, that is, the first pole / first end and the second pole / second end of the transistor in the embodiments of the present application can be indistinguishable in structure, but for the convenience of explanation, in the exemplary embodiment, the end with a lower voltage is usually referred to as the source, and the other end with a higher voltage is referred to as the drain, that is, when the thin film transistor is in the on state, the current flows from the drain to the source. Optionally, in other exemplary embodiments, the end with a lower voltage can also be referred to as the drain, and the other end with a higher voltage can be referred to as the source, that is, when the thin film transistor is in the on state, the current flows from the source to the drain. Exemplarily, when the transistor is a P-type transistor, the first electrode / first end of the transistor is the source, and the second electrode / second end is the drain; Exemplarily, when the transistor is an N-type transistor, the first electrode / first end of the transistor is the drain, and the second electrode / second end is the source. At the same time, the transistor referred to in the embodiments of the present application can be a low-potential conduction transistor, such as a PMOS tube, or a high-potential conduction transistor, such as an NMOS tube, and the present application does not make specific limitations.

[0047] In the embodiment of the present application, when the write protection circuit 30 receives a control signal, the write protection circuit 30 outputs a second level signal to the write protection signal input terminal Wp and enables the memory 20 to write the rewrite data; and when the write protection circuit 30 does not receive a control signal, the write protection circuit 30 outputs a first level signal to the write protection signal input terminal Wp and restricts the memory 20 from writing the rewrite data. That is, only when the data write terminal IN of the memory 20 receives the rewrite data and the write protection circuit 30 receives the control signal, the memory 20 will rewrite the data stored therein, thereby avoiding the phenomenon that the data stored in the memory 20 is rewritten due to the voltage instability of the timing controller 10.

[0048] It can be understood that if data can be written when the write protection pin of the memory 20 receives a high-level signal, the voltage of the first-level signal is less than the voltage of the second-level signal, that is, the first-level signal is a low-level signal, and the second-level signal is a high-level signal; conversely, if data can be written when the write protection pin of the memory 20 receives a low-level signal, the voltage of the first-level signal is greater than the voltage of the second-level signal, that is, the first-level signal is a high-level signal, and the second-level signal is a low-level signal.

[0049] In some embodiments of the present application, the control end of the first transistor Q1 can directly receive a control signal. When the control end of the first transistor Q1 does not receive the control signal, the first transistor Q1 is in an on state, so the first node M1 is directly grounded, thereby generating a low-level signal at the first node M1 and limiting the memory 20 from writing rewrite data; conversely, when the control end of the first transistor Q1 receives a control signal, the first transistor Q1 is in an off state, the first node M1 is not grounded and its voltage is close to or equal to the voltage of the power supply end of the display device, thereby generating a high-level signal at the first node M1 and allowing the memory 20 to write rewrite data.

[0050] For example, taking the first transistor Q1 as an NMOS tube, when the control signal input terminal Vi receives a high-level signal, the first transistor Q1 is in an on state, thereby generating a low-level signal at the first node M1 and causing the write protection signal output terminal Vo to output a low-level signal, ultimately causing the write protection signal input terminal Wp to receive a low-level signal and restricting the memory 20 from writing rewrite data; conversely, when the control signal input terminal Vi receives a low-level signal, the first transistor Q1 is in an off state, thereby generating a high-level signal at the first node M1 and causing the write protection signal output terminal Vo to output a high-level signal, ultimately causing the write protection signal input terminal Wp to receive a high-level signal and causing the memory 20 to write rewrite data.

[0051] In some embodiments of the present application, the first transistor Q1 may also be indirectly controlled by a control signal, for example, Figure 2 , Figure 2 Another schematic diagram of the display device in the embodiment of the present application is shown, wherein the write protection circuit 30 also includes a second resistor R2 and a second transistor Q2; one end of the second resistor R2 is electrically connected to the power supply end of the display device, and the other end is electrically connected to the first end of the second transistor Q2; the second end of the second transistor Q2 is electrically connected to the ground end of the display device, the control end of the second transistor Q2 is electrically connected to the control signal input end Vi, and the control end of the first transistor Q1 is electrically connected to the other end of the second resistor R2, that is, the control end of the first transistor Q1 is electrically connected to the second node M2 ​​between the second resistor R2 and the second transistor Q2, and the potential of the second node M2 ​​is controlled by the conduction of the second transistor Q2, thereby indirectly controlling the conduction of the first transistor Q1 by the potential of the second node M2, and finally achieving the purpose of inputting the first level signal or the second level signal to the write protection signal input end Wp of the memory 20.

[0052] In some embodiments of the present application, the control end of the second transistor Q2 can directly receive a control signal. When the control end of the second transistor Q2 does not receive the control signal, the second transistor Q2 is in a cut-off state, so the second node M2 ​​is not grounded and its voltage is close to or equal to the voltage of the power supply end of the display device, so that the first transistor Q1 is turned on and the first node M1 is directly grounded, thereby generating a low-level signal at the first node M1 and limiting the memory 20 from writing rewrite data; conversely, when the control end of the third transistor Q3 receives a control signal, the second transistor Q2 is in a turned-on state, so the second node M2 ​​is grounded so that the first transistor Q1 is in a cut-off state, the first node M1 is not grounded and its voltage is close to or equal to the voltage of the power supply end of the display device, thereby generating a high-level signal at the first node M1 and allowing the memory 20 to write rewrite data.

[0053] For example, taking the first transistor Q1 and the second transistor Q2 as NMOS tubes, when the control signal input terminal Vi receives a high-level signal, the second transistor Q2 is in an on state and the first transistor Q1 is in an off state, thereby generating a high-level signal at the first node M1 and causing the write protection signal output terminal Vo to output a high-level signal, ultimately causing the write protection signal input terminal Wp to receive a high-level signal and causing the memory 20 to write the rewrite data; conversely, when the control signal input terminal Vi receives a low-level signal, the second transistor Q2 is in an off state and the first transistor Q1 is in an on state, thereby generating a low-level signal at the first node M1 and causing the write protection signal output terminal Vo to output a low-level signal, ultimately causing the write protection signal input terminal Wp to receive a low-level signal and limiting the memory 20 from writing the rewrite data.

[0054] In some embodiments of the present application, multiple transistors may be used to control whether the first transistor Q1 is turned on. For example, see Figure 3 , Figure 3Another schematic diagram of the display device in an embodiment of the present application is shown, wherein the write protection circuit 30 also includes a third transistor Q3, a first end of the third transistor Q3 is electrically connected to the other end of the second resistor R2 (the second node M2), and a second end of the third transistor Q3 is electrically connected to the ground end of the display device. Specifically, the control end of the third transistor Q3 is electrically connected to the control signal input end Vi of the write protection circuit 30, that is, the control end of the third transistor Q3 can directly receive the control signal. When the control end of the third transistor Q3 does not receive the control signal, the third transistor Q3 is in a cut-off state, so the second node M2 ​​is not grounded and its voltage is close to or equal to the voltage of the power supply end of the display device, so that the first transistor Q1 is turned on and the first node M1 is directly grounded, thereby generating a low-level signal at the first node M1 and limiting the memory 20 from writing rewrite data; conversely, when the control end of the third transistor Q3 receives the control signal, the third transistor Q3 is in a turned-on state, so the second node M2 ​​is grounded so that the first transistor Q1 is in a cut-off state, the first node M1 is not grounded and its voltage is close to or equal to the voltage of the power supply end of the display device, thereby generating a high-level signal at the first node M1 and allowing the memory 20 to write rewrite data.

[0055] For example, taking the first transistor and the third transistor as NMOS tubes, when the control signal input terminal Vi receives a high-level signal, the third transistor Q3 is in an on state and the first transistor Q1 is in an off state, thereby generating a high-level signal at the first node M1 and causing the write protection signal output terminal Vo to output a high-level signal, ultimately causing the write protection signal input terminal Wp to receive a high-level signal and causing the memory 20 to write rewrite data; conversely, when the control signal input terminal Vi receives a low-level signal, the third transistor Q3 is in an off state and the first transistor Q1 is in an on state, thereby generating a low-level signal at the first node M1 and causing the write protection signal output terminal Vo to output a low-level signal, ultimately causing the write protection signal input terminal Wp to receive a low-level signal and limiting the memory 20 from writing rewrite data.

[0056] In some embodiments of the present application, the control signal input terminal Vi of the write protection circuit 30 may include a first input terminal Vi1 and a second input terminal Vi2, the control terminal of the second transistor Q2 is electrically connected to the first input terminal Vi1 of the write protection circuit 30, and the control terminal of the third transistor Q3 is electrically connected to the second input terminal Vi2 of the write protection circuit 30. When the first input terminal Vi1 and / or the second input terminal Vi2 receive the control signal, the write protection circuit 30 can output a second level signal to the write protection signal input terminal Wp and enable the memory 20 to write and rewrite data. This method can control whether the memory 20 writes data through a larger number of control ports to adapt to the data rewriting requirements of the memory 20 in different scenarios. For example, the control terminal of the second transistor Q2 can be used as a control port of a de-mura production node of a display device to control the memory 20 to rewrite data at the de-mura production node; for another example, the control terminal of the third transistor Q3 can be used as a control port of a g-gamma production node of a display device to control the memory 20 to rewrite data at the g-gamma production node.

[0057] In some embodiments of the present application, see Figure 4 , Figure 4 Another schematic diagram of the display device in the embodiment of the present application is shown, wherein the write protection circuit 30 further includes a fourth resistor R4 and a fourth transistor Q4; the first end of the fourth transistor Q4 is electrically connected to the power supply end of the display device, the second end of the fourth transistor Q4 is electrically connected to the first end of the fourth resistor R4; the second end of the fourth resistor R4 is electrically connected to the ground end of the display device, and the control end of the first transistor M1 is electrically connected to the first end of the fourth resistor R4, that is, the control end of the first transistor M1 is electrically connected to the fourth node M4 between the fourth resistor R4 and the fourth transistor Q4. In other words, the fourth transistor Q4 can also be connected to the power supply end of the display device, and the fourth resistor R4 is grounded, and the potential of the fourth node M4 is controlled by the conduction of the fourth transistor Q4, and finally the first transistor M1 is controlled to achieve the purpose of inputting the first level signal or the second level signal to the write protection signal input end Wp of the memory 20.

[0058] In some embodiments of the present application, see Figure 4 The control end of the fourth transistor Q4 can directly receive the control signal. When the control end of the fourth transistor Q4 does not receive the control signal, the fourth transistor Q4 is in the on state, and the fourth node M4 is connected to the power supply, so the first transistor M1 can be controlled to be turned on and the memory 20 can be restricted from writing the rewrite data; conversely, when the control end of the fourth transistor Q4 receives the control signal, the fourth transistor Q4 is in the off state, and the potential of the fourth node M4 is the ground terminal potential, so that the first transistor M1 can be controlled to be turned off and the memory 20 can be allowed to write the rewrite data.

[0059] For example, taking the first transistor Q1 and the fourth transistor Q4 as NMOS tubes, when the control signal input terminal Vi receives a high-level signal, the fourth transistor Q4 is in an on state and the first transistor Q1 is in an on state, thereby generating a low-level signal at the first node M1 and causing the write protection signal output terminal Vo to output high and low-level signals, ultimately causing the write protection signal input terminal Wp to receive a low-level signal and restricting the memory 20 from writing rewrite data; conversely, when the control signal input terminal Vi receives a low-level signal, the fourth transistor Q4 is in an off state and the first transistor Q1 is in an off state, thereby generating a high-level signal at the first node M1 and causing the write protection signal output terminal Vo to output a high-level signal, ultimately causing the write protection signal input terminal Wp to receive a high-level signal and causing the memory 20 to write rewrite data.

[0060] In some embodiments of the present application, see Figure 5 , Figure 5 Another schematic diagram of the display device in the embodiment of the present application is shown, wherein the write protection circuit 30 further includes a fifth resistor R5 and a fifth transistor Q5, wherein the first end of the fifth transistor Q5 is electrically connected to the power supply end of the display device, and the second end of the fifth transistor Q5 is electrically connected to the first end of the fifth resistor R5; the second end of the fifth resistor R5 is electrically connected to the ground end of the display device, and the control end of the fifth transistor Q5 is electrically connected to the first end of the fifth resistor R5, that is, the control end of the fifth transistor Q5 is electrically connected to the fifth node M5 between the fifth resistor R5 and the fifth transistor Q5. In other words, the potential of the fifth node M5 can also be controlled by the conduction of the fifth transistor Q5, and then the conduction of the fourth transistor Q4 can be indirectly controlled by the potential of the fifth node M1, and finally the purpose of inputting the first level signal or the second level signal to the write protection signal input end Wp of the memory 20 is achieved.

[0061] In some embodiments of the present application, see Figure 5 , the control end of the fifth transistor Q5 can directly receive the control signal. When the control end of the fifth transistor Q5 does not receive the control signal, the fifth transistor Q5 is in the on state, and the fifth node M5 is connected to the power supply, so the fourth transistor Q4 and the first transistor Q1 can be controlled to be turned on and a low level is generated at the first node M1, thereby limiting the memory 20 from writing rewrite data; conversely, when the control end of the fifth transistor Q5 receives the control signal, the fifth transistor Q5 is in the off state, and the fifth node M4 is grounded, so that the fourth transistor Q4 and the first transistor Q1 can be controlled to be turned off and a high level is generated at the first node M1, so that the memory 20 can write rewrite data.

[0062] For example, taking the first transistor Q1 and the fifth transistor Q5 as NMOS tubes, when the control signal input terminal Vi receives a high-level signal, the fifth transistor Q5 is in an on state and the first transistor Q1 is in an on state, thereby generating a low-level signal at the first node M1 and causing the write protection signal output terminal Vo to output high and low-level signals, ultimately causing the write protection signal input terminal Wp to receive a low-level signal and restricting the memory 20 from writing rewrite data; conversely, when the control signal input terminal Vi receives a low-level signal, the fifth transistor Q5 is in an off state and the first transistor Q1 is in an off state, thereby generating a high-level signal at the first node M1 and causing the write protection signal output terminal Vo to output a high-level signal, ultimately causing the write protection signal input terminal Wp to receive a high-level signal and causing the memory 20 to write rewrite data.

[0063] The above is a detailed introduction to a display device provided in an embodiment of the present application. Specific examples are used herein to illustrate the principle and implementation method of the present invention. The description of the above embodiments is only used to help understand the method and core idea of ​​the present invention. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims

1. A display device, characterized in that: include: Timing controller; A memory having a data writing terminal and a write protection signal input terminal, wherein the data writing terminal is electrically connected to the timing controller; as well as A write protection circuit, comprising a control signal input terminal and a write protection signal output terminal, wherein the write protection signal output terminal is electrically connected to the write protection signal input terminal; Wherein, the write protection circuit includes a first resistor and a first transistor; One end of the first resistor is electrically connected to the power supply end of the display device, and the other end of the first resistor is electrically connected to the first end of the first transistor and the write protection signal output end; The second end of the first transistor is electrically connected to the ground end of the display device, and the control end of the first transistor is electrically connected to the control signal input end.

2. The display device according to claim 1, wherein: When the control signal input terminal receives a high level signal, the first transistor is in a conducting state, so that the write protection signal output terminal outputs a low level signal; When the control signal input terminal receives a low level signal, the first transistor is in a cut-off state, so that the write protection signal output terminal outputs a high level signal.

3. The display device according to claim 1, wherein: The write protection circuit also includes a second resistor and a second transistor; One end of the second resistor is electrically connected to a power supply end of the display device, and the other end of the second resistor is electrically connected to a first end of the second transistor; The second end of the second transistor is electrically connected to the ground end of the display device, the control end of the second transistor is electrically connected to the control signal input end, the control end of the first transistor is electrically connected to the other end of the second resistor, and the control end of the second transistor is electrically connected to the control signal input end.

4. The display device according to claim 3, characterized in that When the control signal input terminal receives a high level signal, the second transistor is in an on state, and the first transistor is in an off state, so that the write protection signal output terminal outputs a high level signal; When the control signal input terminal receives a low level signal, the second transistor is in a cut-off state, and the first transistor is in a turn-on state, so that the write protection signal output terminal outputs a low level signal.

5. The display device according to claim 3, characterized in that The write protection circuit further includes a third transistor; The first end of the third transistor is electrically connected to the other end of the second resistor, the second end of the third transistor is electrically connected to the ground end of the display device, and the control end of the third transistor is electrically connected to the control signal input end.

6. The display device according to claim 5, characterized in that When the control signal input terminal receives a high level signal, the third transistor is in an on state, and the first transistor is in an off state, so that the write protection signal output terminal outputs a high level signal; When the control signal input terminal receives a low level signal, the third transistor is in a cut-off state, and the first transistor is in a turn-on state, so that the write protection signal output terminal outputs a low level signal.

7. The display device according to claim 5, characterized in that The control signal input terminal includes a first input terminal and a second input terminal; The control end of the second transistor is electrically connected to the first input end, and the control end of the third transistor is electrically connected to the second input end.

8. The display device according to claim 1, wherein: The write protection circuit further includes a fourth resistor and a fourth transistor; A first end of the fourth transistor is electrically connected to a power supply end of the display device, and a second end of the fourth transistor is electrically connected to a first end of the fourth resistor; The second end of the fourth resistor is electrically connected to the ground end of the display device, the control end of the first transistor is electrically connected to the first end of the fourth resistor, and the control end of the fourth transistor is electrically connected to the control signal input end.

9. The display device according to claim 8, wherein: When the control signal input terminal receives a high level signal, the fourth transistor is in an on state, and the first transistor is in an on state, so that the write protection signal output terminal outputs a low level signal; When the control signal input terminal receives a low level signal, the fourth transistor is in a cut-off state, and the first transistor is in a cut-off state, so that the write protection signal output terminal outputs a high level signal.

10. The display device according to claim 8, wherein: The write protection circuit further includes a fifth resistor and a fifth transistor; A first end of the fifth transistor is electrically connected to a power supply end of the display device, and a second end of the fifth transistor is electrically connected to a first end of the fifth resistor; The second end of the fifth resistor is electrically connected to the ground end of the display device, the control end of the fifth transistor is electrically connected to the first end of the fifth resistor, and the control end of the fifth transistor is electrically connected to the control signal input end.

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