Semiconductor device

Abstract

The embodiment of the utility model provides a semiconductor device. A semiconductor device includes an integrated circuit die and an encapsulation. The integrated circuit die includes a semiconductor substrate and an interconnect structure connected to the semiconductor substrate, the semiconductor substrate including a first flange and the interconnect structure including a second flange. An encapsulation extends along a first flange of the first semiconductor substrate and a second flange of the first interconnect structure. By extending encapsulations having different widths along non-uniform sidewalls of the integrated circuit die as a clip, the likelihood of interface delamination in a packaging process is reduced and more efficient bonding between top and bottom integrated circuit die may be achieved.

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor device, and more particularly to a semiconductor device including an integrated circuit die with uneven sidewalls. Background Art

[0002] Semiconductor devices and integrated circuits used in various electronic applications are usually made from semiconductor wafers. The integrated circuit (IC) die of the wafer can be processed and packaged with other electronic devices at the wafer level, and various technologies have been developed for wafer-level packaging. In addition, for multi-die packages, the arrangement of the IC die and the packaging technology affect the reliability of the packaged product. Utility Model Content

[0003] An embodiment of the utility model provides a semiconductor device including a first integrated circuit die and an encapsulation body. The first integrated circuit die includes a first semiconductor substrate and a first internal connection structure, the first semiconductor substrate includes a first flange, the first internal connection structure is connected to the first semiconductor substrate, and the first internal connection structure includes a second flange. The encapsulation body extends along the first flange of the first semiconductor substrate and the second flange of the first internal connection structure.

[0004] Based on the above, the semiconductor wafer is singulated by multiple recess processes to obtain the top integrated circuit die with uneven sidewalls. By allowing the encapsulation body with different widths to extend along the uneven sidewalls of each top integrated circuit die as a clamp, the possibility of interface delamination in the packaging process is reduced and a more effective bonding between the top integrated circuit die and the bottom integrated circuit die can be achieved. In this way, defects at the bonding interface are prevented, thereby improving the reliability of the semiconductor device.

[0005] In order to make the above features and advantages of the embodiments of the present invention more obvious and easy to understand, embodiments are specifically cited below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figures 1 to 8 Schematic diagram illustrating intermediate steps in a process for forming a semiconductor device in accordance with some embodiments.

[0007] Fig. 9 and 10 Schematic diagram illustrating intermediate steps in a process for forming a semiconductor device in accordance with some embodiments.

[0008] Fig.11 and 12 Schematic diagram illustrating intermediate steps in a process for forming a semiconductor device in accordance with some embodiments.

[0009] Fig.13 A schematic cross-sectional view of a semiconductor package according to some embodiments is shown.

[0010] Description of Reference Numerals

[0011] 10, 20, 30: semiconductor device; 11: first recess process; 11R, 11R': first recess; 12: second recess process; 12R: second recess; 13, 23, 33: third recess process; 13R, 23R, 33R: third recess; 40: semiconductor package; 50, 60, 70: top IC die; 50a, 502a: active surface; 50b, 92b, 502b: back surface; 50s, 502_1s, 502_2s, 504_1s, 504_2s, 801s, 802s, 5021SG, 5022SD, 5022SE, 5023SE: sidewall; 60s: uneven sidewall; 60sc: curved portion; 80, 80', 80 0”: enclosure; 80A: insulating enclosure; 80_1, 80_1', 80_1", 502_1, 504_1, 5021': first part; 80_1w, 80_1w', 80_1w", 80_2w, 80_2w", 80_3w, 80_3w", 941BW, 5021w', 5022W, 5022W", 5023w', 5041BW, W1, W1', W1", W2, W3, W3', SLW1, SLW1': width; 80_2, 80_2", 502_2, 504_2, 5022, 5022', 5022": second part; 80_3, 80_3", 5023': third part; 80_4: Fourth part; 80s, 90s: outer side wall; 80t, 90t, 5042Ds: upper surface; 90, 100: bottom IC die; 92, 502, 502', 502": semiconductor substrate; 92a, 501a: front surface; 94, 504: internal connection structure; 94B, 504B: bonding layer; 94m: part; 95: substrate through hole / TSV; 98: under bump metal / UBM; 99: conductive terminal; 150, 414: redistribution structure; 401, 402, 404: tape; 403, 405: frame; 410: lower package component; 411: die attach film; 412: insulation through hole / TIV; 413: protective layer; 415: first conductive terminal; 416: first Two conductive terminals; 417: electrical device; 420: upper package component; 421: substrate; 422: semiconductor die; 423: bonding wire; 424: molding layer; 501, 501', 501": semiconductor wafer; 502L, 502L', 502L", 504L: flange; 502SP, 5042SG, 5042ST: inner sidewall / sidewall; 502W, 502W', 504W, 504W': lateral dimension; 502b', 502b'": thinned rear surface; 932: backside dielectric layer; 941, 5041: conductive pattern; 941B, 5041B: bonding conductive feature; 941Bt, 942Bt, 5041Bt, 5042Bt: top surface;942, 4142, 5042: dielectric layer; 942B: bonding dielectric layer; 4141: conductive layer; 4171: conductive contact; 4181: first bottom filler; 4182: second bottom filler; 4212: conductive feature; 5041D: dummy feature; 5042B: first dielectric layer; 5042C: second dielectric layer; 5042D: third dielectric layer; 5042E: fourth dielectric layer; 5042P: dielectric protrusion; IF1: interface; SL, SL1, SL1': scribe line; TH1, TH2: thickness; X, Y: axis. ; DETAILED DESCRIPTION

[0012] The following disclosure provides many different embodiments or examples for implementing different features of the present disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to limit the scope of the present disclosure. For example, in the following description, a first feature is formed "above" or "on" a second feature, which may include an embodiment in which the first feature and the second feature are formed to be in direct contact, and may also include an embodiment in which an additional feature is formed between the first feature and the second feature so that the first feature and the second feature are not in direct contact. In addition, the present disclosure may reuse component numbers and / or letters in various examples. Such repetition is for the purpose of simplifying and clearly describing the present disclosure, rather than for defining the relationship between various embodiments and / or configurations.

[0013] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one component or feature to another (other) component or feature as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be in other orientations (rotated 90 degrees or at other orientations) and the spatially relative descriptors used therein may be interpreted in a similar manner.

[0014] Figures 1 to 8 Schematic diagram showing an intermediate step in a process for forming a semiconductor device according to some embodiments. According to some embodiments, Figure 1-5 is a schematic diagram of various stages of manufacturing an upper integrated circuit (IC) die 50, Figure 6-8 is a schematic diagram of various stages of manufacturing the semiconductor device 10. Please note that Figure 2 According to some embodiments Figure 1 Schematic top view of the structure shown.

[0015] Reference Figure 1, a semiconductor wafer 501 is provided. The semiconductor wafer 501 may include a plurality of die regions, which will be separated by sawing lines SL in a subsequently performed singulation process to form individual top IC dies. The semiconductor wafer 501 may provide a thickness TH1 of more than 700 μm, for example, about 775 μm. The semiconductor wafer 501 includes a semiconductor substrate 502, such as doped or undoped silicon or an active layer of a semiconductor-on-insulator (SOI) substrate. The semiconductor substrate 502 may include other semiconductor materials, such as germanium, compound semiconductors (including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide), alloy semiconductors (including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and / or GaInAsP) or combinations thereof. Other substrates, such as multilayer or gradient substrates, may also be used. The semiconductor substrate 502 may have an active surface 502a (for example Figure 1 The upwardly facing surface in the middle) and the rear surface 502b (e.g. Figure 1 A device (not shown separately) may be formed at the active surface 502a of the semiconductor substrate 502. The device may be an active device (eg, a transistor, a diode, etc.) or a passive device (eg, a capacitor, a resistor, etc.).

[0016] The semiconductor wafer 501 may include an internal wiring structure 504 formed on an active surface 502a of a semiconductor substrate 502 and interconnected with a device to form an integrated circuit. For example, the internal wiring structure 504 is composed of a layer of a conductive pattern 5041 embedded in a dielectric layer 5042. The conductive pattern 5041 including wires, conductive pads and vias may be formed of a suitable conductive material, such as copper, tungsten, aluminum, silver, gold, combinations thereof, etc. The bottom layer of the conductive pattern 5041 may be in physical and electrical contact with the device at the active surface 502a. The top layer of the conductive pattern 5041 may include a bonding conductive feature 5041B for further electrical connection. The bonding conductive feature 5041B may be a bonding pad, a bonding via, a combination thereof, etc. In some embodiments, the conductive pattern 5041 includes one or more layers of dummy features 5041D electrically floating in the internal wiring structure 504. For example, the conductive pattern 5041 electrically coupled with the bonding conductive feature 5041B to form a functional circuit is substantially formed outside the exclusion zone (e.g., the scribe line SL), while the dummy feature 5041D is formed within the exclusion zone. The dummy feature 5041D can be used as an alignment mark and can be regarded as a sacrificial part at a level that will eventually be removed.

[0017] The dielectric layer 5042 of the interconnect structure 504 may include one or more dielectric materials, including oxides (e.g., silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), tetraethyl orthosilicate (TEOS)-based oxides, etc.), nitrides (e.g., silicon nitride or the like), combinations thereof, etc. In some embodiments, the dielectric layer 5042 includes polyimide, acrylic resin, phenolic resin, benzocyclobutene (BCB), polybenzooxazole (PBO) or other polymer-based dielectric materials. In some embodiments, the dielectric layer 5042 includes a first dielectric layer 5042B, a second dielectric layer 5042C below the first dielectric layer 5042B, a third dielectric layer 5042D below the second dielectric layer 5042C, and a fourth dielectric layer 5042E below the third dielectric layer 5042D. The third dielectric layer 5042D may be an etch stop layer having a material different from the second dielectric layer 5042C above. The first dielectric layer 5042B may be a bonding dielectric layer that laterally covers the bonding conductive feature 5041B. For example, the top surface 5041Bt of the bonding conductive feature 5041B is substantially flush (e.g., coplanar) with the top surface 5042Bt of the bonding dielectric layer 5042B. The bonding conductive feature 5041B and the bonding dielectric layer 5042B may be collectively referred to as a bonding layer 504B. In some embodiments, each uppermost via 5041V includes an upper portion laterally covered by the bonding dielectric layer 5042B and a lower portion laterally covered by the second dielectric layer 5042C.

[0018] Continue to refer to Figure 1 , a first recess process 11 is performed on the semiconductor wafer 501 to form a first recess 11R. For example, the first recess process 11 involves etching a portion of the bonding dielectric layer 5042B and a portion of the second dielectric layer 5042C below the bonding dielectric layer 5042B, resulting in the first recess 11R exposing the top surface of the third dielectric layer 5042D in a touchable manner. The etching can be anisotropic etching or isotropic etching. In some embodiments, the first recess 11R is formed in the cutting street SL1. For example, the first recess 11R is confined within the boundary of the cutting street SL1 and does not extend into the tube core area.

[0019] Reference Figure 2 And refer to Figure 1, in the top view, the cutting lanes (SL1 and SL1') may be distributed parallel to the X-axis direction and / or parallel to the Y-axis direction. In some embodiments, a plurality of cutting lanes SL1 and SL1' are evenly distributed and parallel to each other. In some embodiments, the first recess 11R may be located within the cutting lane SL1 in the Y-axis direction, and the first recess 11R' may be located within the cutting lane SL1' in the X-axis direction. Each first recess (11R / 11R') may refer to a trench of different length and width. The cutting lanes (SL1 and / or SL1') and the first recesses (11R and / or 11R') may include various sizes (e.g., width). In some embodiments, the width W1 of the first recess 11R is smaller than the width SLW1 of the cutting line SL1, and the width W1″ of the first recess 11R′ is smaller than the width SLW1′ of the cutting line SL1′. For example, the width (SLW1 and / or SLW1′) is in a range between approximately 60 μm and 660 μm. The width SLW1 of the cutting line SL1 and the width SLW1′ of the cutting line SL1′ may be substantially the same (or may be different in some embodiments). The width (W1 and / or W1′) may be in a range between approximately 30 μm and 150 μm. The width W1 of the first recess 11R in the Y-axis direction and the width W1′ of the first recess 11R′ in the X-axis direction may be substantially the same (or may be different in some embodiments).

[0020] One or more dummy features 5041D may be disposed within the scribe line (SL1 and / or SL1'). In some embodiments, the dummy features 5041D may be disposed below the first recesses 11R and / or 11R'. Figure 2 In FIG. 5 , the dashed line of the dummy feature 5041D indicates that the dummy feature 5041D covered by the dielectric layer is not exposed in a touchable manner at this stage. It should be noted that Figure 2 A circular dummy feature 5041D is schematically shown, but the dummy feature may alternatively be formed in any desired shape.

[0021] Reference Figure 3 and reference Figure 1Once the first recess process 11 is completed, the resulting structure can be flipped over and the interconnect structure 504 can be attached to the tape 401 for further processing. In some embodiments, a thinning process (e.g., chemical-mechanical polishing (CMP), grinding, etch back, a combination thereof, or the like) is performed on the rear surface 502b of the semiconductor substrate 502. The thinning process may be referred to as a backside grinding process. The tape 401 may be referred to as a grinding tape, which covers the front surface 501a of the semiconductor wafer 501 as a protective layer during thinning. After thinning, the semiconductor wafer 501' may have a thickness TH2 measured from the front surface 501a to the thinned rear surface 502b', wherein the thickness TH2 may be in the range of about 50μm and about 600μm. Thinner wafers allow heat to be dissipated faster, thereby providing a cooler operating die. In an alternative embodiment, the thinning process is skipped.

[0022] Reference Figure 4 and reference Figure 3 Once the thinning process is completed, the tape 401 can be removed from the front surface 501a of the semiconductor wafer 501' by a suitable process (e.g., mechanical stripping, etching, etc.). Next, the resulting structure can be flipped over and the thinned back surface 502b' can be placed on the tape 402 (e.g., dicing tape) supported by the frame 403. Subsequently, a second recess process 12 is performed on the semiconductor wafer 501' to form a semiconductor wafer 501" having a second recess 12R extending from the first recess 11R. In some embodiments, the second recess process 12 involves removing a portion of the third dielectric layer 5042D and a portion of the fourth dielectric layer 5042E below the portion of the third dielectric layer 5042D by, for example, laser grooving or any suitable technique. During the formation of the second recess 12R, the dummy feature 5041D may serve as an alignment mark. During the removal of the dielectric layers (5042D and 5042E), the dummy feature 5041D may also be removed. In some embodiments, during the second recess process 12, a portion of the semiconductor substrate 502 below the portion of the fourth dielectric layer 5042E may be removed. The second recess 12R may not extend completely through the semiconductor substrate 502, and a surface of the semiconductor substrate 502 may be exposed.

[0023] In some embodiments, the second recess process 12 may be exothermic, and the dielectric protrusion 5042P is the result of an exothermic reaction. For example, the second recess process 12 transfers photon energy (e.g., laser) into a target material (e.g., the third dielectric layer 5042D) in the form of thermal energy or photochemical energy, and then removes the target material. The laser treatment used in the second recess process 12 often causes heat to be transferred to the target material, resulting in an affected area, wherein the affected area is on the target material that is not removed but is affected by the heat. The dielectric protrusion 5042P may be produced by the target material in the affected area. For example, the dielectric protrusion 5042P may include at least the chemical elements of the third dielectric layer 5042D. In some embodiments, the dielectric protrusion 5042P is formed on the upper surface 5042Ds of the third dielectric layer 5042D exposed by the first recess 11R. In some embodiments, the dielectric protrusion 5042P is formed at the junction of the inner sidewall of the second dielectric layer 5042C and the upper surface 5042Ds of the third dielectric layer 5042D.

[0024] Continue to refer to Figure 4 , the width W2 of the second recess 12R may be smaller than the width W1 of the first recess 11R directly above the second recess 12R. For example, the difference between the widths (W1 and W2) is about 10 μm, but other values ​​may be used, depending on the process parameters. Figure 1 ) is defined by the inner sidewall 5042ST, and the second recess 12R formed by the second recess process 12 is defined by the inner sidewall 5042SG. The inner sidewall 5042ST may be smoother than the inner sidewall 5042SG. For example, the surface roughness of the inner sidewall 5042ST is less than the surface roughness of the inner sidewall 5042SG.

[0025] Reference Figure 5 and reference Figure 4 Once the second recessing process 12 is completed, the resulting structure can be peeled off the tape 402 and flipped over to be placed on another tape 404 supported by another frame 405 for further processing. For example, the front surface 501a of the semiconductor wafer 501 is attached to the tape 404, and the thinned back surface 502b' is exposed in a touchable manner. Next, the semiconductor wafer 501" can be subjected to the third recessing process 13 to form a third recess 13R connected to the second recess 12R. In some embodiments, the third recessing process 13 is applied to the semiconductor wafer 501" to form a third recess 13R connected to the second recess 12R. Figure 1-2) cuts through the remaining semiconductor substrate 502. The semiconductor wafer 501" can therefore be separated into an array of separated top IC dies 50. The first recess process, the second recess process, and the third recess process can be collectively referred to as a singulation process. For example, the third recess 13R is formed by cutting, which uses any suitable cutting tool (such as a blade, a saw, a grinding disk, or a combination thereof). For example, the cutting tool (not shown) begins by cutting into the thinned back surface 502b'" of the semiconductor wafer 501. When the cutting tool moves downward, since the second recess 12R extends into the semiconductor substrate 502, the cutting tool does not contact the internal connection structure 504. After the third recess process 13, a cleaning (or rinsing) process is optionally performed.

[0026] In some embodiments, the width W3 of the third recess 13R formed by cutting with a blade (or saw) is greater than the width W2 of the second recess 12R formed by laser slotting. For example, the difference between the widths (W3 and W2) is about 10 μm or less, but other values ​​may be used, depending on the process parameters. In some embodiments, the width W3 of the third recess 13R is greater than the width W1 of the first recess 11R formed by etching. The third recess 13R formed by cutting may be defined by an inner sidewall 502SP, and the inner sidewall 502SP may be rougher than the inner sidewall 5042ST defining the first recess 11R. For example, the surface roughness of the inner sidewall 5042ST is less than the surface roughness of the inner sidewall 502SP.

[0027] Continue to refer to Figure 5, each top IC die 50 may include a semiconductor substrate 502 and an interconnect structure 504 connected to the semiconductor substrate 502. The semiconductor substrate 502 may include a first portion 502_1 and a second portion 502_2 interposed between the first portion 502_1 and the interconnect structure 504. The region of the second portion 502_2 protruding from the first portion 502_1 may be considered a flange 502L of the semiconductor substrate 502. The first portion 502_1 may have a lateral dimension (e.g., width) 502W that is smaller than a lateral dimension (e.g., width) 502W′ of the second portion 502_2, so the first portion 502_1 may be a narrow portion and the second portion 502_2 may be a wide portion. The interconnect structure 504 may include a first portion 504_1 connected to the second portion 502_2 of the semiconductor substrate 502 and a second portion 504_2 below the first portion 504_1. The area of ​​the first portion 504_1 protruding from the second portion 504_2 can be considered as a flange 504L of the interconnect structure 504, and the flange 504L is below the flange 502L of the semiconductor substrate 502. The first portion 504_1 can have a lateral dimension (e.g., width) 504W that is greater than the lateral dimension (e.g., width) 504W′ of the second portion 504_2, so the first portion 504_1 can be a wide portion and the second portion 504_2 can be a narrow portion. In some embodiments, the width 504W of the first portion 504_1 of the interconnect structure 504 is substantially equal to the width 502W′ of the second portion 502_1 of the semiconductor substrate 502.

[0028] The dielectric protrusion 5042P may be formed on the flange 504L of the interconnect structure 504, for example, at the interface between the first portion 504_1 and the second portion 504_2 of the interconnect structure 504. The sidewall 5042ST of the second portion 504_2 of the interconnect structure 504 may be smoother than the sidewall 5042SG of the first portion 504_1 of the interconnect structure 504 and the second portion 502_2 of the semiconductor substrate 502. The sidewall 5042ST of the second portion 504_2 of the interconnect structure 504 may be smoother than the sidewall 502SP of the first portion 502_1 of the semiconductor substrate 502.

[0029] Each top IC die 50 may be a logic die (e.g., a central processing unit (CPU), a graphics processing unit (GPU), a system-on-a-chip (SoC), an application processor (AP), a microcontroller, etc.), a memory die (e.g., a dynamic random access memory (DRAM) die, a static random access memory (SRAM) die, etc.), a power management die (e.g., a power management integrated circuit (PMIC) die), a radio frequency (RF) die, a sensor die, a micro-electro-mechanical-system (MEMS) die, a signal processing die (e.g., a digital signal processing (DSP) die), a front-end die (e.g., an analog front-end (AFE) die), etc. or a combination thereof. The top IC dies 50 may be the same or different.

[0030] Other features and processes may also be included. For example, test structures may be included to help verify testing of 3D packages or 3DIC devices. Test structures may include, for example, test pads formed in a redistribution layer or on a substrate that allow testing of the 3D package or 3DIC, the use of probes and / or probe cards, etc. Verification testing may be performed on intermediate structures as well as final structures. In addition, the structures and methods disclosed herein may be used in conjunction with test methods that incorporate intermediate verification of known good dies to increase yield and reduce costs.

[0031] Reference Figure 6 and reference Figure 5Once the formation of the top IC die 50 is completed, one or more top IC dies 50 can be picked up from the tape 404 and placed on the bottom IC die 90. In the illustrated embodiment, two top IC dies 50 are shown bonded to the bottom IC die 90 as an example, and other layouts are also contemplated. For example, the top IC die 50 is arranged in an array structure of rows and columns on the bottom IC die 90. The bottom IC die 90 can be a logic die (e.g., CPU, GPU, SoC, AP, microcontroller, etc.), a memory die (e.g., DRAM die, SRAM die, etc.), a power management die (e.g., PMIC die), an RF die, a sensing die, a MEMS die, a signal processing die (e.g., a DSP die), a front-end die (e.g., an AFE die), etc. or a combination thereof. The bottom IC die 90 may include a semiconductor substrate 92, which may have a front surface 92a and a rear surface 92b opposite to the front surface 92a. The material of the semiconductor substrate 92 may be similar to the semiconductor substrate 502 of the top IC die 50 described in the previous paragraph. A device (not separately shown) may be disposed at the front surface 92a of the semiconductor substrate 92. The device may be an active device (e.g., a transistor, a diode, etc.), a capacitor, a resistor, etc. In an alternative embodiment, the bottom IC die 90 is an interposer die, which may (or may not) include active devices and / or passive devices.

[0032] The bottom IC die 90 may include an interconnect structure 94 disposed on a front surface 92a of a semiconductor substrate 92. The interconnect structure 94 may include a conductive pattern 941 embedded in a dielectric layer 942. The conductive pattern 941 and the dielectric layer 942 may be similar to the conductive pattern 5041 and the dielectric layer 5042 described in the previous paragraph, respectively. In some embodiments, the dielectric layer 942 includes an uppermost dielectric layer as a bonding dielectric layer 942B, and the conductive pattern 941 includes an uppermost conductive pattern as a bonding conductive feature 941B. The bonding conductive feature 941B and the bonding dielectric layer 942B may be collectively referred to as a bonding layer 94B. For example, a top surface 941Bt of the bonding conductive feature 941B is substantially flush (e.g., coplanar) with a top surface 942Bt of the bonding dielectric layer 942B. In some embodiments, a portion 94m of the conductive pattern 941 is disposed at the periphery of the interconnect structure 94 and may serve as an alignment mark during the bonding process, wherein the alignment mark may be electrically floating in the interconnect structure 94.

[0033] The bottom IC die 90 may include a through substrate via (TSV) 95 extending through the semiconductor substrate 92 and electrically coupled to a conductive pattern 941 of the interconnect structure 94. In some embodiments, the bottom IC die 90 includes one or more backside dielectric layers 932 disposed on the rear surface 92b of the semiconductor substrate 92 for protection. In some embodiments, a conductive pattern (not shown) may be formed in the backside dielectric layer 932 and electrically coupled to the TSV 95, wherein the conductive pattern and the backside dielectric layer 932 covering the conductive pattern may be collectively referred to as a backside interconnect structure.

[0034] Continue to refer to Figure 6 The top IC die 50 may be bonded to the bottom IC die 90 by bonding the bonding dielectric layer 5042B and the bonding conductive feature 5041B of each top IC die 50 to the bonding dielectric layer 942B and the bonding conductive feature 941B of the bottom IC die 90, respectively. The bonding dielectric layer 5042B may be directly bonded to the bonding layer 942B by dielectric-to-dielectric bonding, and the bonding conductive feature 5041B may be directly bonded to the bonding conductive feature 941B in a one-to-one manner by metal-to-metal bonding. The bonding may be performed by first pressing the top IC die 50 onto the bottom IC die 90 and then annealing the top IC die 50 and the bottom IC die 90 to increase the bonding strength at the interface IF1. The interface IF1 of each top IC die 50 and the bottom IC die 90 may be substantially flat and may include metal-to-metal bonding and dielectric-to-dielectric bonding. In some embodiments, the interface IF1 also includes metal-to-dielectric bonding. The interface IF1 may not have solder material.

[0035] Still refer to Figure 6 , each bonding conductive feature 941B may have a width 941BW that is less than the width 5041BW of the bonding conductive feature 5041B above. In other embodiments, the width 941BW and the width 5041BW are substantially equal. Alternatively, the width 941BW is greater than the width 5041BW. In some embodiments, the center of each bonding conductive feature 941B is substantially aligned with the center of the bonding conductive feature 5041B above. Alternatively, in a cross-sectional view, the center of each bonding conductive feature 941B is laterally offset from the center of the bonding conductive feature 5041B above.

[0036] Reference Figure 7 and reference Figure 6, the encapsulant 80 may be formed on the bottom IC die 90 to laterally cover each top IC die 50. The encapsulant 80 may include a base material and filler particles in the base material, the base material may be a polymer, resin, epoxy, or the like, and the filler may be particles of a dielectric material, such as SiO2, Al2O3, silicon dioxide, etc. In some embodiments, the encapsulant 80 includes a molding compound or a molding underfill, such as epoxy, resin, or the like, and is formed by compression molding, transfer molding, etc. In some embodiments, the encapsulant 80 includes a dielectric material, such as silicon oxide, PSG, BSG, BPSG, TEOS-based oxide, etc., and is formed by a suitable deposition process, such as CVD, ALD, etc. In some embodiments, the encapsulant 80 does not have a filler. In some embodiments, a layer of encapsulation material is first formed on the upper surface 90t of the bottom IC die 90 to cover the uneven sidewalls 50s and rear surfaces 50b of the respective top IC dies 50, and then a planarization process (e.g., a CMP process, a grinding process, an etch-back process, a combination thereof, etc.) is performed to remove excess portions of the encapsulation material above the rear surfaces 50b of the top IC dies 50 to form an encapsulation body 80 that exposes the rear surfaces 50b of the top IC dies 50 in an accessible manner. In some embodiments, the upper surface 80t of the encapsulation body 80 and the rear surfaces 50b of the top IC dies 50 are substantially flush (e.g., coplanar) within a process variation range.

[0037] Reference Figure 8 and reference Figure 7, under-bump metallization (UBM) 98 may be formed through the backside dielectric layer 932 to electrically couple to the TSV 95, and a conductive terminal 99 may be formed on the UBM 98. As an example of forming the UBM 98, the backside dielectric layer 932 may be patterned to form an opening that exposes the underlying TSV 95 (or a conductive pattern in the backside dielectric layer, if present), and then one or more conductive materials may be formed in the opening of the backside dielectric layer 932 to form the UBM 98. In some embodiments, the conductive terminal 99 includes a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, etc. or a combination thereof. The conductive terminal 99 may be formed by forming a solder layer on the UBM 98 and then reflowing to shape the solder into a desired bump shape. The conductive terminal 99 may be a ball grid array (BGA) connector, a solder ball, a metal column, a controlled collapse chip connection (C4) bump, a micro bump, a bump formed by electroless nickel-electroless palladium-immersion (ENEPIG) technology, etc. The top IC die 50 may be electrically coupled to the conductive terminal 99 through the bottom IC die 90. In some embodiments, Figure 6-8 The processes discussed in are performed using wafer-level processing, while the singulation process may be performed by cutting through the encapsulation body 80 and the underlying bottom IC die 90 to form individual semiconductor devices 10. For example, the outer sidewall 80s of the encapsulation body 80 is substantially aligned with (or adjacent to) the outer sidewall 90s of the bottom IC die 90.

[0038] like Figure 8As shown, the semiconductor device 10 includes a top IC die 50 bonded to a bottom IC die 90 and laterally covered by an encapsulation 80. Each top IC die 50 may include an uneven (or discontinuous) sidewall 50s connected to a back surface 50b and an active (or bonding) surface 50a. For example, a sidewall 502_2s of a second portion 502_2 of a semiconductor substrate 502 protrudes laterally from a sidewall 502_1s of a first portion 502_1 of the semiconductor substrate 502. A sidewall 504_1s of a first portion 504_1 of an inner wiring structure 504 may protrude laterally from a sidewall 504_2s of a second portion 504_2 of the inner wiring structure 504. A portion of the encapsulation 80 between two adjacent top IC dies 50 and extending along the uneven sidewall 50s of the top IC die 50 may have different lateral dimensions (e.g., width). For example, the encapsulation body 80 includes a first portion 80_1 having a width 80_1w, a second portion 80_2 below the first portion 80_1 and having a width 80_2w, and a third portion 80_3 interposed between the second portion 80_2 and the bottom IC die 90 and having a width 80_3w. The width 80_1w is measured between the nearest adjacent sidewalls 502_1s of two adjacent top IC dies 50, the width 80_2w is measured between the nearest adjacent sidewalls 502_2s (or 504_1s) of two adjacent top IC dies 50, and the width 80_3w is measured between the nearest adjacent sidewalls 504_2s of two adjacent top IC dies 50. In some embodiments, the width 80_1w of the first portion 80_1 is greater than the width 80_2w of the second portion 80_2, and the width 80_3w of the third portion 80_3 is greater than the width 80_2w of the second portion 80_2. The difference in width (80_1w and 80_2w) and width (80_2w and 80_3w) creates a flange along the sidewall of each top IC die 50. It is believed that the flange formed along the sidewall of each top IC die 50 reduces the effect of the coefficient of thermal expansion (CTE) mismatch stress between the encapsulation body 80 and the top IC die 50, thereby eliminating interface delamination and improving the reliability of the semiconductor device 10.

[0039] The encapsulant 80 with different widths can be used as a fixture, which is used to compress each top IC die 50 from bonding delamination. It has been observed that due to the CTE mismatch between the top IC die and the encapsulant extending along the vertical sidewalls of each top IC die, delamination occurs at the interface of the top IC die and the bottom IC die during / after the packaging process (e.g., thermal cycling process). Interface delamination causes reliability and yield issues. In the present embodiment, the semiconductor wafer is singulated by multiple recess processes to obtain the top IC die 50 with uneven sidewalls 50s. By allowing the encapsulant 80 with different widths to extend along the uneven sidewalls 50s of each top IC die 50 as a fixture, the possibility of interface delamination in the packaging process is reduced and a more effective bonding between the top IC die and the bottom IC die can be achieved. Defects at the bonding interface are thereby prevented, thereby improving the reliability of the semiconductor device.

[0040] Fig. 9 and 10 Schematic diagram showing an intermediate step in a process for forming a semiconductor device according to some embodiments. Unless otherwise specified, the same reference numerals in the embodiments represent a semiconductor device formed by the same process. Figures 1 to 8 The same components in the illustrated embodiments are described in detail herein, so the process and applicable materials will not be repeated here.

[0041] Reference Fig. 9 , the semiconductor wafer may be singulated by sequentially forming a first recess 11R, a second recess 12R extending from the first recess 11R, and a third recess 23R extending from the second recess 12R. The formation of the first recess 11R and the second recess 12R may be similar to Figures 1 to 4 In the process described in the embodiment, the first recess 11R is defined by the sidewall 5042ST of the interconnect structure 504, and the second recess 12R is defined by the sidewall 5042SG of the interconnect structure 504 and the sidewall 5021SG of the semiconductor substrate 502'. Figure 4After the second recess process 12 described in the above, a third recess process 23 is performed on the semiconductor wafer, wherein the rear surface of the semiconductor wafer remains attached to the tape 402 during the third recess process 23. The third recess process 23 may include etching the remaining semiconductor substrate by, for example, a dry etching process to form a third recess 23R, which is defined by the sidewalls (5022SE and 5023SE) of the semiconductor substrate 502'. In some embodiments, the sidewalls (5022SE and 5023SE) formed by etching may be smoother than the sidewalls (5042SG and 5021SG) formed by laser grooving. After the third recess process 23, the semiconductor wafer may be separated into individual top IC dies 60, wherein each top IC die 60 may include a semiconductor substrate 502' and an internal connection structure 504 on the semiconductor substrate 502'. The singulation method including multiple recess processes may cause the top IC die 60 to have uneven sidewalls 60s.

[0042] In some embodiments, the semiconductor substrate 502' includes a first portion 5021' below the interconnect structure 504 and having a sidewall 5021SG, a second portion 5022' below the first portion 5021' and having a sidewall 5022SE, and a third portion 5023' below the second portion 5022' and having a sidewall 5023SE. The area of ​​the first portion 5021' and the second portion 5022' protruding from the third portion 5023' can be regarded as a flange 502L' of the semiconductor substrate 502', and the flange 502L' is below the flange 504L of the interconnect structure 504. The sidewall 5022SE of the second portion 5022' may be curved due to the etching process. The sidewall 5023SE connected to the sidewall 5022SE may be substantially vertical relative to the sidewall 5022SE. In some embodiments, the width 5021w' of the first portion 5021' is greater than the width 5023w' of the third portion 5023'. In some embodiments, the width of the second portion 5022' may gradually decrease from a side connected to the first portion 5021' toward a side connected to the third portion 5023'.

[0043] Reference Fig.10 and reference Fig. 9 , the top IC die 60 can be coupled to the bottom IC die 90, and then the encapsulation body 80' can be formed on the bottom IC die 90 to laterally cover each top IC die 60. Then the conductive terminals 99 can be formed on the bottom IC die 90 to electrically couple to the top IC die 60. The singulation process is selectively performed to form individual semiconductor devices 20. The process of coupling the top IC die 60 to the bottom IC die 90, forming the encapsulation body 80', and forming the conductive terminals 99 can be similar to Figures 6 to 8 The process described in , therefore, will not be repeated here.

[0044] Continue to refer to Fig.10 And also refer to Figure 8 , Fig.10 The semiconductor device 20 and Figure 8 The difference between the semiconductor devices 10 in the embodiment includes that the uneven sidewalls 60s of each top IC die 60 have a curved portion 60sc. A portion of the encapsulation 80' between two adjacent top IC dies 60 may also include a fourth portion 80_4 vertically interposed between the first portion 80_1 and the second portion 80_2. The fourth portion 80_4 may extend along the curved sidewalls of the adjacent top IC dies 60 and may have a width that gradually changes to conform to the curved portion 60sc. The difference in width results in the generation of a flange along the sidewall of each top IC die 60. The flange formed along the sidewall of each top IC die 60 may result in the encapsulation 80' having portions of different widths as a clamp, and the clamp may compress the top IC die 60 from bonding delamination, thereby improving the reliability of the semiconductor device 20.

[0045] Fig.11 and 12 Schematic diagram of an intermediate step in a process for forming a semiconductor device according to some embodiments. Unless otherwise specified, the same reference numerals in the embodiments refer to devices formed by the same process. Figures 1 to 8 The same components in the illustrated embodiments are described in detail herein, so the process and applicable materials will not be repeated here.

[0046] Reference Fig.11 , the semiconductor wafer may be singulated by sequentially forming a first recess 11R, a second recess 12R extending from the first recess 11R, and a third recess 33R extending from the second recess 12R. The formation of the first recess 11R and the second recess 12R may be similar to Figures 1 to 4 The process described in the embodiment of the present invention, wherein the first recess 11R is defined by the sidewall 5042ST of the interconnect structure 504, and the second recess 12R is defined by the sidewall 5042SG of the interconnect structure 504 and the sidewall 5021SG of the semiconductor substrate 502. In some embodiments, Figure 4After the second recessing process 12 described in , a third recessing process 33 is performed on the semiconductor wafer, wherein during the third recessing process 33, the rear surface of the semiconductor wafer is attached to the tape 402. The third recessing process 33 may include cutting the remaining semiconductor substrate by any suitable cutting tool (e.g., a blade, a saw, etc.) to form a third recess 33R, wherein the third recess 33R is defined by the sidewalls 5022SD of the second portion 5022 of the semiconductor substrate 502'. In some embodiments, the sidewalls 5042ST formed by etching may be smoother than the sidewalls 5022SD formed by cutting / sawing. For example, the lateral dimensions of the cutting tool (not shown) are selected so that the width W3' of the third recess 33R may be smaller than the width W2 of the second recess 12R.

[0047] After the third recess process 33, the semiconductor wafer can be separated into individual top IC dies 70, wherein each top IC die 70 may include a semiconductor substrate 502" and an internal wiring structure 504 above the semiconductor substrate 502". In some embodiments, the semiconductor substrate 502" includes a second portion 5022" below the first portion 5021' and having a sidewall 5022SD. The area of ​​the second portion 5022" protruding from the first portion 5021' can be regarded as a flange 502L" of the semiconductor substrate 502", which is spatially separated from the flange 504L of the internal wiring structure 504 of the first portion 5021' of the semiconductor substrate 502". In some embodiments, a width 5021w' of the first portion 5021' is smaller than a width 5022W" of the second portion 5022" of the semiconductor substrate 502.

[0048] Reference Fig.12 and reference Fig.11 , the top IC die 70 can be coupled to the bottom IC die 90, and then the encapsulation 80" can be formed on the bottom IC die 90 to laterally cover each top IC die 70. Then the conductive terminal 99 can be formed on the bottom IC die 90 to electrically couple to the top IC die 70. The singulation process is selectively performed to form individual semiconductor devices 30. The process of coupling the top IC die 70 to the bottom IC die 90, forming the encapsulation 80", and forming the conductive terminal 99 can be the same as Figures 6 to 8 The process described in is similar and will not be repeated here.

[0049] Continue to refer to Fig.12 And refer to Figure 8 , Fig.12 The semiconductor device 30 and Figure 8The difference between the semiconductor devices 10 in the embodiment includes that each top IC die 70 has a stepped sidewall and a portion of the encapsulation 80" between adjacent top IC dies 70 extends along the stepped sidewall. For example, the portion of the encapsulation 80" between adjacent top IC dies 70 has a first portion 80_1', the width 80_1w' of the first portion 80_1' is smaller than the width 80_2w of the second portion 80_2 below, and the width 80_3w of the third portion 80_3 vertically between the second portion 80_2 and the bottom IC die 90 may be greater than the width 80_2w of the second portion 80_2. The width difference between the width (80_1w' and 80_2w) and the width (80_2w and 80_3w) is caused by the flange along the sidewall of each top IC die 70. It is believed that the encapsulation body 80 ″ having different widths can act as a clamp to compress the adjacent top IC die 70 from bonding delamination, thereby improving the reliability of the semiconductor device 30 .

[0050] Fig.13 Schematic cross-sectional views of semiconductor packages according to some embodiments are shown. Unless otherwise specified, the same reference numerals in the embodiments represent semiconductor packages formed by the same process. Figures 1 to 8 The same components as in the illustrated embodiment. Fig.13 , the semiconductor package 40 may include a lower package component 410 and an upper package component 420 stacked on the lower package component 410 and electrically coupled to the lower package component 410. The lower package component 410 may include at least one top IC die 50 laterally covered by an insulating encapsulation 80A, a through insulating via (TIV) 412 penetrating the insulating encapsulation 80A, and a redistribution structure 414 continuously formed on the top IC die 50, the TIV 412, and below the insulating encapsulation 80A.

[0051] The top IC die 50 with uneven sidewalls 50s may be Figure 5 The IC die described in Fig. 9 or Fig.11 The insulating package 80A may be similar to Figure 6 The encapsulation 80 described in the foregoing may include a molding compound or a molding underfill, such as epoxy resin, resin, etc. The redistribution structure 414 connected to the active surface 50a of the top IC die 50 may include a conductive layer 4141 and a dielectric layer 4142 alternately stacked on each other. The conductive layer 4141 reroutes the electrical signals of the top IC die 50 and extends wider than the wiring area of ​​the top IC die 50, and the redistribution structure 150 may be referred to as a front-side fan-out type redistribution structure.

[0052] Continue to refer to Fig.13 , the TIVs 412 may be arranged in an array to surround the top IC die 50, and a portion of the insulating encapsulant 80A is interposed between the top IC die 50 and the nearest TIV 412. The sidewalls 801s of the portion of the insulating encapsulant 80A connected to the TIVs 412 may be substantially vertical, and the opposing sidewalls 802s of the portion of the insulating encapsulant 80A connected to the uneven sidewalls 50s of the top IC die 50 may be uneven (or discontinuous). For example, the portion of the insulating encapsulant 80A includes a first portion 80_1″ having a width 80_1w″, a second portion 80_2″ below the first portion 80_1″ and having a width 80_2w″, and a third portion 80_3″ below the second portion 80_2″ and having a width 80_3w″. In some embodiments, the width 80_2w" of the second portion 80_2" is smaller than the width 80_1w, and the width 80_3w" of the third portion 80_3" is larger than the width 80_2w". Fig. 9 (or Fig.11 In some embodiments of other top IC die replacements described in ), the portion of the insulating encapsulant may vary according to the contour of the uneven sidewalls of the top IC die and may be similar to that in Fig.10 (or Fig.12 ) described in the encapsulation.

[0053] In some embodiments, a protective layer 413 is formed on the rear surface 50b of the top IC die 50 and the surfaces of the TIV 412 and the insulating encapsulant 80A. In some embodiments, a conductive pattern (not shown) is formed in the protective layer to be physically and electrically coupled to the TIV, and the conductive pattern and the protective layer may be collectively referred to as a backside redistribution structure. A die attaching film (DAF) 411 may be optionally disposed between the rear surface 50b of the top IC die 50 and the protective layer 413 and may be laterally covered by the insulating encapsulant 80A. In some embodiments, the lower package component 410 includes a first conductive terminal 415 formed on the outermost conductive layer 4141 of the redistribution structure 414. In some embodiments, a second conductive terminal 416 is disposed between the lower package component 410 and the upper package component 420, and each second conductive terminal 416 may extend through the protective layer 413 to be in electrical contact with the TIV 412. The top IC die 50 can be electrically coupled to the upper package component 420 through the redistribution structure 414, TIV 412 and second conductive terminals 416. The first conductive terminals 415 and / or the second conductive terminals 416 can be BGA connectors, solder balls, metal pillars, C4 bumps, micro bumps, bumps formed by ENEPIG, etc.

[0054] In some embodiments, the lower package component 410 includes at least one electrical device 417, such as an integrated passive device (IPD), which is electrically coupled to the outermost conductive layer 4141 of the redistribution structure 414 through a conductive contact 4171 (e.g., a solder contact). The conductive contact 4171 may include the same material as the first conductive terminal 415 and / or the second conductive terminal 416. A first underfill 4181 may be formed in a gap between the electrical device 417 and the redistribution structure 414. In some embodiments, a second underfill 4182 is formed in a gap between the upper package component 420 and the lower package component 410 to surround a portion of the second conductive terminal 416 protruding from the protective layer 413.

[0055] Still refer to Fig.13 , the upper package component 420 may include a substrate 421 and one or more semiconductor dies 422 (e.g., memory dies) attached to the substrate 421. The substrate 421 may include silicon, gallium arsenide, SOI, or other suitable semiconductor materials. In some embodiments, the substrate 421 is a multilayer circuit board or may include BT resin, FR-4, ceramic, glass, plastic, tape, film, or other supporting materials. The substrate 421 may include conductive features 4212 (e.g., wires, conductive pads, and vias, not shown separately) formed in / on the substrate 421. The semiconductor die 422 may be electrically coupled to the conductive features 4212 by, for example, bonding wires 423. In some embodiments, the semiconductor die 422 is electrically coupled to the top IC die 50 by the rewiring structure 414, the TIV 412, the second conductive terminal 416, the conductive features 4212 in the substrate 421, and the bonding wires 423. A molding layer 424, which may include epoxy resin, organic polymers, polymers, etc., may be formed on the substrate 421 and encapsulate the semiconductor die 422.

[0056] The lower package assembly 410 may be referred to as an integrated fan-out (InFO) package. In some embodiments, the upper package assembly 420 including the memory die is referred to as a memory package. The semiconductor package 40 may be referred to as an InFO package-on-package (PoP). It should be understood that Fig.13 The semiconductor package 40 shown in the figure is only an example, and the top IC die described here may also be applicable to other packaging configurations, such as a system-on-chip (SoC) package, a chip-on-wafer (CoW) package, a chip-on-wafer-on-substrate (CoWoS) package, etc.

[0057] According to some embodiments, a device includes a first IC die and an encapsulation. The first IC die includes a first semiconductor substrate and a first interconnect structure connected to the first semiconductor substrate. The first semiconductor substrate includes a first flange, and the first interconnect structure includes a second flange. The encapsulation extends along the first flange of the first semiconductor substrate and the second flange of the first interconnect structure.

[0058] In some embodiments, the first flange of the first semiconductor substrate includes a first sidewall and a second sidewall laterally offset from the first sidewall, the second flange of the first interconnect structure includes a third sidewall and a fourth sidewall laterally offset from the third sidewall, and the second sidewall of the first semiconductor substrate is connected to and substantially aligned with the fourth sidewall of the first interconnect structure. In some embodiments, the first flange of the first semiconductor substrate further includes a curved surface connected to the first sidewall and the second sidewall. In some embodiments, the first flange of the first semiconductor substrate includes a first sidewall and a second sidewall laterally offset from the first sidewall, the second flange of the first interconnect structure includes a third sidewall and a fourth sidewall laterally offset from the third sidewall, and the first sidewall of the first semiconductor substrate is connected to and substantially aligned with the fourth sidewall of the first interconnect structure. In some embodiments, the surface roughness of the third sidewall of the first interconnect structure is less than the surface roughness of the fourth sidewall of the first interconnect structure. In some embodiments, a dielectric protrusion is disposed on a surface of the second flange of the first interconnect structure. In some embodiments, the device further comprises a second integrated circuit die connected to the active surface of the first integrated circuit die, wherein the encapsulant is disposed on the second integrated circuit die to laterally cover the first integrated circuit die, and the interface of the active surface of the first integrated circuit die and the second integrated circuit die is substantially flat. In some embodiments, the first conductive feature of the first interconnect structure is bonded to the second conductive feature of the second integrated circuit die, and the first bonding dielectric layer of the first interconnect structure laterally covers the first conductive feature and is bonded to the second bonding dielectric layer of the second integrated circuit die. In some embodiments, the device further comprises a second integrated circuit die, the second integrated circuit die comprising an uneven sidewall and being laterally spaced apart from the first integrated circuit die by the encapsulant. In some embodiments, the second integrated circuit die comprises a second semiconductor substrate and a second interconnect structure, the second semiconductor substrate comprising a first sidewall and a second sidewall laterally offset from the first sidewall, a second interconnect structure connected to the second semiconductor substrate, the second interconnect structure comprising a third sidewall and a fourth sidewall laterally offset from the third sidewall. In some embodiments, the device also includes an insulating via that extends through the encapsulation and is laterally spaced from the first integrated circuit die by a portion of the encapsulation, wherein the portion of the encapsulation includes an uneven side connected to the first integrated circuit die and a substantially vertical side connected to the insulating via.

[0059] According to some alternative embodiments, a device includes an IC die and an encapsulation, the IC die including sidewalls and the encapsulation connected to the sidewalls of the IC die. The encapsulation includes a first portion, a second portion below the first portion, and a third portion below the first portion, wherein a width of the second portion is different from a width of the first portion and a width of the third portion.

[0060] In some embodiments, the width of the second portion is less than the width of the third portion. In some embodiments, the width of the second portion is greater than the width of the first portion. In some embodiments, the sidewall of the integrated circuit die includes a first sidewall connected to the third portion of the encapsulation and a second sidewall connected to the second portion of the encapsulation and protruding laterally from the first sidewall, wherein the surface roughness of the first sidewall is less than the surface roughness of the second sidewall.

[0061] According to some alternative embodiments, a method includes: forming a first recess having a first width on a semiconductor wafer; forming a second recess extending from the first recess on the semiconductor wafer, wherein a second width of the second recess is smaller than a first width in the first recess; forming a third recess connected to the second recess to cut through the semiconductor wafer to form an IC die having an uneven sidewall, wherein a third width of the third recess is different from the second width of the second recess; and forming an encapsulation to cover the uneven sidewall of the IC die.

[0062] In some embodiments, forming the first recess includes removing an upper portion of an interconnect structure of the semiconductor wafer within a scribe line of the semiconductor wafer, and forming the second recess includes removing a lower portion of the interconnect structure and an upper portion of a semiconductor substrate of the semiconductor wafer below the lower portion of the interconnect structure. In some embodiments, forming the third recess includes etching a lower portion of the semiconductor substrate from a front side of the semiconductor wafer, the interconnect structure being formed on the front side of the semiconductor wafer. In some embodiments, forming the third recess includes cutting a lower portion of the semiconductor substrate from the front side of the semiconductor wafer, the interconnect structure being formed on the front side of the semiconductor wafer, wherein the third width of the third recess is less than the second width of the second recess. In some embodiments, forming the third recess includes cutting the semiconductor substrate of the semiconductor wafer from a rear surface of the semiconductor wafer, wherein the third width of the third recess is greater than the second width of the second recess.

[0063] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the embodiments of the utility model, rather than to limit them. Although the embodiments of the utility model are described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents. However, these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the embodiments of the utility model.

Claims

1. A semiconductor device, characterized in that: include: A first integrated circuit die comprising: A first semiconductor substrate including a first flange; and a first interconnect structure connected to the first semiconductor substrate, the first interconnect structure comprising a second flange; and The encapsulation body extends along the first flange of the first semiconductor substrate and the second flange of the first interconnect structure.

2. The semiconductor device according to claim 1, wherein: The first flange of the first semiconductor substrate includes a first sidewall and a second sidewall laterally offset from the first sidewall, the second flange of the first internal connection structure includes a third sidewall and a fourth sidewall laterally offset from the third sidewall, and the second sidewall of the first semiconductor substrate is connected to and aligned with the fourth sidewall of the first internal connection structure.

3. The semiconductor device according to claim 1, wherein: The first flange of the first semiconductor substrate includes a first sidewall and a second sidewall laterally offset from the first sidewall, the second flange of the first internal connection structure includes a third sidewall and a fourth sidewall laterally offset from the third sidewall, and the first sidewall of the first semiconductor substrate is connected and aligned with the fourth sidewall of the first internal connection structure.

4. The semiconductor device according to claim 1, wherein: The dielectric protrusion is disposed on the surface of the second flange of the first inner connecting structure.

5. The semiconductor device according to claim 1, wherein: Also includes: A second integrated circuit die is connected to the active surface of the first integrated circuit die, wherein the encapsulant is disposed on the second integrated circuit die to laterally cover the first integrated circuit die, and an interface between the active surface of the first integrated circuit die and the second integrated circuit die is flat.

6. The semiconductor device according to claim 1, wherein: Also includes: A second integrated circuit die includes non-uniform sidewalls and is laterally spaced apart from the first integrated circuit die by the encapsulation.

7. The semiconductor device according to claim 1, wherein: Also includes: An insulating through-via extends through the encapsulation and is laterally spaced apart from the first integrated circuit die by a portion of the encapsulation, wherein the portion of the encapsulation includes an uneven side connected to the first integrated circuit die and a vertical side connected to the insulating through-via.

8. The semiconductor device according to claim 1, wherein: in: The encapsulation body includes a first portion, a second portion below the first portion, and a third portion below the first portion, wherein a width of the second portion is different from widths of the first portion and the third portion.

9. The semiconductor device according to claim 8, wherein: The width of the second portion is smaller than the width of the third portion.

10. The semiconductor device according to claim 8, wherein: The first integrated circuit die comprises: a first side wall connected to the third portion of the enclosure; and A second side wall is connected to the second portion of the enclosure.

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