Chip packaging structure

Abstract

The utility model provides a chip packaging structure. The chip packaging structure comprises a substrate, a chip, a heat dissipation cover and a heat conduction structure. Wherein the heat conduction structure comprises a PI layer and a metal connection structure, the PI layer is laid on the back face of the chip, the bottom end of the metal connection structure is connected with the PI layer, the top end of the metal connection structure is connected with the heat dissipation cover, and a complete heat conduction path is formed. The metal connection structure comprises a plurality of metal columns which are arranged at intervals. The heat conduction structure not only has excellent heat conductivity, but also can quickly conduct heat generated by the chip to the heat dissipation cover, so that the temperature of the chip is effectively reduced. Meanwhile, the flexible packaging material has good flexibility and high deformation capacity, the warping phenomenon caused by different thermal expansion coefficients of materials is effectively reduced, displacement caused by warping can be compensated to a certain degree, and the packaging reliability is ensured. In addition, the heat conduction structure is low in production cost and simple in process, large-scale production is easy to achieve, high-density integration is supported, and the defects of a traditional indium sheet process can be overcome.

Description

Technical Field

[0001] The utility model belongs to the technical field of semiconductor packaging and relates to a chip packaging structure. Background Art

[0002] In the field of semiconductor packaging technology, flip chip electronic packaging technology has become the mainstream packaging form in the market due to its high performance and high-density integration, accounting for about 60-70% of the IC packaging market share. With the advancement of technology, high-end flip chip packaging is increasingly adopting advanced packaging technologies such as 2.5D and 3D to integrate multiple simple chips with different functions into a high-performance composite chip. This integration trend puts higher requirements on the heat dissipation of products. Among them, the indium sheet process has been widely used in chip packaging due to its excellent heat dissipation performance. However, the melting point of metallic indium is low (156.61°C). During the packaging process, the reflow temperature of tin metal may be as high as about 260°C, which will cause the indium metal to boil, flow and splash, and even overflow to components such as capacitors, causing their electrical performance to fail. In addition, the overflow of indium metal may also lead to insufficient coverage, further reducing the heat dissipation effect.

[0003] Therefore, how to provide a chip packaging structure to solve the problems in the prior art such as insufficient coverage, failure of component electrical performance and reduced heat dissipation effect caused by the easy boiling, flow splashing and overflow of indium metal at high temperature has become an important technical problem that needs to be urgently solved by technical personnel in this field.

[0004] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the present application and facilitating the understanding of those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because they are described in the background technology section of the present application. Utility Model Content

[0005] In view of the shortcomings of the prior art described above, the purpose of the present invention is to provide a chip packaging structure for solving the problems in the prior art of insufficient coverage, failure of electrical performance of components and reduced heat dissipation effect due to the fact that indium metal is easy to boil, flow splash and overflow at high temperature.

[0006] In order to achieve the above-mentioned object and other related objects, the utility model provides a chip packaging structure, including:

[0007] a substrate having a first surface and a second surface opposite to each other;

[0008] A chip is flip-chip bonded on the first surface of the substrate;

[0009] A heat dissipation cover is fixed on the first surface of the substrate, a cavity is formed between the heat dissipation cover and the substrate, and the chip is located in the cavity;

[0010] A heat conduction structure is located in the cavity, the heat conduction structure includes a PI layer and a metal connection structure, the PI layer is laid on the back of the chip, the bottom end of the metal connection structure is connected to the PI layer, the top end of the metal connection structure is connected to the heat dissipation cover, and the metal connection structure includes a plurality of metal columns arranged at intervals.

[0011] Optionally, the metal connection structure further includes a plurality of pads, each of which is connected to at least one metal column.

[0012] Optionally, the pad is located on the upper surface of the PI layer.

[0013] Optionally, the PI layer has a plurality of through holes whose bottoms expose the back side of the chip, and the plurality of pads are arranged in the plurality of through holes in a one-to-one correspondence.

[0014] Optionally, a plurality of solder bumps are formed on a side of the heat dissipation cover facing the back side of the chip, the plurality of solder bumps correspond to the plurality of metal pillars one by one, and each of the metal pillars is connected to the heat dissipation cover via a solder bump.

[0015] Optionally, top ends of the plurality of metal pillars are located on the same horizontal plane.

[0016] Optionally, a plurality of solder balls are disposed on the second surface of the substrate.

[0017] Optionally, it also includes components, which are fixedly connected to the first surface and / or the second surface of the substrate; wherein, when the components are located on the first surface of the substrate, the components are located in the cavity and are spaced a preset distance from the chip.

[0018] Optionally, the heat dissipation cover is fixed to the first surface of the substrate by gluing or welding.

[0019] Optionally, the chip includes a single chip or a chip assembly.

[0020] As described above, the chip packaging structure of the utility model includes a substrate, a chip, a heat dissipation cover and a heat conduction structure. Among them, the heat conduction structure includes a PI layer and a metal connection structure, the PI layer is laid on the back of the chip, and the bottom end of the metal connection structure is connected to the PI layer, and the top end is connected to the heat dissipation cover, forming a complete heat conduction path. Among them, the metal connection structure includes a plurality of metal columns arranged at intervals. The heat conduction structure not only has excellent thermal conductivity, but can also quickly conduct the heat generated by the chip to the heat dissipation cover, effectively reducing the chip temperature. At the same time, it also has good flexibility and strong deformation ability, effectively reducing the warping phenomenon caused by different thermal expansion coefficients of materials, and can compensate for the displacement caused by warping to a certain extent, ensuring the reliability of the package. In addition, the heat conduction structure has low production cost, simple process, easy to achieve large-scale production, supports high-density integration, and can avoid the defects of traditional indium sheet processes. The chip packaging structure of the utility model shows significant advantages in improving heat dissipation efficiency, enhancing structural stability, improving packaging density and simplifying manufacturing processes, fully meeting the market's urgent demand for high-performance chip packaging technology. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 It is a schematic cross-sectional structure diagram of the chip packaging structure of the present invention in the first embodiment.

[0022] Figure 2 Shown is a top view of the heat conduction structure in the chip packaging structure of the present invention in the first embodiment.

[0023] Figure 3 It is a schematic cross-sectional structure diagram of the chip packaging structure of the present invention in the second embodiment.

[0024] Component number description

[0025] 100 substrates

[0026] 200 chips

[0027] 300 Heatsink Cover

[0028] 400 heat conduction structure

[0029] 401 PI layer

[0030] 402 Metal connection structure

[0031] 4021 Pad

[0032] 4022 Metal Column

[0033] 500 Cavity

[0034] 600 solder balls

[0035] 700 components

[0036] 800 Adhesive layer DETAILED DESCRIPTION

[0037] The following is an explanation of the implementation of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific implementations, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0038] See also Figures 1 to 3 It should be noted that the illustrations provided in this embodiment are only used to schematically illustrate the basic concept of the utility model, and the drawings only show the components related to the utility model rather than the number, shape and size of the components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0039] Embodiment 1

[0040] This embodiment provides a chip packaging structure. Figure 1 , which is a schematic cross-sectional structure diagram of the chip packaging structure, includes a substrate 100, a chip 200, a heat dissipation cover 300 and a heat conduction structure 400, wherein the substrate 100 has a first surface and a second surface opposite to each other; the chip 200 is flip-chip bonded to the first surface of the substrate 100; the heat dissipation cover 300 is fixed on the first surface of the substrate 100, a cavity 500 is formed between the heat dissipation cover 300 and the substrate 100, and the chip 200 is located in the cavity 500; the heat conduction structure 400 is located in the cavity 500, and the heat conduction structure 400 includes a PI layer 401 and a metal connection structure 402, the PI layer 401 is laid on the back side of the chip 200, the bottom end of the metal connection structure 402 is connected to the PI layer 401, the top end of the metal connection structure 402 is connected to the heat dissipation cover 300, and the metal connection structure 402 includes a plurality of metal pillars 4022 arranged at intervals.

[0041] Specifically, the substrate 100 includes a printed circuit board (PCB) with metal wiring inside, a through silicon via (TSV) with metal pillars inside, or a re-distribution layer (RDL) with metal wiring inside. In this embodiment, the substrate 100 adopts a printed circuit board with metal wiring inside, but the type of the substrate 100 is not limited thereto and can be selected according to needs.

[0042] As an example, the chip 200 includes a single chip or a chip assembly. The chip assembly can be a horizontal assembly or a vertical assembly, that is, multiple bare chips are arranged side by side on the same horizontal plane or vertically stacked to form a multi-layer structure.

[0043] As an example, the chip 200 is flip-chip bonded to the first surface of the substrate 100 through an electrical connection structure, and the pads (not shown) of the chip 200 are directly electrically connected to the pads (not shown) on the first surface of the substrate 100 through the electrical connection structure, and the electrical connection structure includes solder balls or other suitable electrical connection materials.

[0044] Furthermore, a bottom filling layer (not shown) is formed between the chip 200 and the substrate 100, and the bottom filling layer is used to strengthen the connection between the chip 200 and the substrate 100, improve the structural stability, and provide additional protection to prevent the chip 200 from being affected by environmental factors such as moisture and dust.

[0045] As an example, the material of the heat dissipation cover 300 includes aluminum, iron, copper or an alloy containing any of the above metals.

[0046] As an example, the heat dissipation cover 300 is fixed on the first surface of the substrate 100 by gluing or welding.

[0047] Specifically, in one example, an adhesive layer 800 is formed between the heat dissipation cover 300 and the substrate 100. The adhesive layer 800 is located on the first surface of the substrate 100 and is used to bond the heat dissipation cover 300 and the substrate 100. The material of the adhesive layer 800 includes any one of epoxy resin, silicone rubber and polyurethane.

[0048] Specifically, in another example, a welding layer is formed between the heat dissipation cover 300 and the substrate 100, and the welding layer is located on the first surface of the substrate 100, and is used to support and further fix the heat dissipation cover 300. The material of the welding layer includes copper, silver, gold or other suitable solders to ensure good thermal conduction and mechanical connection between the heat dissipation cover 300 and the substrate 100.

[0049] In this embodiment, an adhesive layer 800 is formed between the heat dissipation cover 300 and the substrate 100 to provide the required bonding strength and thermal conductivity.

[0050] Specifically, the method for forming the PI layer 401 includes chemical vapor deposition, coating, spraying, photocuring or other suitable methods. The PI layer 401 has good chemical stability and corrosion resistance, and has a thermal expansion coefficient similar to that of the material of the chip 200, which helps to reduce stress and thermal damage risks during thermal cycling. Moreover, the processing technology of the PI layer 401 is simple and low in cost, and is suitable for mass production.

[0051] Specifically, in one example, the PI layer 401 further includes a thermally conductive filler, which is evenly dispersed in the PI layer 401 . The thermally conductive filler includes any one of a metal filler, a ceramic filler, a carbon-based material, and a polymer-based material to achieve an optimal heat conduction effect.

[0052] As an example, the material of the metal pillar 4022 includes copper, aluminum, nickel, gold, silver, titanium, tantalum or other suitable metal materials.

[0053] Specifically, the metal pillar 4022 is formed by chemical vapor deposition, physical vapor deposition, electroplating, chemical plating, evaporation, atomic layer deposition, magnetron sputtering or other suitable methods. The metal pillar 4022 can effectively promote the rapid transfer and dispersion of heat, achieve efficient thermal management, and significantly improve the heat dissipation efficiency of the packaging structure. In addition, the high mechanical strength of the metal pillar 4022 helps to ensure that the packaging structure remains stable in the face of stress such as thermal expansion and vibration caused by temperature changes, reduce the risk of damage caused by stress, and improve the overall reliability and durability of the packaging structure.

[0054] As an example, the metal connection structure 402 further includes a plurality of pads 4021 , and each of the pads 4021 is connected to at least one metal pillar 4022 .

[0055] As an example, the pad 4021 is located on the upper surface of the PI layer 401 .

[0056] Specifically, the pad 4021 includes a metal layer or multiple metal layers, and the material of the metal layer includes any one or a combination of two or more of copper, aluminum, nickel, gold, silver, titanium and tantalum.

[0057] Specifically, the method for forming the pad 4021 includes chemical vapor deposition, physical vapor deposition, electroplating, chemical plating, evaporation, atomic layer deposition, magnetron sputtering or other suitable methods. In this embodiment, the pad 4021 is formed by electroplating.

[0058] Specifically, under the condition of ensuring the performance of the heat conduction structure 400, the number of layers, thickness and material of the metal layer in the pad 4021 can be selected according to actual conditions. Preferably, in this embodiment, the pad 4021 includes a metal layer, and the material of the metal layer is copper.

[0059] As an example, the shape of the pad 4021 includes any one of a square, a circle and a polygon. In this embodiment, the shape of the pad 4021 is preferably a square, but the shape of the pad 4021 is not limited thereto and can be selected as needed.

[0060] As an example, the material of the metal pillar 4022 is the same as the material of the pad 4021 .

[0061] Specifically, the metal column 4022 is a copper column, and the pad 4021 is a copper pad. In this embodiment, the pad 4021 and the metal column 4022, which are made of the same metal material, have a strong bonding force, and can effectively enhance the stability and reliability of the overall packaging structure. At the same time, since the selected copper material has excellent thermal conductivity, an efficient heat conduction path is formed between the pad 4021 and the metal column 4022, which significantly improves the heat dissipation efficiency. In addition, the cost of copper material is relatively low, which not only helps to reduce the production cost of the overall packaging structure, but also makes the structure have a higher cost performance while ensuring performance.

[0062] Specifically, in this embodiment, heat is transferred from the PI layer 401 located on the back side of the chip 200 to the pad 4021, and then further transferred to the metal column 4022 through the pad 4021, and finally dissipated to the external environment through the heat dissipation cover 300 connected to the metal column 4022, thereby achieving efficient heat dissipation effect.

[0063] As an example, top ends of the plurality of metal pillars 4022 are located on the same horizontal plane.

[0064] Specifically, in this embodiment, the top ends of the plurality of metal pillars 4022 are located on the same horizontal plane, which helps to form a flat contact surface, improves the stability of the overall structure, and helps to promote a more uniform distribution of heat on the heat dissipation cover 300 to avoid local overheating. At the same time, it helps to reduce stress concentration and further improve the reliability and durability of the packaging structure.

[0065] As an example, a plurality of solder bumps are formed on one side of the heat dissipation cover 300 facing the back side of the chip 200 , and the plurality of solder bumps correspond one-to-one to the plurality of metal pillars 4022 , and each of the metal pillars 4022 is connected to the heat dissipation cover 300 via a solder bump.

[0066] Specifically, the material of the solder bump includes any one of tin, lead and silver, or an alloy containing any one of the above solder metals. In this embodiment, the material of the solder bump is preferably tin.

[0067] In another example, a metal material layer is first formed on the side of the heat dissipation cover 300 facing the back side of the chip 200, and then a plurality of solder bumps are formed on the metal material layer. The plurality of solder bumps are located on the metal material layer and correspond one-to-one to the plurality of metal pillars 4022. Each of the metal pillars 4022 is connected to the metal material layer and the heat dissipation cover 300 through a solder bump.

[0068] Specifically, the material of the metal material layer includes any one of copper, aluminum, silver, nickel and gold. The metal material layer provides additional protection for the heat dissipation cover 300, not only to resist degradation caused by environmental factors such as humidity or corrosive gases, but also to help the heat dissipation cover 300 to expand and contract more evenly when the temperature fluctuates, thereby reducing thermal stress and improving the structural stability and durability of the heat dissipation cover 300.

[0069] As an example, a plurality of solder balls 600 are disposed on the second surface of the substrate 100 , and the solder balls 600 are fixedly connected to the substrate 100 .

[0070] As an example, the chip 200 packaging structure also includes a component 700, which is fixedly connected to the first surface and / or the second surface of the substrate 100; wherein, when the component 700 is located on the first surface of the substrate 100, the component 700 is located in the cavity 500 and is spaced a preset distance from the chip 200.

[0071] Specifically, the component 700 is fixed to the first surface and / or the second surface of the substrate 100 by a surface mounting process.

[0072] As an example, the component 700 includes at least one of a resistor, an inductor and a capacitor.

[0073] Please see again Figure 2 , which is a top view of the heat conduction structure 400 , wherein the pad 4021 is located above the PI layer 401 , the pad 4021 is a square pad 4021 , and a plurality of metal pillars 4022 are connected above each of the pads 4021 .

[0074] Embodiment 2

[0075] This embodiment provides a chip packaging structure. Figure 3 The difference between this embodiment and the first embodiment is that: the PI layer 401 has a plurality of through holes with the bottom exposing the back side of the chip 200, and the plurality of pads 4021 are arranged in the plurality of through holes in a one-to-one correspondence.

[0076] Specifically, in this embodiment, heat is transferred from the pad 4021 disposed in the PI layer 401 to the metal column 4022, and then dissipated to the external environment through the heat dissipation cover 300 connected to the metal column 4022. In addition, in this embodiment, the PI layer 401 located on the back of the chip 200 also helps to dissipate heat.

[0077] As an example, the shape of the through hole includes any one of a square through hole, a circular through hole and a polygonal through hole.

[0078] Specifically, the shape of the through hole is the same as the shape of the pad 4021. In this embodiment, the through hole is preferably a square through hole.

[0079] In summary, the utility model provides a chip packaging structure, including a substrate, a chip, a heat dissipation cover and a heat conduction structure. Among them, the heat conduction structure includes a PI layer and a metal connection structure, the PI layer is laid on the back of the chip, and the bottom end of the metal connection structure is connected to the PI layer, and the top end is connected to the heat dissipation cover, forming a complete heat conduction path. Among them, the metal connection structure includes a plurality of metal columns arranged at intervals. The heat conduction structure not only has excellent thermal conductivity, but can also quickly conduct the heat generated by the chip to the heat dissipation cover, effectively reducing the chip temperature. At the same time, it also has good flexibility and strong deformation ability, effectively reducing the warping phenomenon caused by different thermal expansion coefficients of materials, and can compensate for the displacement caused by warping to a certain extent, ensuring the reliability of the package. In addition, the heat conduction structure has low production cost, simple process, easy to achieve large-scale production, supports high-density integration, and can avoid the defects of traditional indium sheet processes. The chip packaging structure of the utility model shows significant advantages in improving heat dissipation efficiency, enhancing structural stability, improving packaging density and simplifying manufacturing processes, fully meeting the market's urgent demand for high-performance chip packaging technology. Therefore, the utility model effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

[0080] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the technology may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed in the present invention shall still be covered by the claims of the present invention.

Claims

1. A chip packaging structure, characterized in that: include: a substrate having a first surface and a second surface opposite to each other; A chip is flip-chip bonded on the first surface of the substrate; A heat dissipation cover is fixed on the first surface of the substrate, a cavity is formed between the heat dissipation cover and the substrate, and the chip is located in the cavity; A heat conduction structure is located in the cavity, the heat conduction structure includes a PI layer and a metal connection structure, the PI layer is laid on the back of the chip, the bottom end of the metal connection structure is connected to the PI layer, the top end of the metal connection structure is connected to the heat dissipation cover, and the metal connection structure includes a plurality of metal columns arranged at intervals.

2. The chip packaging structure according to claim 1, characterized in that: The metal connection structure further includes a plurality of pads, each of which is connected to at least one metal column.

3. The chip packaging structure according to claim 2, characterized in that: The pad is located on the upper surface of the PI layer.

4. The chip packaging structure according to claim 2, characterized in that: The PI layer has a plurality of through holes with the bottoms exposing the back side of the chip, and the plurality of pads are arranged in the plurality of through holes in a one-to-one correspondence.

5. The chip packaging structure according to claim 1, characterized in that: A plurality of solder bumps are formed on one side of the heat dissipation cover facing the back side of the chip. The plurality of solder bumps correspond to the plurality of metal pillars one by one, and each of the metal pillars is connected to the heat dissipation cover through one of the solder bumps.

6. The chip packaging structure according to claim 1, characterized in that: The top ends of the plurality of metal pillars are located on the same horizontal plane.

7. The chip packaging structure according to claim 1, characterized in that: A plurality of solder balls are disposed on the second surface of the substrate.

8. The chip packaging structure according to claim 1, characterized in that: It also includes components, which are fixedly connected to the first surface and / or the second surface of the substrate; wherein, when the components are located on the first surface of the substrate, the components are located in the cavity and are spaced a preset distance from the chip.

9. The chip packaging structure according to claim 1, characterized in that: The heat dissipation cover is fixed on the first surface of the substrate by gluing or welding.

10. The chip packaging structure according to claim 1, characterized in that: The chip includes a single chip or a chip assembly.

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