Package substrate assembly and semiconductor device

Abstract

The utility model discloses a packaging substrate assembly and a semiconductor device, the packaging substrate assembly comprises a substrate, the thickness of the substrate extends in a first direction, the substrate is provided with a first side and a second side which are oppositely arranged in the first direction, and the first side is provided with an avoiding groove; the chip comprises a first chip and a second chip, the first chip is arranged in the groove, a first connecting line is connected between the first chip and the first side of the substrate, the second chip is arranged on the second side, and a second connecting line is connected between the second chip and the second side of the substrate. Therefore, the first chip is arranged in the groove formed in the first side of the substrate, the second chip is arranged on the second side of the substrate, and the first chip and the second chip are arranged on the two sides of the substrate respectively, so that the bonded first chip can be prevented from being damaged when the second chip is bonded, and double-sided lead bonding of the packaging substrate can be realized; signal crosstalk between channels is prevented, the structural design of the packaging substrate assembly can be optimized, and the processing difficulty of the packaging substrate assembly is reduced.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductor devices, in particular to a packaging substrate assembly and a semiconductor device. Background Art

[0002] With the continuous advancement of technology, the semiconductor industry has also developed rapidly. As an important component of semiconductor devices, the packaging substrate assembly can provide electrical connection and protection for the chips in the semiconductor devices.

[0003] In the related art, some packaging structures place the chips on the same side of the substrate, which will cause mutual interference between the signals in the signal channels, affect the signal quality, and increase the chip layout area, thereby increasing the volume of the packaging substrate. In addition, some packaging structures place the chips on both sides of the substrate and use metal bumps on one side to raise the bonding area for protection. Although this can reduce the lead layout density, it will increase the thickness of the substrate, increase the manufacturing cost of the substrate, and the process flow is also more complicated. Utility Model Content

[0004] The utility model aims to solve at least one of the technical problems existing in the prior art. To this end, one purpose of the utility model is to provide a package substrate assembly, which has better channel signal quality, lower cost and simpler process flow.

[0005] The utility model further provides a semiconductor device.

[0006] According to the utility model, the packaging substrate assembly includes: a substrate, the thickness of the substrate extends in the first direction, the substrate has a first side and a second side arranged opposite to each other in the first direction, and the first side is provided with an avoidance groove; a chip, the chip includes a first chip and a second chip, the first chip is arranged in the groove and is connected to the first side of the substrate by a first connecting line, the second chip is arranged on the second side and is connected to the second side of the substrate by a second connecting line, the depth of the groove in the first direction is D, the overall height of the first chip and the first connecting line in the first direction is H, and D and H satisfy the relationship: D>H.

[0007] Therefore, by setting the first chip in the groove opened on the first side of the substrate and setting the second chip on the second side, the first chip and the second chip are respectively set on both sides of the substrate, which can prevent the second chip from causing damage to the bonded first chip during bonding, and can also realize double-sided wire bonding of the packaging substrate to prevent signal crosstalk between channels. The structural design of the packaging substrate assembly can be optimized and the processing difficulty of the packaging substrate assembly can be reduced.

[0008] In some examples of the present invention, an optical coupling device is further included, the optical coupling device includes a first optical coupling device and a second optical coupling device, the second optical coupling device is arranged on the second side and covers the second chip, and the second optical coupling device is electrically connected to the second chip;

[0009] The first optical coupling device is arranged in the groove and covers the first chip, the first optical coupling device is electrically connected to the first chip, the size of the first optical coupling device in the second direction is smaller than the size of the groove in the second direction, and the size of the first optical coupling device in the third direction is smaller than the size of the groove in the third direction.

[0010] In some examples of the present invention, a conductive contact is provided at one end of the first side in the second direction, the groove and the conductive contact are spaced apart in the second direction, the first connecting line includes a first microstrip line segment, a second microstrip line segment and a strip line segment, one end of the first microstrip line segment is electrically connected to the conductive contact, and the other end of the first microstrip line segment is extended in the second direction toward a side adjacent to the groove;

[0011] A metal via is provided in the substrate, the metal via extends in a first direction from the first side toward the second side, one end of the metal via adjacent to the second side is flush with the bottom surface of the groove, the second microstrip line segment is provided on the bottom surface of the groove and one end is connected to the first chip, the stripline segment is provided in the substrate and extends in the second direction, the stripline segment is connected between one end of the metal via adjacent to the second side and the second microstrip line segment, wherein the first direction and the second direction are perpendicular to each other.

[0012] In some examples of the present invention, the line widths of the first microstrip line segment and the second microstrip line segment are equal and greater than the line width of the strip line segment, there are multiple first microstrip line segments, the multiple first microstrip line segments are spaced apart in the third direction, and the distance between two adjacent first microstrip line segments is L1, there are multiple second microstrip line segments, the multiple second microstrip line segments are spaced apart in the third direction, and the distance between two adjacent second microstrip line segments is L2, there are multiple strip line segments, the multiple strip line segments are spaced apart in the third direction, and the distance between two adjacent strip line segments is L3, L1, L2 and L3 satisfy the relationship: L1=L3<L2, wherein the third direction, the first direction and the second direction are perpendicular to each other.

[0013] In some examples of the present invention, a conductive contact is provided at one end of the first side in the second direction, the groove and the conductive contact are spaced apart in the second direction, the first connecting line includes a third microstrip line segment and a fourth microstrip line segment, a metal half-hole is opened on a side wall of the substrate corresponding to the second direction of the groove and adjacent to the conductive contact, the two ends of the metal half-hole are respectively flush with the first side and the bottom of the groove, the third microstrip line segment extends along the second direction on the first side and is connected between the conductive contact and one end of the metal half-hole, and the fourth microstrip line segment extends along the second direction on the bottom surface of the groove and is connected between the first chip and the other end of the metal half-hole.

[0014] In some examples of the present invention, the metal half hole includes a connecting half hole and a grounding half hole, the two ends of the connecting half hole are respectively connected to the third microstrip line segment and the fourth microstrip line segment, the grounding half hole and the connecting half hole are spaced apart in a third direction, wherein the third direction, the first direction and the second direction are perpendicular to each other.

[0015] In some examples of the present invention, the groove is open at a side away from the second side in the first direction.

[0016] In some examples of the present invention, a conductive contact is provided at one end of the first side in the second direction, and the side of the groove in the second direction away from the conductive contact is open, wherein the first direction and the second direction are perpendicular to each other.

[0017] In some examples of the present invention, there are a plurality of grooves, and the plurality of grooves are spaced apart on the substrate. There are a plurality of first chips, and the plurality of first chips correspond one-to-one to the plurality of grooves.

[0018] A semiconductor device according to an embodiment of the present invention includes: the packaging substrate assembly described above.

[0019] Additional aspects and advantages of the present invention will be given in part in the following description, and in part will become apparent from the following description, or will be learned through the practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The above and / or additional aspects and advantages of the present invention will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0021] Figure 1 is a front view of a packaging substrate assembly according to an embodiment of the utility model;

[0022] Figure 2 is a side view of a package substrate assembly according to an embodiment of the utility model;

[0023] Figure 3 is a bottom view of a packaging substrate assembly according to an embodiment of the utility model;

[0024] Figure 4 is a top view of a packaging substrate assembly according to an embodiment of the utility model;

[0025] Figure 5 is a schematic diagram of a packaging substrate assembly according to an embodiment of the utility model;

[0026] Figure 6 is a bottom view of a packaging substrate assembly according to an embodiment of the utility model;

[0027] Figure 7 is a schematic diagram of a packaging substrate assembly according to an embodiment of the utility model;

[0028] Figure 8 is a partial schematic diagram of a packaging substrate assembly according to an embodiment of the utility model;

[0029] Fig. 9 is a schematic diagram of a packaging substrate assembly according to an embodiment of the utility model;

[0030] Fig.10 It is a schematic diagram of a packaging substrate assembly according to an embodiment of the utility model.

[0031] Reference numerals:

[0032] 100. Package substrate assembly;

[0033] 10. substrate; 101. first side; 102. second side; 103. groove;

[0034] 20. Chip; 201. First chip; 202. Second chip;

[0035] 30. Conductive contact;

[0036] 40, first connecting line; 401, first microstrip line segment; 402, second microstrip line segment; 403, strip line segment; 404, third microstrip line segment; 405, fourth microstrip line segment;

[0037] 50. Second connecting line;

[0038] 60. Optical coupling device; 601. First optical coupling device; 602. Second optical coupling device;

[0039] 70. Metal vias;

[0040] 80, metal half hole; 801, connection half hole; 802, grounding half hole. DETAILED DESCRIPTION

[0041] The embodiments of the present utility model are described in detail below. The embodiments described with reference to the accompanying drawings are exemplary. The embodiments of the present utility model are described in detail below.

[0042] Reference below Figure 1-Figure 10 The package substrate assembly 100 according to an embodiment of the present invention is described. The package substrate assembly 100 may be applied to a semiconductor device.

[0043] Combination Figure 1-Figure 10 As shown, the package substrate assembly 100 according to the utility model can mainly include: a substrate 10 and a chip 20. Among them, the thickness of the substrate 10 is extended in the first direction, and the substrate 10 has a first side 101 and a second side 102 arranged opposite to each other in the first direction. The first side 101 is provided with an avoidance groove 103 to provide space for the subsequent placement of the first chip 201 and the first optical coupling device 601. This can not only reduce the arrangement of metal bumps, thereby reducing the thickness of the substrate 10 and reducing costs, but also ensure the stability and reliability of the substrate 10.

[0044] The chip 20 includes a first chip 201 and a second chip 202. The first chip 201 is disposed in the groove 103 and is connected to the first side 101 of the substrate 10 by a first connection line 40. The second chip 202 is disposed on the second side 102 and is connected to the second side 102 of the substrate 10 by a second connection line 50. Specifically, the first chip 201 is disposed in the groove 103 of the first side 101, and the first chip 201 is electrically connected to the conductive contact sheet 30 of the first side 101 through the first connection line 40. The second chip 202 is disposed on the second side 102, and the second chip 202 is electrically connected to the conductive contact sheet 30 of the second side 102 through the second connection line 50. In this way, the first chip 201 and the second chip 202 are disposed on both sides of the substrate 10, respectively, so that double-sided wire bonding of the package substrate assembly 100 can be achieved, the difficulty of signal line layout can be reduced, and signal crosstalk between channels can be prevented.

[0045] The depth of the groove 103 in the first direction is D, the overall height of the first chip 201 and the first connecting wire 40 in the first direction is H, and D and H satisfy the relationship: D>H. Specifically, the design of the groove 103 is mainly used to protect the device in the groove 103, so the depth of the groove 103 should be greater than the overall height of the first chip 201 and the first connecting wire 40 in the first direction, so that the first chip 201 can be completely placed in the groove 103, and the first chip 201 can be better protected.

[0046] In addition, the first chip 201 and the second chip 202 are respectively arranged on both sides of the substrate 10. The first chip 201 needs to be mounted in the groove 103 of the first side 101 and wire-bonded with gold wires. Then the substrate 10 is flipped and laid flat, and the second chip 202 on the second side 102 is mounted and wire-bonded. In this way, after the substrate 10 is flipped, the first chip 201 is completely placed in the groove 103 and has no contact with the plane on which the substrate 10 is placed. This can protect the first chip 201 in the groove 103, and can prevent the first chip 201 from being squeezed after the substrate 10 is flipped, thereby causing the chip 20 to lose its function and be damaged, and can avoid unnecessary waste of materials.

[0047] Therefore, by opening an avoidance groove 103 on the first side 101 of the substrate 10, the first chip 201 is set in the groove 103, and the second chip 202 is set on the second side 102. This can not only prevent signal crosstalk between channels and improve the interconnection density, but also avoid damage to the first chip 201 bonded on the other side when the second chip 202 is bonded, and also eliminate the tooling for wire bonding, which can be integrated with the PCB processing process to save the processing cycle.

[0048] In some embodiments of the present invention, the depth of the groove 103 is set to be less than half of the thickness of the substrate 10 .

[0049] Combination Figure 1 , Figure 2 and Figure 5 As shown, the package substrate assembly 100 further includes an optical coupling device 60, and the optical coupling device 60 includes a first optical coupling device 601 and a second optical coupling device 602. The second optical coupling device 602 is disposed on the second side 102 and covers the second chip 202, and the second optical coupling device 602 is electrically connected to the second chip 202. Specifically, by covering the second optical coupling device 602 on the second chip 202, and the second optical coupling device 602 is electrically connected to the second chip 202, not only can the signal transmission performance of the second side 102 be improved, but also the electrical connection between the input and the output can be effectively prevented, and the anti-interference capability can be improved, and the reliability of the structure of the package substrate assembly 100 can be improved.

[0050] The first optical coupling device 601 is disposed in the groove 103 and covers the first chip 201, and the first optical coupling device 601 is electrically connected to the first chip 201. Specifically, by disposing the first optical coupling device 601 in the groove 103 and covering the first chip 201, the first optical coupling device 601 is electrically connected to the first chip 201, which can not only improve the signal transmission performance of the first side 101, but also effectively prevent the electrical connection between the input and the output, and can also improve the anti-interference ability, and can improve the reliability of the structure of the package substrate assembly 100.

[0051] The size of the first optical coupling device 601 in the second direction is smaller than the size of the groove 103 in the second direction, and the size of the first optical coupling device 601 in the third direction is smaller than the size of the groove 103 in the third direction. Specifically, by setting the size of the groove 103 to be larger than the size of the first optical coupling device 601 in the second direction and also larger than the size of the first optical coupling device 601 in the third direction, it can not only ensure that the first optical coupling device 601 is still completely placed in the groove 103 after being covered on the first chip 201, but also protect the first optical coupling device 601 and the first chip 201 after being attached, but also avoid the problem that the first optical coupling device 601 cannot be tightly attached to the first chip 201 or is difficult to place, and avoid secondary processing of the substrate 10, thereby adding unnecessary processes.

[0052] In some embodiments of the present invention, the first direction, the second direction and the third direction are perpendicular to each other.

[0053] Combination Figure 2 and Figure 3 As shown, a conductive contact 30 is provided at one end of the first side 101 in the second direction, and the groove 103 and the conductive contact 30 are spaced apart in the second direction. The first connecting line 40 includes a first microstrip line segment 401, a second microstrip line segment 402 and a stripline segment 403. One end of the first microstrip line segment 401 is electrically connected to the conductive contact 30, and the other end of the first microstrip line segment 401 is extended in the second direction toward a side adjacent to the groove 103. Specifically, a conductive contact 30 is provided at one end of the first side 101 in the second direction, which mainly plays a connecting role. Other devices can be connected to the conductive contact 30 and signals can be transmitted. Not only can the signal in the package substrate assembly 100 be transmitted, but also external signals can be received and transmitted to the corresponding chip 20 on the substrate 10. In addition, one end of the first microstrip line segment 401 on the first connecting line 40 is electrically connected to the conductive contact 30, and the other end is extended in the second direction toward a side adjacent to the groove 103, so that the transmission path of the signal can be guaranteed and the signal transmission can be effectively performed.

[0054] A metal via 70 is provided in the substrate 10, and the metal via 70 extends from the first side 101 toward the second side 102 in a first direction. One end of the metal via 70 adjacent to the second side 102 is flush with the bottom surface of the groove 103. The second microstrip line segment 402 is provided on the bottom surface of the groove 103 and one end is connected to the first chip 201. The stripline segment 403 is provided in the substrate 10 and extends in the second direction. The stripline segment 403 is connected between one end of the metal via 70 adjacent to the second side 102 and the second microstrip line segment 402, wherein the first direction and the second direction are perpendicular to each other. Specifically, the metal via 70 is arranged in the first direction, and the two ends of the metal via 70 are flush with the first side 101 and the bottom of the groove 103 respectively. One end of the metal via 70 is connected to the first microstrip line segment 401 on the first side 101, and the other end is connected to the strip line segment 403 on the bottom of the groove 103. One end of the second microstrip line segment 402 is connected to the strip line segment 403, and the other end is connected to the first chip 201. The strip line segment 403 is arranged between the metal via 70 and the second microstrip line segment 402. In this way, a complete electrical connection path can be established to ensure normal signal transmission.

[0055] With this arrangement, electrical connection between the conductive contact 30 and the first chip 201 is achieved through the conductive contact 30, the first microstrip line segment 401, the metal via 70, the strip line segment 403, the second microstrip line segment 402, and the first chip 201 in sequence, thereby ensuring the continuity of the impedance and the signal transmission path between the conductive contact 30 and the first chip 201, and ensuring the normal function of the packaging substrate assembly 100.

[0056] Combination Figure 2 and Figure 3As shown, the line widths of the first microstrip line segment 401 and the second microstrip line segment 402 are equal and greater than the line width of the strip line segment 403. There are multiple first microstrip line segments 401, and the multiple first microstrip line segments 401 are spaced apart in the third direction, and the distance between two adjacent first microstrip line segments 401 is L1. There are multiple second microstrip line segments 402, and the multiple second microstrip line segments 402 are spaced apart in the third direction, and the distance between two adjacent second microstrip line segments 402 is L2. There are multiple strip line segments 403, and the multiple strip line segments 403 are spaced apart in the third direction, and the distance between two adjacent strip line segments 403 is L3. L1, L2 and L3 satisfy the relationship: L1=L3<L2, wherein the third direction, the first direction and the second direction are perpendicular to each other. Specifically, the first microstrip line segment 401, the second microstrip line segment 402 and the strip line segment 403 are all multiple, the multiple first microstrip line segments 401 are parallel to each other in the third direction, and a certain spacing distance is set between two adjacent first microstrip line segments 401, the multiple strip line segments 403 are arranged in parallel on the bottom surface of the groove 103 in the third direction, and a certain spacing distance is set between two adjacent strip line segments 403, and the multiple second microstrip line segments 402 are also arranged in parallel on the bottom surface of the groove 103 in the third direction, and a certain spacing distance is set between two adjacent second microstrip line segments 402. A certain spacing distance is set to avoid interference between adjacent line segments. In addition, for the same impedance, the line width of the first microstrip line segment 401 and the second microstrip line segment 402 is set larger than the strip line segment 403. Therefore, the spacing distance between adjacent line segments of the first microstrip line segment 401 and the second microstrip line segment 402 is smaller than the spacing distance between adjacent line segments of the strip line segment 403. In this way, the continuity of impedance between different line segments can be guaranteed, and the normal transmission of signals between different line segments can be guaranteed, so as to ensure the normal operation of the circuit of the packaging substrate assembly 100.

[0057] In some embodiments of the present invention, the remaining non-signal lines may have a uniform line width.

[0058] Combination Figure 6 , Figure 7 and Figure 8As shown, a conductive contact 30 is provided at one end of the first side 101 in the second direction, the groove 103 and the conductive contact 30 are spaced apart in the second direction, the first connecting line 40 includes a third microstrip line segment 404 and a fourth microstrip line segment 405, a metal half hole 80 is opened on a side wall of the substrate 10 corresponding to the groove 103 and adjacent to the conductive contact 30 in the second direction, and the two ends of the metal half hole 80 are respectively flush with the first side 101 and the bottom of the groove 103, the third microstrip line segment 404 extends along the second direction on the first side 101 and is connected between the conductive contact 30 and one end of the metal half hole 80, and the fourth microstrip line segment 405 extends along the second direction on the bottom surface of the groove 103 and is connected between the first chip 201 and the other end of the metal half hole 80. Specifically, the conductive contact 30 is arranged at one end of the first side 101 in the second direction, and the conductive contact 30 and the groove 103 are spaced apart in the second direction, the metal half hole 80 is arranged on a side wall of the substrate 10 corresponding to the groove 103 in the second direction adjacent to the conductive contact 30, and the two ends of the metal half hole 80 are respectively flush with the first side 101 and the bottom of the groove 103, a third microstrip line segment 404 is arranged between the conductive contact 30 and the metal half hole 80 along the second direction, a fourth microstrip line segment 405 is arranged between the metal half hole 80 and the first chip 201 along the second direction, the third microstrip line segment 404 and the fourth microstrip line segment 405 are connected through the metal half hole 80, and the third microstrip line segment 404 and the fourth microstrip line segment 405 can adopt a consistent line width, which can ensure the continuity of impedance and improve the reliability of circuit design.

[0059] Furthermore, the electrical connection between the conductive contact 30 and the first chip 201 is achieved through the conductive contact 30, the third microstrip line segment 404, the metal half hole 80, the fourth microstrip line segment 405, and the first chip 201 in sequence, so that the normal transmission of signals between the conductive contact 30 and the first chip 201 can be ensured, and the normal function of the packaging substrate assembly 100 can be ensured.

[0060] Combination Figure 6 , Figure 7 and Figure 8 As shown, the metal half hole 80 includes a connecting half hole 801 and a grounding half hole 802, the two ends of the connecting half hole 801 are respectively connected to the third microstrip line segment 404 and the fourth microstrip line segment 405, and the grounding half hole 802 is arranged at intervals with the connecting half hole 801 in the third direction, wherein the third direction, the first direction and the second direction are perpendicular to each other. Specifically, the connecting half hole 801 arranged in the third direction mainly plays a connecting role, and the third microstrip line segment 404 and the fourth microstrip line segment 405 are electrically connected through the metal half hole 80. In addition, the grounding half hole 802 is arranged at a certain distance from the connecting half hole 801 as a reference ground of the connecting half hole 801, so that it can be ensured that there is still a complete reference ground when the signal passes through the connecting half hole 801, and the continuity of the impedance can be further guaranteed.

[0061] In some embodiments of the present invention, the diameter of the metal half hole 80 is 0.15 mm, and the center distance between the connecting half hole 801 and the grounding half hole 802 is 0.3 mm.

[0062] Combination Figure 1 , Figure 5 , Figure 7 and Fig. 9 As shown, the groove 103 is openly arranged on one side away from the second side 102 in the first direction. Specifically, by opening the groove 103 on one side away from the second side 102 in the first direction, it is possible to prevent the upward fan-out of the signal and the heat dissipation of the first chip 201 from being affected, thereby ensuring the normal function of the package substrate assembly 100, and facilitating subsequent other tests and fault repairs, thereby increasing the reliability of the structure.

[0063] Combination Figure 2 , Figure 5 and Figure 7 As shown, a conductive contact 30 is disposed at one end of the first side 101 in the second direction, and a side of the groove 103 in the second direction away from the conductive contact 30 is open, wherein the first direction and the second direction are perpendicular to each other. Specifically, by opening the side of the groove 103 in the second direction away from the conductive contact 30, it is not only possible to prevent the signal from fanning out in the slot direction, but also to reduce the difficulty of slotting, and to facilitate the installation of the chip 20 and the optical coupling device 60, thereby increasing the reliability of the structure.

[0064] Combination Fig.10 As shown, there are multiple grooves 103, and the multiple grooves 103 are arranged at intervals on the substrate 10. There are multiple first chips 201, and the multiple first chips 201 correspond one-to-one to the multiple grooves 103. Specifically, the functions of the package substrate assembly 100 are different, and the types and quantities of chips 20 to be packaged may also be different. Therefore, the package substrate assembly 100 can have multiple grooves 103, and there are also multiple first chips 201. The first chips 201 correspond one-to-one to the grooves 103. The first chips 201 are placed in the corresponding grooves 103 respectively. This can not only better protect the first chip 201 and avoid damage to the first chip 201 during the mounting process, but also make the installation of the first chip 201 simpler and more intuitive.

[0065] Furthermore, the total groove width of the plurality of grooves 103 does not exceed 80% of the entire board width, which can prevent local cracking and warping of the substrate 10 and ensure the reliability of the overall structure of the package substrate assembly 100 .

[0066] The semiconductor device according to the present invention can mainly include: the above-mentioned package substrate assembly 100. Specifically, since the package substrate assembly 100 has a simpler structure and can well protect the chip 20, applying the package substrate assembly 100 to the semiconductor device can reduce the manufacturing cost, simplify the process flow, and save the processing cycle.

[0067] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present invention.

[0068] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the utility model. In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment or example.

[0069] Although the embodiments of the present invention have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the claims and their equivalents.

Claims

1. A packaging substrate assembly, comprising: A substrate, wherein the thickness of the substrate is extended in a first direction, the substrate has a first side and a second side which are arranged opposite to each other in the first direction, and the first side is provided with an avoidance groove; The chip comprises a first chip and a second chip, the first chip is arranged in the groove and is connected to the first side of the substrate by a first connecting line, the second chip is arranged on the second side and is connected to the second side of the substrate by a second connecting line, the depth of the groove in the first direction is D, the overall height of the first chip and the first connecting line in the first direction is H, and D and H satisfy the relationship: D>H.

2. The package substrate assembly according to claim 1, characterized in that: It also includes an optical coupling device, the optical coupling device includes a first optical coupling device and a second optical coupling device, the second optical coupling device is arranged on the second side and covers the second chip, and the second optical coupling device is electrically connected to the second chip; The first optical coupling device is arranged in the groove and covers the first chip, the first optical coupling device is electrically connected to the first chip, the size of the first optical coupling device in the second direction is smaller than the size of the groove in the second direction, and the size of the first optical coupling device in the third direction is smaller than the size of the groove in the third direction.

3. The package substrate assembly according to claim 1, characterized in that: A conductive contact is provided at one end of the first side in the second direction, the groove and the conductive contact are spaced apart in the second direction, the first connecting line comprises a first microstrip line segment, a second microstrip line segment and a strip line segment, one end of the first microstrip line segment is electrically connected to the conductive contact, and the other end of the first microstrip line segment is extended in the second direction toward a side adjacent to the groove; A metal via is provided in the substrate, the metal via extends in a first direction from the first side toward the second side, one end of the metal via adjacent to the second side is flush with the bottom surface of the groove, the second microstrip line segment is provided on the bottom surface of the groove and one end is connected to the first chip, the stripline segment is provided in the substrate and extends in the second direction, the stripline segment is connected between one end of the metal via adjacent to the second side and the second microstrip line segment, wherein the first direction and the second direction are perpendicular to each other.

4. The package substrate assembly according to claim 3, characterized in that: The line widths of the first microstrip line segment and the second microstrip line segment are equal and greater than the line width of the stripline segment. There are multiple first microstrip line segments, and the multiple first microstrip line segments are spaced apart in the third direction, and the distance between two adjacent first microstrip line segments is L1. There are multiple second microstrip line segments, and the multiple second microstrip line segments are spaced apart in the third direction, and the distance between two adjacent second microstrip line segments is L2. There are multiple stripline segments, and the multiple stripline segments are spaced apart in the third direction, and the distance between two adjacent stripline segments is L3. L1, L2 and L3 satisfy the relationship: L1=L3<L2, wherein the third direction, the first direction and the second direction are perpendicular to each other.

5. The package substrate assembly according to claim 1, characterized in that: A conductive contact is provided at one end of the first side in the second direction, the groove and the conductive contact are spaced apart in the second direction, the first connecting line includes a third microstrip line segment and a fourth microstrip line segment, a metal half-hole is provided on a side wall of the substrate corresponding to the second direction of the groove and adjacent to the conductive contact, the two ends of the metal half-hole are respectively flush with the first side and the bottom of the groove, the third microstrip line segment extends along the second direction on the first side and is connected between the conductive contact and one end of the metal half-hole, and the fourth microstrip line segment extends along the second direction on the bottom surface of the groove and is connected between the first chip and the other end of the metal half-hole.

6. The packaging substrate assembly according to claim 5, characterized in that: The metal half hole includes a connecting half hole and a grounding half hole, the two ends of the connecting half hole are respectively connected to the third microstrip line segment and the fourth microstrip line segment, the grounding half hole and the connecting half hole are spaced apart in a third direction, wherein the third direction, the first direction and the second direction are perpendicular to each other.

7. The package substrate assembly according to claim 1, characterized in that: The groove is open at a side away from the second side in the first direction.

8. The package substrate assembly according to claim 7, characterized in that: A conductive contact is disposed at one end of the first side in the second direction, and a side of the groove in the second direction away from the conductive contact is open, wherein the first direction and the second direction are perpendicular to each other.

9. The package substrate assembly according to claim 1, characterized in that: There are a plurality of grooves, and the plurality of grooves are arranged at intervals on the substrate. There are a plurality of first chips, and the plurality of first chips correspond to the plurality of grooves one by one.

10. A semiconductor device, characterized in that: A packaging substrate assembly comprising any one of claims 1-9.

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