Semiconductor wafer

Abstract

A semiconductor wafer is provided. An example semiconductor wafer has a plurality of die regions divided by die space regions, and includes a wafer substrate, a plurality of dies disposed on the wafer substrate, and a plurality of buried sacrificial structures corresponding to the plurality of dies. Each die is located in a corresponding die region and also includes a die substrate, an integrated circuit device disposed on the die substrate, and a multi-layer interconnect structure disposed on the integrated circuit device. A buried sacrificial structure surrounds the die substrate and is disposed between the die and the wafer substrate. The buried sacrificial structure also includes a bottom portion disposed in the die region and a side portion circumferentially connected to the bottom portion. The side portions are located in the grain spacing areas, surround the grains and are arranged on the side walls of the grain substrate.

Description

Technical Field

[0001] The embodiments of the present disclosure are mostly related to wafer-level dicing, and more particularly to wafer-level die separation using buried sacrificial structures. Background Art

[0002] The semiconductor industry has experienced rapid growth due to the continuous improvement of integrated circuit density of various electronic components (such as transistors, diodes, resistors, capacitors, etc.). In most cases, the increase in integrated circuit density is achieved by repeatedly shrinking the minimum feature size, thereby allowing more components to be integrated into a given area. Utility Model Content

[0003] According to at least one embodiment of the present disclosure, a semiconductor wafer has a plurality of die regions divided by a die spacing region, the semiconductor wafer comprising: a wafer substrate; a plurality of dies corresponding to the die regions and disposed on the wafer substrate, each of the dies being located in a corresponding one of the die regions and comprising: a die substrate extending vertically from an upper surface to a lower surface and comprising a side wall circumferentially connecting the upper surface and the lower surface; an integrated circuit element disposed in the die substrate; and a multi-layer interconnect structure disposed on the integrated circuit element and electrically connected to the integrated circuit element; and a plurality of buried sacrificial structures corresponding to the dies and embedded in the wafer substrate, each of the buried sacrificial structures surrounding a corresponding one of the dies and disposed between a corresponding one of the dies and the wafer substrate, wherein the buried sacrificial structure further comprises: a bottom portion disposed in the die region and in contact with the lower surface of the die substrate; and a side portion circumferentially connected to the bottom portion, the side portion being located in the die spacing region surrounding a corresponding one of the dies and disposed on the side wall of the die substrate, wherein the side portion has an upper surface and is coplanar with the upper surface of the die substrate.

[0004] According to at least one embodiment of the present disclosure, a semiconductor wafer has a plurality of die regions divided by a die spacing region, the semiconductor wafer comprising: a wafer substrate; a plurality of dies corresponding to the die regions and disposed on the wafer substrate, each of the dies being located in a corresponding one of the die regions and comprising: a die substrate extending vertically from an upper surface to a lower surface and comprising a side wall circumferentially connecting the upper surface and the lower surface; an integrated circuit element disposed in the die substrate; and a multi-layer interconnect structure disposed on the integrated circuit element and electrically connected to the integrated circuit element ; and a plurality of buried sacrificial structures corresponding to the grains and embedded in the wafer substrate, each of the buried sacrificial structures surrounds the corresponding grain substrate and is disposed between a corresponding one of the grains and the wafer substrate, the buried sacrificial structure comprises silicon oxide, wherein the buried sacrificial structure further comprises: a bottom portion, disposed in the grain region and in contact with the lower surface of the grain substrate; and a side portion, circumferentially connected to the bottom portion, the side portion is located in the grain spacing region surrounding the corresponding one of the grains and disposed on the side wall of the grain substrate, wherein the side portion has an upper surface and is coplanar with the upper surface of the grain substrate.

[0005] According to at least one embodiment of the present disclosure, a semiconductor wafer has a plurality of die regions divided by a die spacing region, the semiconductor wafer comprising: a wafer substrate; a plurality of dies corresponding to the die regions and disposed on the wafer substrate, each of the dies being located in a corresponding one of the die regions and comprising: a die substrate extending vertically from an upper surface to a lower surface and comprising a side wall circumferentially connecting the upper surface and the lower surface; an integrated circuit element disposed in the die substrate; and a multi-layer interconnect structure disposed on the integrated circuit element and electrically connected to the integrated circuit element; and a plurality of buried sacrificial structures corresponding to the die substrate. The buried sacrificial structure is disposed to the die and embedded in the wafer substrate, each of the buried sacrificial structures surrounds the corresponding die substrate and is disposed between a corresponding one of the die and the wafer substrate, wherein the buried sacrificial structure further comprises: a bottom portion, disposed in the die region and in contact with the lower surface of the die substrate; and a side portion, circumferentially connected to the bottom portion, the side portion is located in the die spacing region, surrounds the corresponding one of the die and is disposed on the side wall of the die substrate, wherein the side portion has an upper surface and is coplanar with the upper surface of the die substrate, wherein the die substrate has an angle (α) generated between the side portion and the bottom portion, and the angle (α) is at least 120 degrees. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. Note that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1A is a top view of a design of an example semiconductor wafer according to some embodiments;

[0008] Figure 1B According to some embodiments, Figure 1A A cross-sectional view of an example semiconductor wafer along a dotted line AA';

[0009] Figure 2A is a top view of a design of an example semiconductor wafer according to some embodiments;

[0010] Figure 2B According to some embodiments, Figure 2A The middle portion is a cross-sectional view of an exemplary semiconductor wafer along the dashed line BB';

[0011] Figure 3A is a top view of another example wafer design according to some embodiments;

[0012] Figure 3B is a top view of another example wafer design according to some embodiments;

[0013] Figure 4 is a flow chart of an example method for wafer level process separation according to some embodiments;

[0014] Figure 5 According to some embodiments, Figure 4 A flowchart of the example operation shown in ;

[0015] Figure 6 According to some embodiments, Figure 4 A flowchart of another example operation in ;

[0016] FIG. 7A to FIG. 7R According to some embodiments, the wafer is used Figures 4 to 6 Cross-sections of the example method at various stages are shown.

[0017]

Explanation of symbols

[0018] 100:Semiconductor wafer

[0019] 102: Wafer substrate

[0020] 103: Grain

[0021] 104: Integrated Circuit Components

[0022] 105: Grain spacing area

[0023] 106:Multilayer interconnection structure

[0024] 107: Grain area

[0025] 108: Boundary

[0026] 110: Buried Sacrificial Structure

[0027] 111: Boundary

[0028] 112: Side part

[0029] 114: Bottom part

[0030] 115: Surface

[0031] 116: Side wall

[0032] 117: Surface

[0033] 118: Surface

[0034] 119: Sacrifice Area

[0035] 120: Grain substrate

[0036] 121: Surface

[0037] 122: Surface

[0038] 132: Passivation layer

[0039] 134: Passivation layer

[0040] 136: passivation layer

[0041] 136a: Part

[0042] 136b: Partial

[0043] 200:Semiconductor wafer

[0044] 202: Cutting groove

[0045] 204: Open end

[0046] 206: Open end

[0047] 208: Side wall

[0048] 212: Side wall

[0049] 300A: Wafer

[0050] 300B: Wafer

[0051] 301: Wafer substrate

[0052] 302: Grain

[0053] 304: Grain

[0054] 306: Grain

[0055] 308: Grain

[0056] 310: Grain spacing area

[0057] 312: Buried Sacrificial Structure

[0058] 314: Buried Sacrificial Structure

[0059] 400: Example Method

[0060] 402: Operation

[0061] 404: Operation

[0062] 406: Operation

[0063] 502: Operation

[0064] 504: Operation

[0065] 506: Operation

[0066] 508: Operation

[0067] 510: Operation

[0068] 512: Operation

[0069] 514: Operation

[0070] 602: Operation

[0071] 604: Operation

[0072] 606: Operation

[0073] 608: Operation

[0074] 610: Operation

[0075] 612: Operation

[0076] 614: Operation

[0077] 616: Operation

[0078] 618: Operation

[0079] 620: Operation

[0080] 622: Operation

[0081] 624: Operation

[0082] 700: Wafer

[0083] 702a: Pattern

[0084] 702b: Pattern

[0085] 704: Groove

[0086] 706: Oxygen implant layer

[0087] 706a: Part

[0088] 706b: Part

[0089] 708: silicon epitaxial layer

[0090] 708a: Part

[0091] 708b: Partial

[0092] 710: silicon epitaxial layer

[0093] 720: Opening

[0094] 730:Pre-etched handle

[0095] 732: Carrier

[0096] 734: Support

[0097] 736: Carrier

[0098] 740: Hole

[0099] 742: Substrate gap

[0100] 744: Cutting Gap

[0101] 746: Bottom tape

[0102] A-A': dotted line

[0103] B-B': dotted line

[0104] D1: Length

[0105] D2: Length

[0106] T1: Thickness

[0107] T2: Thickness

[0108] α: Angle

[0109] γ: angle DETAILED DESCRIPTION

[0110] The following disclosure provides many different embodiments or examples for implementing the different features of the subject matter provided. Specific examples of components and configurations are described below to simplify the disclosure. Of course, these are only examples and are not intended to be restrictive. For example, in the following description, the formation of a first feature above or on a second feature may include an embodiment in which the first and second features are directly contacted, and may also include an embodiment in which additional features may be formed between the first and second features so that the first and second features may not be in direct contact. In addition, in various examples, the disclosure may repeat reference numbers and / or letters. This repetition is for the purpose of simplicity and clarity, and does not itself define the relationship between the various embodiments and / or configurations discussed.

[0111] Additionally, for ease of description, spatially relative terms such as "beneath," "below," "lower," "above," and "upper," and the like, may be used herein to describe the relationship of one element or feature to another element or feature as illustrated in the figures. The various spatially relative terms are intended to encompass different orientations of the elements in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein likewise interpreted accordingly.

[0112] In addition, the source / drain regions may be represented as a source or a drain, respectively or collectively, depending on the context of the article. For example, a component may include a first source / drain region and a second source / drain region relative to other components. The first source / drain region may be a source, and the second source / drain region may be a drain, or vice versa. Those of ordinary skill in the art will recognize many variations, modifications, and substitutions thereof.

[0113] Some embodiments disclosed will be described. More operations may be provided before, during and / or after the stages described in these embodiments. In different embodiments, some of the stages discussed may be replaced or deleted. In different embodiments, some of the features discussed may be replaced or deleted and other features may be added. Although certain embodiments and operations are discussed and implemented at specific scales, these operations may also be implemented at other reasonable scales.

[0114] Overview.

[0115] Modern integrated circuits (ICs) are made with millions of electronic components such as transistors or capacitors. The electronic components are initially isolated from each other, but are later interconnected by wire routing resources to create functional circuits using back-end processing. Typical interconnect structures include lateral structures such as metal wires and vertical structures such as vias and contacts. On top of the interconnect structures, pads are created and exposed on the surface of the individual (semiconductor) die. Electrical connections are made by connecting the die to the package substrate or another die through the pads. Pads can be used for wire bonding or flip chip bonding. Flip chip packaging uses bumps to establish electrical contact between the die input / output pads and the substrate or package lead frame. Wafer level die scale packaging (WLCSP) is currently widely used due to its low cost and relatively simple process, in which ball implantation and ball growth processes are used in wafer level die scale packaging.

[0116] Thus, dozens or hundreds of integrated circuits can be fabricated on a single semiconductor wafer. These individual integrated circuits are sometimes referred to as individual "dies". The individual dies are usually separated or segmented in a separation process. A common method used in the separation process is to cut the individual dies along the dicing lines. The cutting can be performed mechanically or by laser cutting. After the separation process, each die can be packaged and used separately.

[0117] The width of the dicing road is usually about 60μm. The wafer area under the dicing road is usually wasted. For dies manufactured using more advanced technology nodes (such as 3 nanometers), the wasted wafer area becomes larger as the size of each die shrinks. In addition, the die may be damaged during the mechanical dicing or laser dicing process. Finally, the mechanical dicing or laser dicing process requires back grinding, which causes additional manufacturing process complexity and additional expenses.

[0118] The present disclosure provides methods to address the above-mentioned challenges. According to some disclosed embodiments, a new method for wafer-level die separation using a buried sacrificial layer is provided. According to some embodiments, the method includes manufacturing a plurality of buried sacrificial structures embedded in a wafer substrate. Then, each die is individually generated above the buried sacrificial structure, so that each buried sacrificial structure surrounds the die substrate of each independent die. The die is then separated from the wafer by removing the buried sacrificial layer structure, such as using an etching process.

[0119] Unlike mechanical cutting or laser cutting, according to the present disclosure, there is no need for a cutting path to separate the dies. Therefore, the utilization of the chip area can be improved, and potential damage caused by mechanical cutting or laser cutting can be avoided. In one example, the space between two adjacent dies is 0.2μm to 1μm, compared to the width of the cutting path, which is about 60μm. In addition, extremely small thickness of each die can be achieved. In one example, the thickness of the produced die is between 2μm and 200μm. In addition, each die may not be limited in shape and two-dimensional structure, and non-standard or irregular shaped dies can be densely stacked on the horizontal plane of the wafer, which can further enhance the design flexibility, improve the utilization of wafer area, and improve the yield of the die. In addition, each separated die obtained by etching away the buried sacrificial structure can have a smooth outer surface and low roughness compared to the die obtained from mechanical cutting processes such as cutting separation.

[0120] Examples of semiconductor die and semiconductor wafer.

[0121] Figure 1A is a top view of an example semiconductor wafer 100 according to some embodiments. Figure 1B yes Figure 1AFIG. 1 is a cross-sectional view of an exemplary semiconductor wafer 100 along dashed line AA' in FIG. In the exemplary embodiment, the semiconductor wafer 100 (hereinafter referred to as "wafer") includes, among other parts, a wafer substrate 102, a plurality of semiconductor dies 103 (hereinafter referred to as "dies"), and a plurality of buried sacrificial structures 110 (sometimes referred to as "buried sacrificial structures" or "buried sacrificial layers" or the like) disposed between the wafer substrate 102 and each of the dies 103.

[0122] like Figure 1A As shown, the semiconductor wafer 100 has a plurality of different die regions 107 separated and isolated by die spacing regions 105. For simplicity, each die region 107 may have a standard shape or outline such as a square or a rectangle. However, other shapes such as non-standard or irregular shapes (e.g., pentagons, hexagons, crosses, etc.) are also possible in alternative embodiments. Each die region 107 has a boundary 108, and each die 103 is disposed within the corresponding die region 107 in the boundary 108. The plurality of die 103 may be arranged in a pattern such as a horizontal or vertical pattern. The plurality of die 103 may be densely stacked so that the die spacing region 105 has a substantially smaller dimension than the die region 107. The number of die 103 in the semiconductor wafer 100 depends on the size of the die and the size of the wafer substrate 102. The die 103 are arranged to be separated from each other by the die spacing region 105. According to the present disclosure, the horizontal dimension of the grain spacing region 105 (i.e., the distance between two adjacent grains 103, or the distance between the edge of the wafer substrate 102 and the edge adjacent to the grain 103) can be less than 100 μm, less than 60 μm, less than 40 μm, less than 20 μm, less than 10 μm, less than 5 μm or less than 2 μm.

[0123] In some embodiments, the wafer substrate is a silicon-on-insulator (SOI) structure of a single crystalline semiconductor material such as at least one of silicon, silicon carbide, germanium, silicon germanium, gallium indium arsenide, gallium arsenide, indium antimonide, gallium phosphide, gallium antimonide, aluminum indium arsenide, antimony gallium phosphide, antimony gallium arsenide, or indium phosphide, but not limited thereto. In some embodiments, each die 103 may include a logic die such as a central processing unit (CPU) die, a graphics processing unit (GPU) die, a mobile application die, or the like.

[0124] like Figure 1BAs shown, each die 103 includes a die substrate 120 disposed on a corresponding buried sacrificial structure 110, at least one integrated circuit (IC) component 104, and a multi-layer interconnect (MLI) structure 106 (also referred to as an "interconnect structure"). The integrated circuit component 104 can be one or more active or passive components such as transistors, diodes, resistors, and capacitors. The multi-layer interconnect structure 106 is disposed on the integrated circuit component 104 and electrically connected thereto. The integrated circuit component 104 is disposed on the die substrate 120. The multi-layer interconnect structure is configured to electrically connect the integrated circuit component to another internal component or externally connect to the die 103.

[0125] The multilayer interconnect structure 106 is a set of metallization layers (sometimes referred to as "metal layers") that are added on one side of the substrate. The metallization layers are patterned to create a complex interconnect network that connects different parts together. Each metallization layer is created on a corresponding dielectric layer and includes a plurality of horizontal metal features (e.g., metal lines) and vertical metal features (e.g., metal vias) created on the corresponding dielectric layer.

[0126] In some embodiments, a plurality of passivation layers (e.g., a first passivation layer 132 and a second passivation layer 134) are sequentially disposed on the top metal layer of the multi-layer interconnect structure 106. In some embodiments, the passivation layer is formed of a dielectric material, such as undoped silicate glass (USG), silicon nitride, silicon oxide, silicon oxynitride, or a non-porous material by any suitable method, such as chemical vapor deposition, physical vapor deposition, or the like. In some embodiments, an interlayer dielectric (ILD) structure (not shown) is disposed between the multi-layer interconnect structure 106 and the integrated circuit device 104, and a conductive feature (not depicted) may be disposed in the interlayer dielectric structure to electrically interconnect the integrated circuit device 104 and the multi-layer interconnect structure 106.

[0127] In some embodiments, the die substrate 120 and the wafer substrate 102 may be identical in composition (i.e., composed of the same material such as silicon). Alternatively, the die substrate 120 and the wafer substrate 102 may be composed of different materials. In some embodiments, the wafer substrate 102 comprises silicon and the die substrate 120 comprises silicon carbide.

[0128] In some illustrative examples, each buried sacrificial structure 110 is buried or embedded in the wafer substrate 102 and disposed between the die substrate 120 and the wafer substrate 102. Figure 1AAs shown, the buried sacrificial structure 110 is located in a sacrificial region 119 defined by a boundary 111 (dashed area). The sacrificial region 119 overlaps and encompasses the die region 107 in the XY plane and is substantially aligned and centered with the die region 107. The boundary 111 is substantially aligned or parallel to the boundary 108 of the die region 107. A portion of the sacrificial region 119 (i.e., between the boundary 111 and the boundary 108) is located in the die spacing region 105 and surrounds the die region 107.

[0129] like Figure 1B As shown, each buried sacrificial structure 110 further includes a side portion 112 and a bottom portion 114. The side portion 112 is circumferentially connected to the bottom portion 114. The side portion 112 is substantially located in a portion of the sacrificial region 119 between the boundary 111 and the boundary 108. The bottom portion 114 is located in a portion of the sacrificial region 119 substantially overlapping the die region 107. An angle (α) formed between the side portion 112 and the bottom portion 114 is at least 85 degrees. In some embodiments, the angle (α) is at least 90 degrees, at least 100 degrees, at least 110 degrees, at least 120 degrees. The side portion 112 of the buried sacrificial structure 110 is substantially located in the die spacing region 105 and surrounds the integrated circuit device 104. The die substrate 120 of each die 103 substantially covers and is vertically aligned with the bottom portion 114 of the buried sacrificial structure 110. The side portion 112 has an upper surface 115 coplanar with an upper surface 117 of the die substrate 120. In some embodiments, the buried sacrificial structure 110 is composed of silicon oxide (SiO 2 ). In another embodiment, the buried sacrificial structure 110 may include metal, polymer, polysilicon, oxide, or a combination thereof.

[0130] The die base plate 120 is disposed and surrounds the corresponding buried sacrificial structure 110. Each die base plate 120 vertically extends from an upper surface 117 to a lower surface 118, and further includes a sidewall 116 circumferentially connecting the upper surface 117 and the lower surface 118. The sidewall 116 is substantially aligned with and in contact with the side portion 112 of the buried sacrificial structure 110, and the lower surface 118 is substantially aligned with and in contact with the bottom portion 114 of the buried sacrificial structure. Therefore, the angle formed between the lower surface 118 and the sidewall 116 is substantially equal to the angle between the side portion 112 and the bottom portion 114 of the buried sacrificial structure 110.

[0131] like Figure 1B As shown, the side portion 112 and the bottom portion 114 of the buried sacrificial structure 110 may have a critical dimension or thickness (T1), which can be measured from the distance from the upper surface 121 to the lower surface 122 of the side portion 112 and the bottom portion 114. T1 also expresses the distance between the boundary 108 and the boundary 111, as Figure 1AIn some embodiments, T1 may be from about 0.2 μm to about 20 μm, from about 0.2 μm to 10 μm, from about 0.2 μm to 5 μm, from about 0.2 μm to 1 μm. The die substrate 120 may have a thickness T2, which may be from about 1 μm to about 500 μm, from about 2 μm to about 200 μm, or from 2 μm to 100 μm.

[0132] Figure 2A is a top view of an example semiconductor wafer 200 according to some embodiments. Figure 2B yes Figure 2A A cross-sectional view of an exemplary semiconductor wafer 200 along a dashed line BB' is shown. The semiconductor wafer 200 is Figure 1A to Figure 1B A close-up of a variation of a semiconductor wafer 100. In the illustrated example, the semiconductor wafer 200 includes, among other things, a wafer substrate 102, a plurality of dies 103, and a plurality of buried sacrificial structures 110 disposed between the wafer substrate 102 and each of the dies 103. Each of the dies 103 is individually separated by a die spacing region 105. The semiconductor wafer 200 includes a plurality of saw grooves 202 (sometimes referred to as "streets" or "channels") corresponding to the plurality of dies 103. Each saw groove 202 is located in the die spacing region 105 surrounding a corresponding die 103, or more particularly, in a portion of the sacrificial region 119 between a boundary 108 and a boundary 111. The saw grooves 202 may be generated by the multi-layer interconnect structure 106 and circumferentially connect a side portion 112 of a corresponding buried sacrificial structure 110 such that an upper surface of the side portion 112 is exposed to the saw groove 202.

[0133] In the example shown, each saw groove 202 is exposed at the overlapped portion of the die spacing region 105 and the sacrificial region 119 surrounding the peripheral die region 107. Figure 2B As shown, each cutting groove 202 extends vertically from an upper open end 204 to a lower open end 206 and horizontally from an inner sidewall 212 to an outer sidewall 208. The lower open end 206 is connected to the upper surface of the side portion 112 of the buried sacrificial structure 110 and has a horizontal length (D1). The upper open end 204 has a horizontal length (D2). In some embodiments, D2 is substantially the same as D1. In other embodiments, D2 is greater than D1, so that the inner sidewall 212 and the outer sidewall 208 have an inclination. In some embodiments, D1 is greater than or approximately the same as T1, so that the upper surface of the side portion 112 of the buried sacrificial structure 110 is substantially exposed to the cutting groove 202.

[0134] In some embodiments, the semiconductor wafer 200 further includes a third passivation layer 136, which is disposed on the second passivation layer 134 and the inner sidewalls 212 and the outer sidewalls 208 of the cutting groove 202. The third passivation layer 136 can serve as a protective layer to protect the inner sidewalls 212 in a subsequent manufacturing process (e.g., etching). After the separation process, the die 103 is separated from the semiconductor wafer 200, and the inner sidewalls 212 become the sidewalls of the independent die 103. Therefore, the third passivation layer can also protect the independent die 103.

[0135] It is to be understood that the buried sacrificial structure 110 may be completely or substantially removed to create a substrate void in the same area (eg, Figure 7P The substrate void 742 may be in the shape of a buried sacrificial structure 110 and circumferentially connect the cutting groove 202 to generate a continuous cutting void (eg, Figure 7P The cut gap 744 surrounds and partially covers the die 103. In the separation process, the cut gap can be used to separate the die 103 from the wafer substrate 102. More examples of buried sacrificial structure removal, substrate gap and cut gap generation, and separation processes for making individual die will be described in the following reference figures. FIG. 7A to FIG. 7R A more detailed discussion is available.

[0136] Figure 3A and Figure 3B 300A and 300B are top views of more exemplary wafer designs, respectively, according to some embodiments. Wafers 300A and 300B are close variations of semiconductor wafer 100 and semiconductor wafer 200, showing various 2-dimensional (2D) shapes and densely packed die patterns on the wafer level. Figure 3A In the example of FIG. 3 , a wafer 300A includes a plurality of dies 302 and 304 of various shapes and a buried sacrificial structure 312 for each of the dies 302 and 304. The die 302 has a non-standard shape (i.e., a cross shape), and the die 304 has a rectangular shape. The dies 302 and 304 are separated from each other by a die spacing region 310, and the buried sacrificial structure 312 is disposed between the wafer substrate 301 and each of the dies 302 and 304. The side portions of the buried sacrificial structure 312 are located in the die spacing region 310 surrounding each of the dies 302 and 304. These dies 302 and 304 may be arranged on the XY plane in a complementary manner.

[0137] exist Figure 3BIn the illustrated example, the wafer 300B also includes a plurality of dies 306 and 308 of various shapes and a buried sacrificial structure 314 in each of the dies 306 and 308. The die 306 has a hexagonal shape and the die 308 has a trapezoidal shape (i.e., half of a hexagon). The dies 306 and 308 are spaced apart from each other by a die spacing region 310, and the buried sacrificial structure 314 is disposed between the wafer substrate 301 and each of the dies 306 and 308. The sidewalls of the buried sacrificial structure are located in the die spacing region 310 surrounding each of the dies 306 and 308. The dies 306 and 308 may also be arranged in a highly complementary manner on the wafer 300B. Because these non-standard and irregularly shaped dies can be separated and isolated from the wafer using buried sacrificial structures (i.e., buried sacrificial structures 312 and buried sacrificial structures 314) without using dicing streets, these non-standard or irregularly shaped dies can be densely stacked on the XY plane, minimizing the wasted space of the wafer. This allows a greater number of dies to be accommodated on the wafer, so that production efficiency and yield can be improved.

[0138] An example of the process of making a craft.

[0139] Figure 4 is a flow chart of an example method 400 for wafer-level die separation of a wafer 700 , according to some embodiments. Figure 5 According to some embodiments, Figure 4 Flowchart of example operation 402 . Figure 6 is a flow diagram of example operation 406 according to some embodiments. FIG. 7A to FIG. 7Q According to some embodiments, using Figure 4 The example method 400 is a cross-sectional view of a wafer 700 at various stages of fabrication.

[0140] like Figure 4 In the illustrated example, the example method 400 includes operation 402, operation 404, and operation 406. More operations may be implemented herein. In operation 402, a plurality of buried sacrificial structures are fabricated in a wafer substrate.

[0141] like Figure 5 In the example shown, operation 402 includes operation 502, operation 504, operation 506, operation 508, operation 510, operation 512, and operation 514. More operations may be implemented herein. At the same time, it should be understood that various Figure 5 The order of operations is provided for reference only, and therefore, other implementations may use different orders. These different operation orders are all included in the scope of this embodiment.

[0142] In operation 502, a semiconductor substrate (ie, a wafer substrate) is provided. As described above, the semiconductor substrate may be a silicon substrate. It should be understood that other types of substrates may also be used in other embodiments.

[0143] In operation 504, a trench is generated in a semiconductor substrate. In one embodiment, the semiconductor substrate is selectively etched to generate the trench. In one embodiment, the trench is obtained by etching an exposed area outside a first mask pattern of the semiconductor substrate. In one embodiment, the first mask pattern is a photoresist mask pattern. In another embodiment, the first mask pattern is a hard mask pattern, which may include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. In one embodiment, the semiconductor substrate is etched using wet etching. In another embodiment, the semiconductor substrate is etched using dry etching. In one example, the semiconductor substrate is etched using plasma etching.

[0144] like Fig. 7A In the example shown, the wafer substrate 102 is a portion of the wafer 700 and has an exposed area outside the first mask pattern 702a. The geometry of the exposed area corresponds to the trench to be formed.

[0145] like Figure 7B In the example shown, the trench 704 is generated by etching the wafer substrate 102. After the wafer substrate 102 is etched, the trench 704 has a bottom and sidewalls. The bottom and sidewalls define Figure 1A In some embodiments, the angle α is at least 85 degrees. In one example, the angle α is 90 degrees. In another example, the angle α is 100 degrees. In another example, the angle α is 110 degrees. In another example, the angle α is 120 degrees.

[0146] In operation 506, an oxide implant layer is generated. In one embodiment, the opening is defined by a second mask pattern 702b, which has a larger opening than the first mask used in operation 504. The difference between the two masks is the geometry of the buried sacrificial structure 110 (in the XY plane), such as Figure 1B In one embodiment, the second mask pattern 702b is a photoresist mask pattern. In another embodiment, the second mask pattern 702b is a hard mask pattern, and the hard mask pattern may include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

[0147] The semiconductor substrate area outside the exposure of the second mask pattern 702b is implanted with oxygen. Therefore, oxygen is implanted below the surface of the semiconductor substrate and the sidewalls of the trench. Depending on the energy and time of the implantation, the thickness of the oxygen implantation layer can be adjusted. The thickness of the oxygen implantation layer is defined as the portion below the upper surface that has a greater oxygen concentration than the original amount. In one example, the oxygen concentration range is between 5×10 15cm -2 Up to 5×10 18 cm -2 It should be appreciated that other values ​​of oxygen concentration may be used in other examples.

[0148] like Fig.7D In the example shown, the oxide implant layer 706 is formed after operation 506. The oxide implant layer 706 corresponds to Figure 1B The buried sacrificial structure 110 is shown. The implanted oxide layer 706 has a bottom portion 706a and a sidewall portion 706b. The sidewall portion 706b is disposed at the sidewall portion of the trench 704. The sidewall portion 706b and the bottom portion 706a define an angle γ, such as Figure 1B In some embodiments, angle γ is at least 85 degrees. In one embodiment, angle γ is 90 degrees. In other embodiments, angle γ is 100 degrees. In another embodiment, angle γ is 110 degrees. In another embodiment, angle γ is 120 degrees. In some embodiments, angle γ is substantially the same as angle α.

[0149] In operation 508, a first silicon epitaxial layer is grown on the oxide implant layer. In one embodiment, the opening is defined by the first mask pattern used in operation 504, which has a smaller opening than the second mask pattern 702b used in operation 506. The first silicon epitaxial layer is epitaxially grown on the oxide implant layer. In some embodiments, the first silicon epitaxial layer is epitaxially grown using a chemical vapor deposition (CVD) technique (e.g., metal organic chemical vapor deposition (MOCVD)), atmospheric pressure chemical vapor deposition (APCVD), low pressure chemical vapor deposition (LPCVD), ultra high vacuum chemical vapor deposition (UHVCCVD), molecular beam epitaxy (MBE), atomic layer deposition (ALD), other suitable methods, or a combination thereof.

[0150] like Fig. 7E In the example shown, the first mask pattern 702a covers the upper surface of the sidewall portion 706b of the oxide implant layer 706 to prevent the first silicon epitaxial layer from being grown thereon.

[0151] like Figure 7F In the example shown, a first silicon epitaxial layer 708 is formed on the oxide implant layer 706. The first silicon epitaxial layer 708 has a bottom portion 708a and a sidewall portion 708b. The sidewall portion 708b and the bottom portion 708a define the following: Figure 1B In some embodiments, the angle α is greater than 85 degrees. In one example, the angle α is 90 degrees. In another example, the angle α is 100 degrees. In another example, the angle α is 110 degrees. In another example, the angle α is 120 degrees.

[0152] In operation 510, an annealing process is performed. In one embodiment, the annealing process is a thermal annealing process. In one example, the temperature of the thermal annealing process ranges from 900° C. to 1100° C. After the thermal annealing process, the oxygen in the oxygen implant layer (introduced in operation 506) reacts with the silicon in the oxygen implant layer to form silicon dioxide. Therefore, the oxygen implant layer is converted into a silicon dioxide layer.

[0153] like Figure 7G The example shown, Figure 7F The illustrated oxide implant layer 706 is transformed into a buried sacrificial structure 110. The buried sacrificial structure 110 includes a bottom portion 114 and a side portion 112 corresponding to the bottom portion 706a and the sidewall portion 706b of the oxide implant layer 706, respectively.

[0154] In operation 512, a second silicon epitaxial layer is generated. The second silicon epitaxial layer is epitaxially grown on the first silicon epitaxial layer. In some implementations, the second silicon epitaxial layer is epitaxially grown using chemical vapor deposition (CVD) techniques (e.g., metal organic chemical vapor deposition, atmospheric pressure chemical vapor deposition, low pressure chemical vapor deposition (LPCVD), ultra high vacuum chemical vapor deposition (UHVCCVD)), molecular beam epitaxy (MBE), atomic layer deposition (ALD), other suitable methods, or combinations thereof.

[0155] like Figure 7H In the example shown, the second silicon epitaxial layer 710 is formed on the first silicon epitaxial layer 708 and fills the first silicon epitaxial layer 708 with the second silicon epitaxial layer 710. Figure 7G The remaining portion of the trench 704 is shown. The second silicon epitaxial layer 710 (eg Figure 7H The upper surfaces of the first epitaxial silicon layer 708 and the second epitaxial silicon layer 710 may be planarized by a subsequent planarization process, which will be discussed below.

[0156] In operation 514, a chemical mechanical planarization (CMP) process is performed. The chemical mechanical planarization process is performed on the upper surface of the semiconductor substrate. After operation 514, a portion of the second metal epitaxial layer outside the trench or exceeding the upper surface of the semiconductor substrate is removed.

[0157] like Fig.7IIn the example shown, the upper surface of the wafer substrate 102 is planarized. Therefore, the buried sacrificial structure 110 is formed on the wafer substrate 102. The first silicon epitaxial layer 708 and the second silicon epitaxial layer 710 together form a die substrate 120, which is partially surrounded and surrounded by the buried sacrificial structure 110. The upper surface 117 of the die substrate 120 is coplanar with the upper surface 115 of the wafer substrate 102 and the side portion 112 of the buried sacrificial structure 110. In the horizontal direction, the side portion 112 of the buried sacrificial structure 110 surrounds the die substrate 120. Although only one buried sacrificial structure 110 is extended Fig.7I It should be understood that a plurality of buried sacrificial structures are fabricated in the wafer substrate 102 , and each buried sacrificial structure 110 may correspond to a die to be grown on the die substrate 120 and above a bottom portion 114 of the buried sacrificial structure 110 .

[0158] exist Figure 4 In operation 404, a plurality of dies are generated and disposed respectively above the plurality of buried sacrificial structures. Figure 7J In the example shown, the die 103 is grown on top of each die substrate 120. In some embodiments, the integrated circuit element 104 is grown in the die substrate 120, and the multi-layer interconnect structure 106 is subsequently grown on the integrated circuit element. The first passivation layer 132 is grown on the top metallization layer of the multi-layer interconnect structure 106. The integrated circuit element 104, the multi-layer interconnect structure 106, and the first passivation layer 132 can be part of the die 103.

[0159] exist Figure 4 In operation 406, the plurality of dies are separated or separated by the plurality of buried sacrificial structures to generate individual dies. Figure 6 In the example shown, operation 406 includes operation 602, operation 604, operation 606, operation 608, operation 610, operation 612, operation 614, operation 616, operation 618, operation 620, operation 622, and operation 624. More operations may be implemented. In addition, it is to be understood that various operations described above Figure 6 The order of operations is provided for reference only, and therefore, other implementations may use different orders. These different operation orders are all included in the scope of this embodiment.

[0160] In operation 602, a second passivation layer is provided. Figure 7K As shown, the second passivation layer 134 is grown on the first passivation layer 132 and covers the metal lines of the uppermost metallization layer of the multi-layer interconnect structure 106 .

[0161] In operation 604, an opening is created in the second metal passivation layer. Figure 7KIn the example shown, the opening 720 is formed in the second passivation layer 134. The opening 720 is vertically aligned to the upper surface 115 of the side portion 112 of the buried sacrificial structure 110. The opening 720 may be formed by removing a portion of the second passivation layer 134 through a patterning and etching process.

[0162] In operation 606, a cutting groove is generated to expose the upper surface of the buried sacrificial structure. Figure 7L In the illustrated example, a dicing groove 202 is generated in the wafer substrate 102 for each die 103. The dicing groove 202 can be generated by a patterning and etching process, and multiple dicing grooves can be generated simultaneously or by the same process. In one example, a photoresist layer is used, and a mask with a desired groove pattern is aligned and exposed to light to expose specific areas of the photoresist. The exposed photoresist is then developed to produce a mask that can protect the desired dicing groove area in the wafer 700. An etching process, such as reactive ion etching (RIE) or deep reactive ion etching (DRIE) can be used to remove unprotected material on the wafer 700. The etching gas used depends on the material to be etched, which can be a fluorine-based or chlorine-based gas. The etching process continues until the upper surface 115 of the side portion 112 of the buried sacrificial structure 110 is exposed. The dicing groove 202 extends from the upper open end 204 to the lower open end 206 and is defined by an inner sidewall 212 and an outer sidewall 208. The lower open end 206 is connected to the upper surface 115 of the side portion 112 of the buried sacrificial structure 110. It should be noted that the inner sidewall 212 will become the outer surface of the die 103 portion after the separation process.

[0163] In operation 608, a third passivation layer is generated. Figure 7M In the example shown, the third passivation layer 136 is disposed on the second passivation layer 134. A portion of the third passivation layer 136, labeled 136a, is disposed on the inner sidewall 212 and the outer sidewall 208 of the cutting groove 202. A portion of the third passivation layer 136, labeled 136b, is generated at the lower opening end 206 and is disposed on the upper surface of the side portion 112 of the buried sacrificial structure 110. As described above, the portion 136a can serve as a protective layer to protect the inner sidewall 212 (which will become the outer surface of the portion of the die 103) during the subsequent manufacturing process.

[0164] In operation 610, the third passivation layer is etched to expose the upper surface of the buried sacrificial structure. Figure 7NIn the example shown, portion 136b of the third passivation layer 136 is removed to expose the upper surface of the side portion 112 of the buried sacrificial structure 110. The etching process can be performed using one or more etchants to remove portion 136b of the third passivation layer 136. Examples of etching techniques can include wet etching, dry etching, plasma etching, reactive ion etching, or other suitable methods. The selection of etchants and etching parameters (e.g., etching time, plasma parameters (if it is a plasma-based etching), wet etching chemistry, etc.) can be optimized to remove portion 136b of the third passivation layer 136 and leave portion 136a intact on the inner sidewall 212 and the outer sidewall 208.

[0165] In operation 612, the wafer is attached to the pre-etched handle. Fig.7O In the example shown, the wafer 700 includes a plurality of dies 103 that are closely stacked in the XY plane. Figure 1B The semiconductor wafer 100 shown has a similar approach. It is to be understood that Fig.7O The wafer 700 in the figure is for exemplary purposes only, and the total number of dies 103 on the wafer 700 may vary in another embodiment. The wafer 700 is attached to the pre-etched handle 730. The pre-etched handle 730 includes a wafer carrier 732, a wafer carrier 736, and a wafer support 734 (also known as a "wafer chuck" or "wafer fixing fixture"). The wafer carrier 732 is detachably attached to the upper surface of the wafer (i.e., the surface where the passivation layer 132 / passivation layer 134 / passivation layer 136 is exposed) and is configured to securely support the upper surface of the wafer. The wafer carrier 732 can have a flat surface or a groove that matches the size and shape of the wafer 700, and can provide stability and protection during handling and manufacturing. The wafer support 734 is detachably attached to the periphery of the wafer 700 and is configured to securely support the wafer 700 to the desired area by clamping or locking the wafer 700. The wafer support 734 provides stability and prevents any movement or sliding of the wafer 700 during the manufacturing process (such as etching or cleaning). The wafer lower carrier 736 is removably attached to the back side or lower surface of the wafer substrate 102 and is configured to support the back side or lower surface of the wafer 700. Similar to the wafer carrier 732, the wafer lower carrier 736 can conform to the shape or size of the wafer 700 and prevent damage or warping of the wafer during handling and manufacturing. The wafer carrier 732 and the wafer lower carrier 736 can be composed of any suitable material, such as semiconductor, glass or metal. In some embodiments, the wafer carrier 732 and the wafer lower carrier 736 can respectively include an adhesive layer (not shown) that is used to removably adhere to the upper surface of the wafer 700 and the lower surface of the wafer substrate 102.

[0166] In some embodiments, the wafer carrier 732 includes a plurality of holes 740 extending through the entire thickness of the wafer carrier 732. The plurality of holes 740 may be of relatively small dimensions (i.e., substantially smaller than the horizontal dimensions of the wafer 700). The number of holes 740 may vary depending on the design requirements. The holes 740 provide a path for external etchant to be introduced into the dicing grooves 202 in subsequent steps. The holes 740 may help with alignment and orientation of the wafer 700 and may provide clear visibility and reference points to properly position the wafer carrier 732 to the wafer 700. The holes 740 may also provide access for external sensors used to communicate with the wafer 700 for detection and control during various process steps. The plurality of holes 740 in the wafer carrier 732 may help reduce the total contact area between the wafer 700 and the wafer carrier 732, which may facilitate removal of the wafer carrier 732 and the separated dies 103 in subsequent steps.

[0167] In operation 614, the buried sacrificial layer structure is removed. Figure 7P In the illustrated example, the buried sacrificial structure 110 can be removed by a selective etching process by introducing one or more etchants into the saw grooves 202 to selectively etch away the buried sacrificial structure 110 and leave the wafer substrate 102 and the die substrate 120 intact. The selective etching can be performed by using an etchant that is selective to the material of the buried sacrificial structure 110 (e.g., SiO2) to minimize the effect on the surrounding materials (e.g., silicon of the wafer substrate 102 and silicon carbide of the die substrate 120). Substrate voids 742 are generated after the buried sacrificial structure 110 is removed. The substrate voids 742 are substantially similar in shape and size to the buried sacrificial structure 110 and are spatially connected to the saw grooves 202. The substrate voids 742 and the saw grooves 202 can be combined to form saw voids 744 that surround and partially cover the die substrate 120. Therefore, each die 103 is separated from the wafer substrate 102 by a corresponding saw void 744, but it is still attached to the wafer carrier 732.

[0168] In operation 616, the wafer carrier and wafer support are removed. Figure 7Q In the example shown, the wafer lower carrier 736 and the wafer support 734 are removed. The wafer substrate 102 and the wafer support 734 bonded to the wafer lower carrier 736 are also removed. Therefore, before the wafer lower carrier 736 and the wafer support are removed, the individual dies 103 remain bonded to the upper carrier 732 in the same pattern as they are arranged on the wafer 700. The individual dies 103 are separated and isolated from each other.

[0169] In operation 618, the die substrates of the plurality of dies are bonded to the bottom tape. The bottom tape is also referred to as the back tape. As described above, the die substrates of the dies can have a relatively small thickness compared to the dies made by the conventional sawing and macro-breaking processes. The bottom tape can provide mechanical support and protection for the relatively thin dies 103 in subsequent process steps. Figure 7R In the example shown, the bottom tape 746 is removably adhered to the back portion of the die substrate 120 of the die 103 .

[0170] In operation 620, the wafer carrier is removed. Depending on the type of adhesive layer used to bond the wafer carrier to the die top surface, the wafer carrier may be removed by a mechanical removal process, a vacuum release process, a thermal release process, a chemical release process, or any combination thereof.

[0171] In operation 622, the passivation layer on the die is removed to expose the metal lines of the uppermost die. The passivation layer can be removed by performing an etching process. In some embodiments, a wet etching process is performed and a chemical solution is used as an etchant to remove the passivation layer. In some embodiments, a dry etching process using plasma is used. Figure 7R In the example shown, the wafer carrier 732 is removed and the bottom tape 746 is removably bonded to the back surface of the die substrate 120. The second passivation layer (e.g., any of the removed third passivation layer 136, the second passivation layer 134, and a portion of the first passivation layer 132) of each die 103 is removed to expose the top metal line (i.e., the top of the metallization layer metal lines of the multi-layer interconnect structure 106). Before the bottom tape 746 is removed, the top of the exposed metal line can be used for die performance testing.

[0172] In operation 624, die performance testing is performed and die with good test results are removed. In some embodiments, die performance testing is performed while the die is still attached to the bottom tape. Dies that fail the performance test are removed from the bottom tape. Once the die is tested and characterized, a separation process is performed by removing the bottom tape to obtain individually separated good die.

[0173] The die obtained from the separation process has an outer surface, which is generated by the inner sidewall 212 of the cutting groove 202 and the sidewall 116 and the lower surface of the die substrate 120, such as Figure 2BAs shown. The outer surface of the separated grain is generally smoother than the grain obtained from the conventional giant cutting process. As described above, the etchant used in the process to generate the cutting groove (i.e., the cutting groove 202) and remove the buried sacrificial structure (i.e., the buried sacrificial structure 110) may have an isotropic etching phenomenon. Therefore, the material is removed uniformly in all directions, which can produce a smooth and flat etching profile and minimize surface roughness. In addition, the selectivity of the etchant allows for precise control in a gentler method during the etching process, so that a smooth and clean surface is maintained in the desired area. In contrast, sawing involves using a giant knife or laser to cut along the cutting path, which always causes some surface roughness due to the physical cutting action and may result in residues or debris that are difficult to clean. In some embodiments, the sidewalls of the grain 103 have a roughness R a (Arithmetic mean roughness) less than 1 μm, less than 500 nm, less than 200 nm, less than 100 nm, less than 50 nm, less than 10 nm or less than 5 nm.

[0174] It should be understood that the present method using buried sacrificial structures is not limited to the die separation shown and described herein. The use of buried sacrificial structures can have a wider range of applications in semiconductor manufacturing and packaging applications, including but not limited to micro-electromechanical systems (MEMS) and three-dimensional integrated circuit (3DIC) packaging applications.

[0175] For example, in MEMS applications, the use of buried sacrificial layers can provide significant benefits in the process of suspended or movable structures, allowing microsensors, microactuators and other micro-sized components to be built directly on the buried sacrificial junction layer. Unlike the traditional method of using a bonded handle wafer (i.e., upper wafer) and a carrier wafer (i.e., lower wafer) in the process of manufacturing MEMS components, which requires a carrier wafer and then a mechanical separation method to remove the MEMS components from the carrier, the use of buried sacrificial layers does not require a mechanical separation process. As the sacrificial layer can be selectively etched to allow the suspended or movable structures of the MEMS components to be released while maintaining their intended functionality, this allows the sacrificial layer to be selectively etched, providing a non-destructive and efficient means of removing the MEMS components. This can effectively reduce the risk of damage to the MEMS components occurring during the mechanical removal process.

[0176] Likewise, in 3D integrated circuit packaging applications, the use of buried sacrificial layers can enable special shape designs (e.g. FIG. 3A to FIG. 3BDies with special shapes (such as those shown) can be manufactured. These special shaped dies can be used to achieve special functions or provide special uses. Another benefit of using buried sacrificial layers in 3D IC packaging is that ultra-thin IC chips can be manufactured. The thickness of each die can be significantly reduced compared to traditional dies. The thickness of the die can be as small as 1μm to 200μm, while typical conventional die thickness ranges from 100μm to 600μm. Therefore, the total thickness of the 3D IC structure can be greatly reduced. The reduction in the total thickness of the 3D IC structure can improve packaging efficiency. Thin dies can reduce the total footprint of the 3D IC structure and allow for more compact and space-efficient integration. In addition, the use of buried sacrificial layers in 3D IC packaging applications can allow greater design flexibility. Special shaped dies can be customized to meet special specifications and allow for optimization of the functionality of the packaged product and its overall performance.

[0177] Summarize.

[0178] According to at least one embodiment of the present disclosure, a semiconductor wafer has a plurality of die regions divided by a die spacing region, the semiconductor wafer comprising: a wafer substrate; a plurality of dies corresponding to the plurality of die regions and disposed on the wafer substrate, each of the plurality of dies being located in a corresponding one of the plurality of die regions and comprising: a die substrate extending vertically from an upper surface to a lower surface and comprising a side wall circumferentially connecting the upper surface and the lower surface; an integrated circuit element disposed in the die substrate; and a multi-layer interconnect structure disposed on the integrated circuit element and electrically connected to the integrated circuit element; and a plurality of buried sacrificial structures corresponding to the plurality of dies and embedded in the wafer substrate, each of the plurality of buried sacrificial structures surrounding the corresponding die substrate and disposed between a corresponding one of the plurality of dies and the wafer substrate, wherein the buried sacrificial structure further comprises: a bottom portion disposed in the die region and in contact with the lower surface of the die substrate; and a side portion circumferentially connected to the bottom portion, the side portion being located in the die spacing region surrounding the corresponding one of the plurality of dies and disposed on the side wall of the die substrate, wherein the side portion has an upper surface and is coplanar with the upper surface of the die substrate.

[0179] In some embodiments, the side portion and the bottom portion of the buried sacrificial structure have a thickness ranging from about 0.2 μm to about 10 μm.

[0180] In some embodiments, the buried sacrificial structure comprises silicon oxide.

[0181] In some embodiments, the wafer substrate and the die substrate are made of the same material.

[0182] In some embodiments, the wafer substrate comprises silicon (Si), and the die substrate comprises silicon carbide (SiC).

[0183] In some embodiments, the die substrate has an angle (α) generated between the side portion and the bottom portion, and the angle (α) is at least 85 degrees.

[0184] In some embodiments, the die substrate has an angle (α) generated between the side portion and the bottom portion, and the angle (α) is at least 120 degrees.

[0185] In some embodiments, the die substrate has a thickness ranging from 2 μm to 200 μm.

[0186] In some embodiments, the grain spacing region between two adjacent grain regions is less than 20 μm.

[0187] In some embodiments, a plurality of cutting grooves are further included corresponding to the plurality of grains, one of the plurality of cutting grooves is located in one of the plurality of grain spacing regions and surrounds a corresponding one of the plurality of grains, wherein the cutting groove vertically extends from an upper opening end to a lower opening end and horizontally extends from an inner side wall to an outer side wall, the lower opening end is circumferentially connected to the side portion of the buried sacrificial structure, and the upper surface of the side portion of the buried sacrificial structure is exposed to the cutting groove.

[0188] In some embodiments, the upper opening is larger in horizontal dimension than the lower opening.

[0189] In some embodiments, the lower opening is larger in horizontal dimension than the upper surface of the side portion of the buried sacrificial structure.

[0190] In some embodiments, the cutting groove further includes a passivation layer disposed on the inner sidewall and the outer sidewall.

[0191] In some embodiments, the inner sidewall has a surface roughness less than 1 μm.

[0192] According to at least one embodiment of the present disclosure, a method for manufacturing a semiconductor wafer having a buried sacrificial structure includes: generating a plurality of grooves on a wafer substrate, each of the plurality of grooves having a bottom surface and a side wall circumferentially connected to the bottom surface; generating an oxide implant layer on each of the plurality of grooves; generating a first silicon epitaxial layer on the oxide implant layer to fill a portion of the groove; performing an annealing process to transform the oxide implant layer into a buried sacrificial structure, the buried sacrificial structure having a bottom portion disposed on the lower surface of the groove and a side portion circumferentially connected to the bottom portion and disposed on the side wall of the groove; generating a second silicon epitaxial layer on the buried sacrificial structure to fill a remaining portion of the groove, wherein the first silicon epitaxial layer and the second silicon epitaxial layer generate a die substrate surrounded by the buried sacrificial layer; and performing a chemical mechanical planarization process to generate substantially planar upper surfaces of the die substrate and the side wall portion of the buried sacrificial structure.

[0193] In some embodiments, the method further includes: growing a plurality of dies on the wafer substrate, wherein each of the plurality of dies is grown on the corresponding die substrate and vertically aligned with the bottom portion of the buried sacrificial structure.

[0194] In some embodiments, the method further includes: forming a passivation layer on the upper surfaces of the plurality of grains.

[0195] According to at least one embodiment of the present disclosure, a method includes: providing a semiconductor wafer, the semiconductor wafer having a plurality of die regions separated by a die spacing region and including: a wafer substrate; a plurality of die corresponding to the plurality of die regions and disposed on the wafer substrate, each of the plurality of die being located in a corresponding one of the plurality of die regions and including: a die substrate extending vertically from an upper surface to a lower surface and including a side wall circumferentially connecting the upper surface and the lower surface; and an integrated circuit element disposed on the die substrate; a plurality of buried sacrificial structures corresponding to the plurality of die, each buried sacrificial structure being embedded in the wafer substrate and disposed between the corresponding die and the wafer substrate, and including: a bottom portion located in the die region; and a side portion circumferentially connected to the bottom portion, the side portion being located in the die spacing region and surrounding the side wall of the corresponding die substrate; generating a plurality of cutting grooves, each of the plurality of cutting grooves being located in the die spacing region surrounding the corresponding die, wherein the cutting grooves vertically extend from an upper opening end to a lower opening end and horizontally extend from an inner side wall to an outer side wall, the lower opening end being circumferentially connected to the side portion of the buried sacrificial structure; attaching the wafer substrate to a pre-etched handle; and performing an etching process to remove the plurality of buried sacrificial structures to generate a plurality of subsurface voids, wherein each of the subsurface voids and the corresponding cutting grooves connected to the subsurface voids form a continuous cutting void that separates the corresponding die from the wafer substrate.

[0196] In some embodiments, the method further comprises: after depositing a passivation layer on the inner sidewall and the outer sidewall of each trench, adhering the wafer substrate to the pre-etched handle.

[0197] In some embodiments, the pre-etched handle further comprises: an on-wafer carrier detachably adhered to an upper surface of the plurality of dies; and an on-wafer carrier detachably adhered to a back surface of the wafer substrate.

[0198] According to at least one embodiment of the present disclosure, a semiconductor wafer has a plurality of die regions divided by a die spacing region, the semiconductor wafer comprising: a wafer substrate; a plurality of dies corresponding to the die regions and disposed on the wafer substrate, each of the dies being located in a corresponding one of the die regions and comprising: a die substrate extending vertically from an upper surface to a lower surface and comprising a side wall circumferentially connecting the upper surface and the lower surface; an integrated circuit element disposed in the die substrate; and a multi-layer interconnect structure disposed on the integrated circuit element and electrically connected to the integrated circuit element ; and a plurality of buried sacrificial structures corresponding to the grains and embedded in the wafer substrate, each of the buried sacrificial structures surrounds the corresponding grain substrate and is disposed between a corresponding one of the grains and the wafer substrate, the buried sacrificial structure comprises silicon oxide, wherein the buried sacrificial structure further comprises: a bottom portion, disposed in the grain region and in contact with the lower surface of the grain substrate; and a side portion, circumferentially connected to the bottom portion, the side portion is located in the grain spacing region surrounding the corresponding one of the grains and disposed on the side wall of the grain substrate, wherein the side portion has an upper surface and is coplanar with the upper surface of the grain substrate.

[0199] According to at least one embodiment of the present disclosure, a semiconductor wafer has a plurality of die regions divided by a die spacing region, the semiconductor wafer comprising: a wafer substrate; a plurality of dies corresponding to the die regions and disposed on the wafer substrate, each of the dies being located in a corresponding one of the die regions and comprising: a die substrate extending vertically from an upper surface to a lower surface and comprising a side wall circumferentially connecting the upper surface and the lower surface; an integrated circuit element disposed in the die substrate; and a multi-layer interconnect structure disposed on the integrated circuit element and electrically connected to the integrated circuit element; and a plurality of buried sacrificial structures corresponding to the die substrate. The buried sacrificial structure is disposed to the die and embedded in the wafer substrate, each of the buried sacrificial structures surrounds the corresponding die substrate and is disposed between a corresponding one of the die and the wafer substrate, wherein the buried sacrificial structure further comprises: a bottom portion, disposed in the die region and in contact with the lower surface of the die substrate; and a side portion, circumferentially connected to the bottom portion, the side portion is located in the die spacing region, surrounds the corresponding one of the die and is disposed on the side wall of the die substrate, wherein the side portion has an upper surface and is coplanar with the upper surface of the die substrate, wherein the die substrate has an angle (α) generated between the side portion and the bottom portion, and the angle (α) is at least 120 degrees.

[0200] The foregoing summarizes the features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art will appreciate that they may readily use the present disclosure as a basis for designing or modifying other processing procedures and structures for carrying out the same purposes and / or achieving the same advantages of the embodiments described herein. Those skilled in the art will also appreciate that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may be variously modified, substituted, and altered without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor wafer having a plurality of die regions separated by a die spacing region, characterized in that: Include: a wafer substrate; A plurality of dies corresponding to the die regions and disposed on the wafer substrate, each of the dies being located in a corresponding one of the die regions and comprising: A die substrate vertically extending from an upper surface to a lower surface and comprising a side wall circumferentially connecting the upper surface and the lower surface; an integrated circuit element disposed in the die substrate; and A multi-layer interconnect structure is disposed on the integrated circuit element and electrically connected to the integrated circuit element; as well as A plurality of buried sacrificial structures corresponding to the die and embedded in the wafer substrate, each of the buried sacrificial structures surrounds the corresponding die substrate and is disposed between a corresponding one of the die and the wafer substrate, wherein the buried sacrificial structures further include: a bottom portion disposed in the die region and in contact with the lower surface of the die substrate; and A side portion is circumferentially connected to the bottom portion, the side portion is located in the die spacing region around the corresponding one of the dies and disposed on the sidewall of the die substrate, wherein the side portion has an upper surface and is coplanar with the upper surface of the die substrate.

2. The semiconductor wafer according to claim 1, wherein: The side portions and the bottom portion of the buried sacrificial structure have a thickness ranging from about 0.2 μm to about 10 μm.

3. The semiconductor wafer according to claim 1, wherein: The buried sacrificial structure comprises silicon oxide.

4. The semiconductor wafer according to claim 1, wherein: The wafer substrate and the die substrate are made of the same material.

5. The semiconductor wafer according to claim 1, wherein: The wafer substrate comprises silicon (Si), and the die substrate comprises silicon carbide (SiC).

6. The semiconductor wafer according to claim 1, wherein: The die substrate has an angle (α) generated between the side portion and the bottom portion, and the angle (α) is at least 85 degrees.

7. The semiconductor wafer according to claim 6, wherein: The die substrate has an angle (α) generated between the side portion and the bottom portion, and the angle (α) is at least 120 degrees.

8. The semiconductor wafer according to claim 1, wherein: The die substrate has a thickness ranging from 2 μm to 200 μm.

9. A semiconductor wafer having a plurality of die regions separated by a die spacing region, characterized in that: Include: a wafer substrate; A plurality of dies corresponding to the die regions and disposed on the wafer substrate, each of the dies being located in a corresponding one of the die regions and comprising: A die substrate vertically extending from an upper surface to a lower surface and comprising a side wall circumferentially connecting the upper surface and the lower surface; an integrated circuit element disposed in the die substrate; and A multi-layer interconnect structure is disposed on the integrated circuit element and electrically connected to the integrated circuit element; as well as A plurality of buried sacrificial structures corresponding to the die and embedded in the wafer substrate, each of the buried sacrificial structures surrounds the corresponding die substrate and is disposed between a corresponding one of the die and the wafer substrate, the buried sacrificial structures comprising silicon oxide, wherein the buried sacrificial structures further comprise: a bottom portion disposed in the die region and in contact with the lower surface of the die substrate; and A side portion is circumferentially connected to the bottom portion, the side portion is located in the die spacing region around the corresponding one of the dies and disposed on the sidewall of the die substrate, wherein the side portion has an upper surface and is coplanar with the upper surface of the die substrate.

10. A semiconductor wafer having a plurality of die regions separated by a die spacing region, characterized in that: Include: a wafer substrate; A plurality of dies corresponding to the die regions and disposed on the wafer substrate, each of the dies being located in a corresponding one of the die regions and comprising: A die substrate vertically extending from an upper surface to a lower surface and comprising a side wall circumferentially connecting the upper surface and the lower surface; an integrated circuit element disposed in the die substrate; and A multi-layer interconnect structure is disposed on the integrated circuit element and electrically connected to the integrated circuit element; as well as A plurality of buried sacrificial structures corresponding to the die and embedded in the wafer substrate, each of the buried sacrificial structures surrounds the corresponding die substrate and is disposed between a corresponding one of the die and the wafer substrate, wherein the buried sacrificial structures further include: a bottom portion disposed in the die region and in contact with the lower surface of the die substrate; and A side portion is circumferentially connected to the bottom portion, the side portion is located in the die spacing area around the corresponding one of the dies and is disposed on the side wall of the die substrate, wherein the side portion has an upper surface and is coplanar with the upper surface of the die substrate, wherein the die substrate has an angle (α) generated between the side portion and the bottom portion, and the angle (α) is at least 120 degrees.

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