Metal interconnection structure and semiconductor device

Abstract

According to the metal interconnection structure and the semiconductor device provided by the utility model, the first structure is arranged in the M layers of metal interconnection units, and the metal interconnection layer of the metal interconnection unit at the lower layer extends into the dielectric layer of the adjacent metal interconnection unit at the upper layer; the height of the metal interconnection line of each layer is the preset height and cannot be changed, so that compared with an existing metal interconnection structure, the thickness of the dielectric layer of the metal interconnection unit located at the lowermost layer is thinned by the first structure; the thickness of the thinned dielectric layer is transmitted to the dielectric layers of other metal interconnection units in the first structure, so that the thickness of the dielectric layers of other metal interconnection units in the first structure is increased relative to the thickness of an insulating layer of an existing metal interconnection unit; the dielectric layer with the increased thickness can effectively improve and relieve the stress generated by the overlarge size of the top metal interconnection structure on the lower metal interconnection unit, and meanwhile, the total thickness of the dielectric layer in the metal interconnection structure cannot be increased.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductor manufacturing, in particular to a metal interconnection structure and a semiconductor device. Background Art

[0002] In the semiconductor back-end process, a multi-layer metal interconnect unit can be arranged on the semiconductor substrate according to different needs. Each layer of the metal interconnect unit includes a metal interconnect line and an insulating layer. Grooves and through holes are formed in the insulating layer, and then metal is deposited in the grooves and through holes. The deposited metal is the metal interconnect line. The metal filled in the groove is called the metal interconnect layer, and the metal filled in the through hole is called the metal interconnect through hole. Copper or aluminum is generally used as the metal interconnect line material.

[0003] like Figure 1 As shown, in the prior art, when forming the top metal interconnect structure 20, due to the large size of the top metal interconnect line 200, especially the top metal interconnect layer 201, such as the thickness, area, etc., it is easy to generate large stress, thereby causing the metal interconnect line thereunder, especially the metal interconnect layer 222 therein, to crack. In severe cases, the metal interconnect layer 222, including the metal interconnect line and / or the dielectric layer, may even break, thereby reducing the product yield.

[0004] like Figure 2 As shown, a multilayer metal interconnect structure 21 below the conventional top metal interconnect structure 20 includes a plurality of metal interconnect units 22 stacked in sequence, each metal interconnect unit 22 includes a metal interconnect line 220 and an insulating layer 221, and the upper and lower surfaces of the insulating layer 221 are both flat surfaces, and the metal interconnect line 220 is filled in the grooves and through holes in the insulating layer 221. It is possible to consider increasing the thickness of the insulating layer 221 in each metal interconnect unit 22 to alleviate the stress damage caused by the top metal interconnect structure 20, but this will inevitably lead to a higher height of the metal interconnect through hole 223 and / or the metal interconnect layer 222 in the metal interconnect line 220, increase the difficulty of the metal filling process, and increase the device volume, which is not conducive to the miniaturization requirements of semiconductor devices. Utility Model Content

[0005] In view of the shortcomings of the prior art described above, the purpose of the utility model is to provide a metal interconnect structure and a semiconductor device, which are used to solve the problems in the prior art of alleviating the stress damage caused by the top metal interconnect structure to the insulating layer by thickening the thickness of each layer of the metal interconnect structure, resulting in the height of the metal interconnect through holes and / or the metal interconnect layer in the metal interconnect line becoming higher, increasing the difficulty of the metal filling process, and increasing the size of the device, which is not conducive to the miniaturization of semiconductor devices.

[0006] In order to achieve the above-mentioned object and other related objects, the utility model provides a metal interconnection structure, which comprises:

[0007] M layers of metal interconnection units are disposed on a semiconductor substrate and are adjacent to and stacked in sequence, M≥2;

[0008] Each layer of the metal interconnection unit includes a metal interconnection line and a dielectric layer; wherein the metal interconnection line includes a metal interconnection through hole located in a lower layer and a metal interconnection layer located in an upper layer, and the height of the metal interconnection line in each layer is the same, the metal interconnection line is at least partially covered by the dielectric layer, and the lower surface of the metal interconnection line of each layer of the metal interconnection unit is at least partially flush with the lower surface of the dielectric layer thereof;

[0009] The metal interconnection lines of the metal interconnection units adjacent to each other are electrically connected in contact;

[0010] The metal interconnection unit of the M layer includes at least one first structure, wherein the first structure includes: at least two layers of metal interconnection units adjacent to each other, and at least a portion of the metal interconnection layer of the metal interconnection unit located at the lower layer extends into at least a portion of the dielectric layer of the metal interconnection unit adjacent to the upper layer to be covered;

[0011] The dielectric layer of the lowest metal interconnection unit in the first structure has the thinnest thickness.

[0012] Optionally, the first structure is arranged on an upper portion of the metal interconnection unit of the M layer.

[0013] Optionally, the metal interconnect unit of layer M also includes at least one second structure, the second structure including: a layer of the metal interconnect unit, and the upper surface and lower surface of the metal interconnect line of the metal interconnect unit are respectively flush with the upper surface and lower surface of the dielectric layer of the metal interconnect unit.

[0014] Furthermore, the heights of all the metal interconnection lines in the metal interconnection unit of the M layer are set to be the same.

[0015] Furthermore, in the first structure, the metal interconnection layer of the metal interconnection unit at the bottom extends into the dielectric layer of the metal interconnection unit adjacent to it at a preset height of 10% to 70% of the thickness of the metal interconnection line of the metal interconnection unit at the bottom.

[0016] Furthermore, the metal interconnection unit of the M layer is only configured as one of the first structures.

[0017] Furthermore, in the first structure, a preset height of the metal interconnection layer of the metal interconnection unit located at the lower layer extending into the dielectric layer of the metal interconnection unit adjacent to it at the upper layer gradually decreases from bottom to top.

[0018] Furthermore, in the first structure, a preset height of the metal interconnection layer of the metal interconnection unit located at the lower layer extending into the dielectric layer of the metal interconnection unit adjacent to it at the upper layer gradually decreases in an arithmetic progression from bottom to top.

[0019] Optionally, the dielectric layer of each metal interconnect unit includes a metal dielectric layer and an etch stop layer.

[0020] The utility model also provides a semiconductor device, the semiconductor device comprising:

[0021] The metal interconnect structure as described in any one of the above;

[0022] a semiconductor substrate located below the metal interconnect structure;

[0023] A top metal interconnection structure is located above the metal interconnection structure, wherein the top metal interconnection structure includes a top metal interconnection line and a top dielectric layer, and the top metal interconnection line is electrically connected to at least part of the metal interconnection lines of the metal interconnection structure.

[0024] As described above, the metal interconnect structure and semiconductor device of the utility model are provided with a first structure in the M-layer metal interconnect unit, and the first structure extends the metal interconnect layer of the metal interconnect unit located at the lower layer into the dielectric layer of the upper metal interconnect unit adjacent thereto, and because the height of the metal interconnect line of each layer is a preset height and cannot be changed, compared with the structure in which the metal interconnect line in each metal interconnect unit of the existing metal interconnect structure is flush with the upper surface of the insulating layer, the first structure of the utility model thins the thickness of the dielectric layer of the metal interconnect unit located at the lowest layer in the first structure, so as to transfer the thinned dielectric layer thickness to the dielectric layers of other metal interconnect units in the first structure, so that the thickness of the dielectric layer of other metal interconnect units in the first structure is thicker than the thickness of the insulating layer of the existing metal interconnect unit, and the dielectric layer with increased thickness can effectively improve and relieve the stress generated by the excessive size of the upper top metal interconnect structure on the lower metal interconnect unit. Therefore, the first structure can be provided at a position where the metal interconnect layer is prone to cracking, so as to reduce or even avoid the risk of cracking or even breaking of the metal interconnect layer in the metal interconnect structure, improve the product yield, and at the same time, will not increase the total thickness of the dielectric layer in the metal interconnect structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 The cross-sectional structure diagram of an example of a top metal interconnection structure in the prior art is shown.

[0026] Figure 2 The cross-sectional structure diagram of a top metal interconnection structure and a metal interconnection structure thereunder is shown as an example in the prior art.

[0027] Figures 3 to 8 Shown is a schematic cross-sectional structure diagram of a metal interconnect structure of the present invention.

[0028] Fig. 9 Shown is a schematic diagram of the cross-sectional structure of a semiconductor device of the present invention.

[0029] Fig.10 and Fig.11 It shows a schematic cross-sectional structure diagram of each step in the method for preparing the second structure in the metal interconnection structure of the present invention.

[0030] Figures 12 to 17 It shows a schematic cross-sectional structure diagram of each step in the method for preparing the first structure in the metal interconnection structure of the present invention.

[0031] Component number description

[0032] 10 Metal Interconnect Structure

[0033] 11 Semiconductor substrate

[0034] 12 Top Metal Interconnect Structure

[0035] 120 Top metal interconnects

[0036] 121 Top metal interconnect vias

[0037] 122 Top metal interconnect layer

[0038] 123 Top dielectric layer

[0039] 13 Metal Interconnect Unit

[0040] 130 Dielectric layer

[0041] 131 Metal Dielectric Layer

[0042] 132 Etch stop layer

[0043] 133 Metal Interconnects

[0044] 134 Metal Interconnect Vias

[0045] 135 Metal Interconnect Layer

[0046] 14 First Structure

[0047] 20 Top Metal Interconnect Structure

[0048] 200 Top metal interconnects

[0049] 201 Top metal interconnect layer

[0050] 202 Top metal interconnect vias

[0051] 21 Metal Interconnect Structure

[0052] 22 Metal Interconnect Unit

[0053] 220 Metal Interconnects

[0054] 221 Insulation layer

[0055] 222 Metal Interconnect Layer

[0056] 223 Metal Interconnect Vias DETAILED DESCRIPTION

[0057] The following is a description of the implementation of the present invention by means of specific embodiments. People familiar with the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification.

[0058] See also Figures 1 to 17 It should be noted that the structures, proportions, sizes, etc. illustrated in the drawings in this specification are only used to match the contents disclosed in the specification for people familiar with this technology to understand and read, and are not used to limit the limiting conditions for the implementation of the utility model, so they have no substantial technical significance. Any modification of the structure, change in the proportion relationship, or adjustment of the size should still fall within the scope of the technical content disclosed by the utility model without affecting the effects and purposes that can be achieved by the utility model. At the same time, the terms such as "upper", "lower", "left", "right", "middle" and "one" quoted in this specification are only for the convenience of description, and are not used to limit the scope of the implementation of the utility model. The change or adjustment of their relative relationship should also be regarded as the scope of the implementation of the utility model without substantially changing the technical content.

[0059] like Figures 3 to 8 As shown, the utility model provides a metal interconnection structure 10, and the metal interconnection structure 10 includes:

[0060] like Figure 3 As shown, M layers of metal interconnection units 13 are arranged adjacently and stacked on the semiconductor substrate 11, where M≥2;

[0061] Each layer of the metal interconnection unit 13 includes a metal interconnection line 133 and a dielectric layer 130; wherein the metal interconnection line 133 includes a metal interconnection through hole 134 located in the lower layer and a metal interconnection layer 135 located in the upper layer, and the height of the metal interconnection line 133 of each layer is set to be the same. For some products, the height of the metal interconnection line 133 of each layer can also be designed according to actual needs, and can be the same or different. The metal interconnection line 133 is at least partially covered by the dielectric layer 130, and the lower surface of the metal interconnection line 133 of each layer of the metal interconnection unit 13 is at least partially flush with the lower surface of its dielectric layer 130; Figure 3 In the figure, for a single metal interconnection unit 13, the bottom of the metal interconnection line 133 is wrapped by a dielectric layer 130, wherein the dielectric layer 130 includes a metal dielectric layer 131 (the metal dielectric layer 131 is usually made of ULK, ultra-lowk, i.e., a porous ultra-low dielectric constant dielectric material layer) and an etch stop layer 132 (usually silicon nitride), i.e., the lower end portion of the metal interconnection unit 13 is wrapped by the etch stop layer 132. The etch stop layer 132 is an etch stop layer at the bottom when forming a metal-filled trench or hole. Figure 3 At least a portion of the bottom of the etch stop layer 132 located below in each metal interconnect unit 13 is flush with the bottom of the metal line 133 in the unit.

[0062] like Figure 3 As shown, the metal interconnection lines 133 of the metal interconnection units 13 of the upper and lower adjacent layers are electrically connected in a contact manner;

[0063] like Figures 4 to 8 As shown, the metal interconnection unit 13 of the M layer includes at least one first structure 14, and the first structure 14 includes: at least two layers of metal interconnection units 13 adjacent to each other, and at least a portion of the metal interconnection layer 135 of the metal interconnection unit 13 located at the lower layer extends into at least a portion of the dielectric layer 130 of the metal interconnection unit 13 adjacent to the upper layer thereof and has been covered by a preset height;

[0064] The dielectric layer 130 of the metal interconnection unit 13 at the bottom of the first structure 14 is the thinnest.

[0065] It should be noted here that the definition of "up and down directions" in this embodiment is defined by the preparation process of the entire metal interconnection structure 10 and the position in the semiconductor device. The metal interconnection structure 10 is located between the semiconductor substrate 11 and the top metal interconnection structure to achieve circuit redistribution and electrical connection between the two, and during the preparation process, the metal interconnection structure 10 is prepared layer by layer on the semiconductor substrate 11, so the "up and down directions" in this embodiment can be understood as the side facing the semiconductor substrate 11 is "down" and the side facing the top metal interconnection structure is "up"; in addition, "the metal interconnection line 133 includes a metal interconnection through hole 134 located in the lower layer and a metal interconnection layer 135 located in the upper layer" refers to the relative position between the metal interconnection through hole 134 and the metal interconnection layer 135 in the metal interconnection line 133 of the same metal interconnection unit 13, and the metal interconnection layer 135 is located above the metal interconnection through hole 134.

[0066] The metal interconnection structure of this embodiment is provided with a first structure in the M-layer metal interconnection unit. The first structure extends the metal interconnection layer of the metal interconnection unit located at the lower layer into the dielectric layer of the upper-layer metal interconnection unit adjacent thereto. Since the height of the metal interconnection line of each layer is a preset height and cannot be changed, compared with the above-mentioned Figure 2 Compared with the structure in which the metal interconnection line 220 in each metal interconnection unit 22 of the metal interconnection structure 21 is flush with the upper surface of the insulating layer 221, the first structure of this embodiment thins the thickness of the dielectric layer of the metal interconnection unit located at the bottom layer in the first structure, so as to transfer the thinned dielectric layer thickness to the dielectric layers of other metal interconnection units in the first structure, thereby making the thickness of the dielectric layers of other metal interconnection units in the first structure relatively Figure 2 The thickness of the insulating layer 221 of the metal interconnection unit is thickened, and the dielectric layer with increased thickness can effectively improve and relieve the stress caused by the excessive size of the top metal interconnection structure on the lower metal interconnection unit. Therefore, the first structure can be set at a position where the metal interconnection layer is prone to cracking, so as to reduce or even avoid the risk of cracking or even breaking of the metal interconnection layer in the metal interconnection structure, improve the product yield, and at the same time will not increase the total thickness of the dielectric layer in the metal interconnection structure.

[0067] The position of the first structure 14 in the metal interconnect structure 10 is not excessively limited, that is, the first structure 14 can be located at the upper part, middle part or lower part of the metal interconnect unit 13 of the M layer; Figure 5 and Figure 6 In the embodiment, the first structure 14 is located at the lower part of the metal interconnection unit 13 of the M layer; Figure 7In the embodiment, the first structure 14 is located at the upper part of the metal interconnection unit 13 of the M layer; of course, the first structure 14 can also be located at the middle part of the metal interconnection unit 13 of the M layer. In addition, the number of the first structures 14 in the metal interconnection structure 10 is not excessively limited. Figures 3 to 8 In the embodiment, one first structure 14 is provided in the metal interconnect structure 10; of course, the metal interconnect structure 10 may also be provided with two or more first structures 14 according to actual conditions. When the metal interconnect structure 10 is provided with more than two first structures 14, the positions of the multiple first structures 14 in the metal interconnect structure 10 are not excessively restricted. They may be provided in a concentrated manner at the upper, middle or lower portion of the metal interconnect unit 13 of the M layer, or they may be provided in a dispersed manner in the metal interconnect unit 13 of the M layer, and the specific arrangement is made according to actual needs. As for the main reason for cracks or fractures in the metal interconnect layer, it is generally caused by the top metal interconnect structure above it, so the metal interconnect layer that has cracks or fractures is generally the metal interconnect unit 13 close to the top metal interconnect structure, and thus the improvement effect of providing the first structure 14 at the upper portion of the metal interconnect unit 13 of the M layer is better.

[0068] The number of layers of the metal interconnection unit 13 in the first structure 14 is not excessively limited, for example, it can be Figure 6 The two layers in Figure 7 The three layers in Figure 5 The four layers in Figure 8 The five layers in Figure 3 and Figure 4 There are six layers in it, and you can choose one according to your actual needs.

[0069] As an example, generally, in the metal interconnect structure 10, the heights of all the metal interconnect lines 133 in the M-layer metal interconnect unit 13 are set to be the same. Taking this as an example, the thickness of the dielectric layer 130 in the first structure 14 of this embodiment can be compared with Figure 2 The thickness change of the insulating layer 221 is illustrated as an example. When the heights of all the metal interconnects 133 are set to be the same, Figure 2 The thickness of the insulating layer 221 of each metal interconnection unit 22 is the same, and the thickness is defined as D. Figure 6 In the first structure 14 shown in FIG. 1 , a first structure 14 is provided, and the first structure 14 includes two layers of metal interconnection units 13. Assuming that the metal interconnection layer 135 of the lower metal interconnection unit 13 extends into the dielectric layer 130 of the upper metal interconnection unit 13 by a preset height of H1, the thickness of the dielectric layer 130 of the lower metal interconnection unit 13 is reduced to D-H1, and the thickness of the dielectric layer 130 of the upper metal interconnection unit 13 is increased to D+H1. Figure 2The thickness of the insulating layer 221 is D, Figure 6 The thickness of the dielectric layer 130 of the upper metal interconnection unit 13 in the first structure 14 is increased to D+H1. When cracks or breaks are likely to occur at this location, the increase in the thickness of the dielectric layer can effectively alleviate the influence of the upper stress on the metal interconnection layer. Figure 8 In the first structure 14 shown in FIG. 1 , a first structure 14 is provided, and the first structure 14 includes five layers of metal interconnection units 13. Assuming that the metal interconnection layer 135 of the lower metal interconnection unit 13 extends into the dielectric layer 130 of the upper metal interconnection unit 13 at preset heights H1, H2, H3, and H4 in sequence, the thickness of the dielectric layer 130 of the lowest metal interconnection unit 13 is reduced to D-H1, and the thickness of the dielectric layer 130 of the remaining metal interconnection units 13 is increased to D-H2+H1, D-H3+H2, D-H4+H3, and D+H4 in sequence. Figure 2 The thickness of the insulating layer 221 is D, Figure 8 The thickness of the dielectric layer 130 of the uppermost metal interconnection unit 13 in the first structure 14 is increased to D+H4. When cracks or fractures are likely to occur there, the increase in the thickness of the dielectric layer can effectively alleviate the stress influence of the upper layer stress on the metal interconnection layer, reducing or avoiding the occurrence of cracks or fractures. In addition, when the thicknesses of H2, H3, and H4 decrease in sequence, it means that the thicknesses of the dielectric layers 130 of the metal interconnection units 13 in other layers other than the uppermost layer in the first structure 14 are also increased. This method can also alleviate the stress influence of the upper layer stress on the metal interconnection layer below. Similarly, when the embodiment of the present invention is provided Figure 4 In the first structure 14 shown in FIG. 1 , a first structure 14 is provided, and the first structure 14 includes five layers of metal interconnection units 13. Assuming that the metal interconnection layer 135 of the lower metal interconnection unit 13 extends into the dielectric layer 130 of the upper metal interconnection unit 13 at preset heights H1, H2, H3, H4, and H5 in sequence, the thickness of the dielectric layer 130 of the lowest metal interconnection unit 13 is reduced to D-H1, and the thickness of the dielectric layer 130 of the remaining metal interconnection units 13 is increased to D-H2+H1, D-H3+H2, D-H4+H3, D-H5+H4, and D+H5 in sequence. Figure 2 The thickness of the insulating layer 221 is D, Figure 8The thickness of the dielectric layer 130 of the uppermost metal interconnection unit 13 in the first structure 14 increases to D+H5. When cracks or breaks are likely to occur there, the increase in the thickness of the dielectric layer can effectively alleviate the stress influence of the upper layer stress on the metal interconnection layer. In addition, when the thicknesses of H1, H2, H3, H4, and H5 decrease in sequence, it means that the thicknesses of the dielectric layers 130 of the metal interconnection units 13 in other layers other than the uppermost layer in the first structure 14 are also increased. This method can also alleviate the stress influence of the upper layer stress on the metal interconnection layer below.

[0070] like Figure 5 As shown, when the metal interconnection unit 13 of the M layer is not completely set to the first structure 14, the metal interconnection unit 13 of the M layer also includes at least one second structure 15, and the second structure 15 includes: a layer of the metal interconnection unit 13, and the upper surface and lower surface of the metal interconnection line 133 of the metal interconnection unit 13 are respectively flush with the upper surface and lower surface of the dielectric layer 130 of the metal interconnection unit 13.

[0071] As a preferred example, when the heights of all the metal interconnection lines 133 in the M-layer metal interconnection unit 13 are set to be the same, in the first structure 14, the metal interconnection layer 135 of the metal interconnection unit 13 at the bottom layer extends into the dielectric layer 130 of the metal interconnection unit 13 at the upper layer adjacent thereto, and the preset height is 10% to 70% of the thickness of the metal interconnection line 133 of the metal interconnection unit 13 at the bottom layer. Figure 4 As shown, further, the metal interconnection unit 13 of the M layer can be set to only one first structure 14, so as to achieve the reduction of the dielectric layer 13 thickness of the metal interconnection unit 13 at the bottom layer to at least transfer to the dielectric layer 13 of the metal interconnection unit 13 at the top layer. Figure 4 As shown, further, in the first structure 14, the preset height of the metal interconnection layer 135 of the metal interconnection unit 13 located at the lower layer extending into the dielectric layer 130 of the metal interconnection unit 13 in the upper layer adjacent thereto gradually decreases from bottom to top, that is, the sizes of H1, H2, H3, H4, and H5 gradually decrease, so that the thickness of the dielectric layer 130 of the metal interconnection units 13 in other layers of the first structure 4 except the metal interconnection unit 13 at the lowermost layer is relatively Figure 2 The thickness D of the insulating layer 221 is thickened, and the multi-layer thickening method can better alleviate the risk of cracking or breaking caused by the stress of the top metal interconnect structure. Figure 4As shown, optimally, in the first structure 14, the preset height of the metal interconnection layer 135 of the metal interconnection unit 13 located at the lower layer extending into the dielectric layer 130 of the metal interconnection unit 13 adjacent to it in the upper layer is gradually reduced in an arithmetic progression from bottom to top, so that the thickness of the dielectric layer 130 of the metal interconnection units 13 in other layers of the first structure 4 except the metal interconnection unit 13 at the lowermost layer is relatively Figure 2 The thickness D of the insulating layer 221 is increased and increased to the same thickness, which can evenly alleviate the risk of cracking or breaking caused by the stress of the top metal interconnect structure.

[0072] like Figures 3 to 8 As shown, as an example, the dielectric layer 130 of each metal interconnect unit 13 includes a metal dielectric layer 131 and an etch stop layer 132. Generally, the hardness of the material of the etch stop layer 132 is harder than that of the material of the metal dielectric layer 131. Therefore, when the metal interconnect layer 135 of the metal interconnect unit 13 of the lower layer in the first structure 14 extends into the dielectric layer 130 of the metal interconnect unit 13 of the upper layer adjacent thereto, the extended portion of the metal interconnect layer 135 will be covered by the etch stop layer 132 with a greater hardness, and the outer side of the portion of the etch stop layer 132 that covers the metal interconnect layer 135 is at least a portion of the metal dielectric layer 131 of the same metal interconnect unit 13 as the etch stop layer 132, so that the stress effect of the top metal interconnect structure on it can also be alleviated.

[0073] As an example, the material of the dielectric layer 130 in each layer of the metal interconnect unit 13 is the same, and generally a low-K material or an ultra-low-K material is selected, such as inorganic materials such as silicon oxyfluoride (SiOF), hydrogenated silicon carbide (SiCOH), silicon oxycarbide (SiCO), nitrogen-doped silicon carbide (BLoK), or organic compounds such as aromatic hydrocarbons and xylene plastics. In addition, when the dielectric layer 130 includes a metal dielectric layer 131 and an etch stop layer 132, the metal dielectric layer 131 generally selects the above-mentioned low-K material or ultra-low-K material, and the etch stop layer 132 selects a dielectric material with a harder texture, such as nitrogen-doped carbide, silicon nitride, silicon carbide or NDC.

[0074] As an example, the outer wall of the metal interconnect line 133 in each layer of the metal interconnect unit 13 is generally also provided with a diffusion barrier layer, such as a titanium nitride material layer, a titanium material layer, a tantalum material layer or a titanium nitride material layer, etc., to prevent the metal interconnect line 133 from diffusing into the dielectric layer 130; the material of the metal interconnect line 133 is generally selected to be copper material.

[0075] like Fig. 9 As shown, this embodiment further provides a semiconductor device, the semiconductor device comprising:

[0076] The metal interconnect structure 10 as described in the above embodiment;

[0077] A semiconductor substrate 11 located below the metal interconnect structure 10;

[0078] A top metal interconnect structure 12 is located above the metal interconnect structure 10 . The top metal interconnect structure 12 includes a top metal interconnect line 120 and a top dielectric layer 123 . The top metal interconnect line 120 is electrically connected to at least a portion of the metal interconnect lines of the metal interconnect structure 10 .

[0079] As an example, the top metal interconnection line 120 includes a top metal interconnection through hole 121 located at the lower layer and a top metal interconnection layer 122 located at the upper layer, and the upper surface and lower surface of the top metal interconnection line 120 of the top metal interconnection structure 12 are respectively flush with the upper surface and lower surface of the top dielectric layer 123 of the top metal interconnection structure 12.

[0080] As an example, the semiconductor substrate 11 can be a substrate structure known to those skilled in the art, such as a silicon substrate, a silicon germanium substrate, a carbon silicon substrate, a silicon on insulator (SOI) substrate, etc. In addition, a device structure can be formed in the semiconductor substrate 11, such as an amplifier, a digital / analog converter, an analog processing circuit and / or a digital processing circuit, an interface circuit, etc., which can be configured according to actual needs.

[0081] like Fig.10 and Fig.11 As shown, if the metal interconnect structure of this embodiment includes a second structure 15, a method for preparing the second structure 15 specifically includes: Fig.10 As described above, an etching stop layer 132 and a metal dielectric layer 131 are sequentially formed on the lower structure (the semiconductor substrate 11 is used as the lower structure here), and the surface is polished by a CMP process; Fig.11 As shown, a metal interconnection line 133 with a flat surface is formed in the etch stop layer 132 and the metal dielectric layer 131 by using photolithography, deposition and CMP processes.

[0082] like Figures 12 to 17 As shown, if the metal interconnect structure of this embodiment includes a first structure 14, the preparation method of the first structure 14 specifically includes: Fig.12 As shown, the dielectric layer 130 (eg, metal dielectric layer 133) of the first layer of the metal interconnection unit 13 is first etched to remove a predetermined height (eg, Figure 6 The dielectric layer 130 is generally etched by a dry etching process; Fig.13As shown, the dielectric layer 130 of the second layer of metal interconnection unit 13, such as the etching stop layer 132 and the metal dielectric layer 133, is then deposited in sequence on the surface of the first layer of metal interconnection unit 13; Fig.14 As shown, the dielectric layer 130 of the second metal interconnection unit 13 is then polished to a desired thickness using a CMP process; Fig.15 As shown, photolithography, deposition and CMP processes are then used to form a metal interconnection line 133 with a flat surface in the etch stop layer 132 and the metal dielectric layer 131 of the second metal interconnection unit 13, thereby achieving the following Figure 6 When the first structure 14 includes more layers of metal interconnection units 13 adjacent to each other, as shown in FIG. Fig.16 As shown, it can be Fig.15 On the basis of the above, the dielectric layer 130 of the metal interconnection unit 13 of the second layer is further etched away to a preset height (eg Figure 4 Then, the dielectric layer 130 of the third metal interconnection unit 13 is sequentially deposited on the surface of the second metal interconnection unit 13; Fig.17 As shown, the CMP process is then used to grind the dielectric layer 130 of the third-layer metal interconnection unit 13 to the required thickness; finally, photolithography, deposition and CMP processes are used to form a metal interconnection line 133 with a flat surface in the etch stop layer 132 and the metal dielectric layer 131 of the third-layer metal interconnection unit 13, and so on to achieve the required first structure 14.

[0083] In summary, the metal interconnection structure of the utility model is provided with a first structure in the M-layer metal interconnection unit, and the first structure extends the metal interconnection layer of the metal interconnection unit located at the lower layer into the dielectric layer of the upper metal interconnection unit adjacent thereto, and because the height of the metal interconnection line of each layer is a preset height and cannot be changed, compared with the structure in which the metal interconnection line in each metal interconnection unit of the existing metal interconnection structure is flush with the upper surface of the insulating layer, the first structure of the utility model thins the thickness of the dielectric layer of the metal interconnection unit located at the lowest layer in the first structure, so as to transfer the thinned dielectric layer thickness to the dielectric layers of other metal interconnection units in the first structure, so that the thickness of the dielectric layer of other metal interconnection units in the first structure is thicker than the thickness of the insulating layer of the existing metal interconnection unit, and the dielectric layer with increased thickness can effectively improve and alleviate the stress caused by the excessive size of the upper top metal interconnection structure on the lower metal interconnection unit. Therefore, the first structure can be provided at a position where the metal interconnection layer is prone to cracking, so as to reduce or even avoid the risk of cracking or even breaking of the metal interconnection layer in the metal interconnection structure, improve the product yield, and at the same time, will not increase the total thickness of the dielectric layer in the metal interconnection structure. Therefore, the utility model effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

[0084] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the technology may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed in the present invention shall still be covered by the claims of the present invention.

Claims

1. A metal interconnect structure, characterized in that: The metal interconnect structure comprises: M layers of metal interconnection units are disposed on a semiconductor substrate and are adjacent to and stacked in sequence, M≥2; Each layer of the metal interconnection unit includes a metal interconnection line and a dielectric layer; wherein the metal interconnection line includes a metal interconnection through hole located in a lower layer and a metal interconnection layer located in an upper layer, and the height of the metal interconnection line in each layer is the same, the metal interconnection line is at least partially covered by the dielectric layer, and the lower surface of the metal interconnection line of each layer of the metal interconnection unit is at least partially flush with the lower surface of the dielectric layer thereof; The metal interconnection lines of the metal interconnection units of upper and lower adjacent layers are electrically connected in contact; The metal interconnection unit of the M layer includes at least one first structure, wherein the first structure includes: at least two layers of metal interconnection units adjacent to each other, and at least a portion of the metal interconnection layer of the metal interconnection unit located at the lower layer extends into at least a portion of the dielectric layer of the metal interconnection unit adjacent to the upper layer to be covered by a preset height; The dielectric layer of the lowest metal interconnection unit in the first structure has the thinnest thickness.

2. The metal interconnect structure according to claim 1, characterized in that: The first structure is arranged on the upper part of the metal interconnection unit of the M layer.

3. The metal interconnect structure according to claim 1, characterized in that: The M-layer metal interconnection unit also includes at least one second structure, which includes: a layer of the metal interconnection unit, and the upper surface and lower surface of the metal interconnection line of the metal interconnection unit are respectively flush with the upper surface and lower surface of the dielectric layer of the metal interconnection unit.

4. The metal interconnect structure according to any one of claims 1 to 3, characterized in that: The heights of all the metal interconnection lines in the metal interconnection unit of the M layer are set to be the same.

5. The metal interconnect structure according to claim 4, characterized in that: In the first structure, the metal interconnection layer of the metal interconnection unit at the bottom extends into the dielectric layer of the metal interconnection unit adjacent to it at a preset height of 10% to 70% of the thickness of the metal interconnection line of the metal interconnection unit at the bottom.

6. The metal interconnect structure according to claim 5, characterized in that: The metal interconnection unit of the M layer is only configured as one of the first structures.

7. The metal interconnect structure according to claim 6, characterized in that: In the first structure, the preset height of the metal interconnection layer of the metal interconnection unit located at the lower layer extending into the dielectric layer of the metal interconnection unit adjacent to it at the upper layer gradually decreases from bottom to top.

8. The metal interconnect structure according to claim 7, characterized in that: In the first structure, the preset height of the metal interconnection layer of the metal interconnection unit located at the lower layer extending into the dielectric layer of the metal interconnection unit adjacent to it at the upper layer gradually decreases in an arithmetic progression from bottom to top.

9. The metal interconnect structure according to claim 1, characterized in that: The dielectric layer of each metal interconnection unit includes a metal dielectric layer and an etching stop layer.

10. A semiconductor device, characterized in that: The semiconductor device comprises: The metal interconnect structure according to any one of claims 1 to 9; a semiconductor substrate located below the metal interconnect structure; A top metal interconnection structure is located above the metal interconnection structure, wherein the top metal interconnection structure includes a top metal interconnection line and a top dielectric layer, and the top metal interconnection line is electrically connected to at least part of the metal interconnection lines of the metal interconnection structure.

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