Display panel and display device

Abstract

The utility model provides a display panel and a display device, the display panel comprises a display area and a frame area arranged on one side of the display area, and the display panel further comprises an integrated circuit input terminal, an integrated circuit output terminal and an array substrate detection terminal which are arranged in the frame area, the electrostatic protection circuit is connected between the detection terminal of the array substrate and the output terminal of the integrated circuit, the electrostatic protection circuit comprises at least one resistor, the resistor is utilized to intercept instantly generated charges, the charges are prevented from being transmitted into a plane, and therefore the probability of explosion caused by electrostatic discharge can be reduced.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] The current display industry is developing rapidly, and display applications have been integrated into all aspects of people's lives. New display modes are constantly emerging, and the traditional liquid crystal display (LCD) panel industry has become increasingly saturated, and the development speed has gradually slowed down. Organic light emitting diode (OLED) display panels have occupied most of the high-end products in the small-size field and are developing rapidly.

[0003] The array substrate detection circuit is used to detect the panel display quality during the production stage to prevent defective products from flowing into the back stage, resulting in waste of production materials and increased production costs. In order to save production costs, some OLED display panels will use small-sized integrated circuit (IC) chips. The space between the input and output terminals of the integrated circuit is compressed, and the array substrate detection (AT) circuit cannot be placed. Only the array substrate detection terminal can be placed. The data line is directly connected from the integrated circuit terminal to the array substrate detection terminal, and then connected to the surface. However, the array substrate detection terminal is prone to accumulate a large amount of charge during the process. The accumulated charge is transmitted to the surface along the data line, which will cause electrostatic discharge (ESD) damage on the devices near the integrated circuit chip.

[0004] Therefore, it is necessary to provide a display panel and a display device to improve this defect. Summary of the invention

[0005] The embodiments of the present application provide a display panel and a display device, which can prevent the charges on the detection terminals of the array substrate from being transmitted into the panel, thereby reducing the probability of electrostatic discharge and explosion.

[0006] An embodiment of the present application provides a display panel, comprising a display area and a frame area arranged on one side of the display area, and the display panel further comprises:

[0007] Integrated circuit input terminals are arranged in the frame area;

[0008] An integrated circuit output terminal is arranged in the frame area, and the integrated circuit output terminal is located on a side of the integrated circuit input terminal close to the display area;

[0009] An array substrate detection terminal is arranged in the frame area, and the array substrate detection terminal is located between the integrated circuit input terminal and the integrated circuit output terminal;

[0010] An electrostatic protection circuit is arranged in the frame area, and the electrostatic protection circuit includes at least one resistor, one end of the resistor is electrically connected to the integrated circuit output terminal, and the other end of the resistor is electrically connected to the array substrate detection terminal.

[0011] According to an embodiment of the present application, the electrostatic protection circuit includes a plurality of the resistors, which are sequentially connected in series and are electrically connected to the array substrate detection terminal and the integrated circuit output terminal, respectively.

[0012] According to an embodiment of the present application, a sheet resistance of the resistor is greater than or equal to 0.5 kilo-ohms and less than or equal to 10 kilo-ohms.

[0013] According to an embodiment of the present application, the display panel further comprises a substrate, and the integrated circuit input terminal, the integrated circuit output terminal and the array substrate detection terminal are all arranged on the substrate;

[0014] Wherein, a plurality of the array substrate detection terminals are arranged side by side and spaced apart, and the orthographic projection of the resistor on the substrate is located between the orthographic projections of adjacent array substrate detection terminals on the substrate.

[0015] According to an embodiment of the present application, the display panel further comprises a substrate, and the integrated circuit input terminal, the integrated circuit output terminal and the array substrate detection terminal are all arranged on the substrate;

[0016] The plurality of array substrate detection terminals are arranged side by side and spaced apart, and the orthographic projection of the resistor on the substrate is located between the orthographic projection of the array substrate detection terminal on the substrate and the orthographic projection of the integrated circuit output terminal on the substrate.

[0017] According to an embodiment of the present application, the material of the resistor is selected from one of polysilicon and oxide semiconductor.

[0018] According to an embodiment of the present application, the display panel further includes a substrate and an active layer, the active layer is disposed on the substrate, the resistor is disposed in the same layer as the active layer, and the substrate and the active layer are made of the same material.

[0019] According to an embodiment of the present application, a minimum distance between the integrated circuit input terminal and the integrated circuit output terminal is less than or equal to 200 micrometers.

[0020] According to an embodiment of the present application, the width of the resistor is greater than or equal to 2 micrometers.

[0021] An embodiment of the present application further provides a display device, comprising the display panel as described above.

[0022] Beneficial effects of the embodiments of the present application: The embodiments of the present application provide a display panel and a display device, the display panel includes a display area and a frame area arranged on one side of the display area, the display panel also includes an integrated circuit input terminal, an integrated circuit output terminal and an array substrate detection terminal arranged in the frame area, by connecting an electrostatic protection circuit between the array substrate detection terminal and the integrated circuit output terminal, the electrostatic protection circuit includes at least one resistor, and the resistor is used to intercept the charges generated instantaneously in the process to prevent the charges from being transmitted into the surface, thereby reducing the probability of electrostatic discharge injury. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 A schematic diagram of the structure of a display panel provided in an embodiment of the present application;

[0024] Figure 2 for Figure 1 The enlarged schematic diagram of point a in the middle;

[0025] Figure 3 for Figure 2 The enlarged schematic diagram of point b in the middle;

[0026] Figure 4 for Figure 2 The enlarged schematic diagram of point c in the middle;

[0027] Figure 5 A schematic structural diagram of a border area of ​​another display panel provided in an embodiment of the present application;

[0028] Figure 6 A schematic diagram of the film layer structure in the display area of ​​the display panel provided in an embodiment of the present application;

[0029] Figure 7 for Figure 3 A cross-sectional view of the display panel along the AA' direction;

[0030] Figure 8 A schematic diagram of a partial structure of another display panel provided in an embodiment of the present application;

[0031] Fig. 9 A schematic diagram of a partial structure of another display panel provided in an embodiment of the present application;

[0032] Fig.10 A schematic diagram of the structure of a display device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0033] The following descriptions of the embodiments are made with reference to the attached drawings to illustrate specific embodiments that the present application may be implemented in. The directional terms mentioned in the present application, such as [up], [down], [front], [back], [left], [right], [inside], [outside], [side], etc., are only with reference to the directions of the attached drawings. Therefore, the directional terms used are used to illustrate and understand the present application, rather than to limit the present application. In the drawings, units with similar structures are represented by the same reference numerals.

[0034] The present application is further described below in conjunction with the accompanying drawings and specific embodiments.

[0035] The embodiments of the present application provide a display panel and a display device, which can prevent the charges on the detection terminals of the array substrate from being transmitted into the surface, thereby reducing the probability of electrostatic discharge and explosion.

[0036] Combination Figure 1 and Figure 2 As shown, Figure 1 A schematic diagram of the structure of a display panel provided in an embodiment of the present application, Figure 2 for Figure 1 In the enlarged schematic diagram at point a, the display panel includes a display area AA and a border area DB arranged on one side of the display area AA. The display panel also includes an integrated circuit input terminal 11, an integrated circuit output terminal 12 and an array substrate detection terminal 13 arranged in the border area DB. The integrated circuit output terminal 12 is located on a side of the integrated circuit input terminal 11 close to the display area AA, and the array substrate detection terminal 13 is located between the integrated circuit input terminal 11 and the integrated circuit output terminal 12.

[0037] It should be noted that the display panel also includes a substrate, and the integrated circuit input terminal 11, the integrated circuit output terminal 12 and the array substrate detection terminal 13 are all arranged on the substrate, and the integrated circuit output terminal 12 is located on the side of the integrated circuit input terminal 11 close to the display area AA, which means that the orthographic projection of the integrated circuit output terminal 12 on the substrate is located on the side of the orthographic projection of the integrated circuit input terminal 11 on the substrate close to the display area AA. Similarly, the array substrate detection terminal 13 is located between the integrated circuit input terminal 11 and the integrated circuit output terminal 12, which means that the orthographic projection of the array substrate detection terminal 13 on the substrate is located between the orthographic projection of the integrated circuit input terminal 11 on the substrate and the orthographic projection of the integrated circuit output terminal 12 on the substrate.

[0038] like Figure 1As shown, the display panel further includes a first detection circuit 14 and a source electrostatic protection circuit 15 arranged in the frame area DB, the first detection circuit 14 is located on the side of the integrated circuit output terminal 12 close to the display area AA, and the source electrostatic protection circuit 15 is located between the first detection circuit 14 and the integrated circuit output terminal 12. The first detection circuit 14 is used to perform lighting detection on the light-emitting device after the light-emitting device is prepared, and the source electrostatic protection circuit 15 is used to transmit static electricity into the display area AA. The first detection circuit 14 and the source electrostatic protection circuit 15 can be replaced by other known circuit structures to achieve similar effects.

[0039] Combination Figure 2 and Figure 3 As shown, Figure 3 for Figure 2 In the enlarged schematic diagram at point b, the display panel also includes an electrostatic protection circuit 16, which is arranged in the border area DB. The electrostatic protection circuit 16 includes at least one resistor 160, one end of the resistor 160 is electrically connected to the integrated circuit output terminal 12, and the other end of the resistor 160 is electrically connected to the array substrate detection terminal 13.

[0040] In the embodiments of the present application, Figure 2 and Figure 3 As shown, the array substrate detection terminal 13 is connected to the resistor 160 through the first detection wiring 17, the resistor 160 is connected to the integrated circuit output terminal 12 through the second detection wiring 18, the integrated circuit output terminal 12 is connected to the data line 19, the data line 19 is led out from the integrated circuit output terminal 12, passes through the source electrostatic protection circuit 15 and the first detection circuit 14, and is connected to the display area AA, and is connected to the corresponding transistor in the display area AA. By connecting the resistor 160 in series between the array substrate detection terminal 13 and the integrated circuit output terminal 12, the resistor 160 can be used to intercept the charges generated instantly during the process, and prevent the instantly generated charges from being transmitted to the display area AA, thereby reducing the probability of electrostatic discharge injury.

[0041] like Figure 3 As shown, the resistor 160 is arranged on one side or two opposite sides of the array substrate detection terminal 13 in the second direction Y, the first detection wiring 17 includes a first wiring segment 171 and a second wiring segment 172 connected to the first wiring segment 171, the first wiring segment 171 is connected to the array substrate detection terminal 13, the second wiring segment 172 is connected to the resistor 160, the first wiring segment 171 is arranged parallel to the first direction X, and the second wiring segment 172 is arranged parallel to the second direction Y.

[0042] like Figure 3As shown, the shape of the array substrate detection terminal 13 is rectangular, the shape of the resistor 160 is rectangular, the length of the array substrate detection terminal 13 in the second direction Y is greater than the length of the resistor 160 in the second direction Y, and the width of the array substrate detection terminal 13 in the first direction X is greater than the width of the resistor 160 in the first direction X.

[0043] Furthermore, the width w of the resistor 160 is greater than or equal to 2 micrometers, so that the sheet resistance requirement of the resistor 160 can be met when it can be manufactured using existing process steps.

[0044] like Figure 2 As shown, the border area DB is provided with two rows of integrated circuit output terminals, wherein each row has a plurality of integrated circuit output terminals 12 arranged side by side and spaced apart from each other, and a row of integrated circuit output terminals that is farther away from the array substrate detection terminals 13 is set as the first row of integrated circuit output terminals, and a row of integrated circuit output terminals that is closer is set as the second row of integrated circuit output terminals.

[0045] like Figure 3 As shown, part of the second detection wiring 18 includes a third wiring segment 181, a fourth wiring segment 182 and a fifth wiring segment 183 connected in sequence, the third wiring segment 181 is connected to the resistor 160, the fifth wiring segment 183 is electrically connected to part of the integrated circuit output terminals 12 located in the second row, and the data line 19 extends between adjacent integrated circuit output terminals 12 in the first row and is connected to the corresponding integrated circuit output terminals 12 in the second row, wherein the third wiring segment 181 and the fifth wiring segment 183 are both arranged in parallel with the second direction Y, and the fourth wiring segment 182 is arranged in parallel with the first direction X.

[0046] like Figure 4 As shown, Figure 4 for Figure 2 In the enlarged schematic diagram at point c, the other part of the second detection wiring 18 includes a third wiring segment 181, a fourth wiring segment 182, a fifth wiring segment 183, a sixth wiring segment 184, a seventh wiring segment 185 and an eighth wiring segment 186 which are connected in sequence, the third wiring segment 181 is connected to the resistor 160, the eighth wiring segment 186 is connected to a part of the integrated circuit output terminals 12 located in the first row, and a part of the data line 19 is connected to the integrated circuit output terminals 12 corresponding to the first row, wherein the third wiring segment 181 and the fifth wiring segment 183 are both arranged in parallel with the second direction Y, the fourth wiring segment 182 and the seventh wiring segment 185 are both arranged in parallel with the first direction X, the sixth wiring segment 184 is arranged between adjacent integrated circuit output terminals 12 in the second row along a direction intersecting the first direction X and the second direction Y, and the eighth wiring segment 186 is arranged in parallel with the first direction X.

[0047] like Figure 4As shown, the border area DB is also provided with a third detection line 20, and some integrated circuit output terminals 12 of the first row are electrically connected to the third detection line 20. The third detection line 20 is led out from the integrated circuit output terminal 12 and extends to between the integrated circuit output terminals 12 of the second row, and is not connected to other devices.

[0048] like Figure 2 As shown, the minimum distance d between the integrated circuit input terminal 11 and the integrated circuit output terminal 12 is less than or equal to 200 microns, the space between the integrated circuit input terminal 11 and the integrated circuit output terminal 12 is small, and no array substrate detection circuit is set. When the array substrate is detected, the signal is directly input into the surface through the array substrate detection terminal 13 to realize the array substrate detection. By connecting the electrostatic protection circuit 16 in series between the array substrate detection terminal 13 and the integrated circuit output terminal 12, the resistor 160 of the electrostatic protection circuit 16 can intercept the charges generated instantly in the process and prevent the charges generated instantly from being transmitted into the surface, thereby reducing the probability of electrostatic discharge injury.

[0049] like Figure 5 As shown, Figure 5 A structural schematic diagram of another frame area of ​​a display panel provided in an embodiment of the present application, the display panel also includes a second detection circuit 21 arranged in the lower frame area DB, and the second detection circuit 21 is arranged between the integrated circuit output terminal 12 and the array substrate detection terminal 13. The second detection circuit 21 is used to detect the circuit after the thin film transistor array layer is prepared. The second detection circuit 21 can be replaced by other known circuit structures to achieve a similar effect. The opposite ends of the resistor are respectively connected to the array substrate detection terminal 13 and the second detection circuit 21, the second detection circuit 21 is connected to the integrated circuit output terminal 12, the integrated circuit output terminal 12 is connected to the data line 19, and the data line 19 is led out from the integrated circuit output terminal 12, passes through the source electrostatic protection circuit 15 and the first detection circuit 14, and is connected to the display area AA, and is connected to the corresponding transistor in the display area AA.

[0050] exist Figure 5 In the embodiment shown, the second detection circuit 21 is a multiplexing circuit having a certain electrostatic interception effect. Adding a resistor 160 for intercepting static electricity between the array substrate detection terminal 13 and the second detection circuit 21 can improve the corresponding electrostatic interception effect and further reduce the probability of the display panel being damaged by static electricity release.

[0051] Compared to Figure 5 The embodiment shown, Figure 2In the embodiment shown, since there is no array substrate detection circuit between the array substrate detection terminal 13 and the integrated circuit output terminal 12, when the array substrate is detected, the signal is directly input into the surface through the array substrate detection terminal 13 to realize the array substrate detection. The accumulated charge on the array substrate detection terminal 13 is more easily transmitted to the display area to cause damage, so Figure 2 The embodiment shown further requires a resistor 160 to be connected in series between the array substrate detection terminal 13 and the integrated circuit output terminal 12. The resistor 160 of the electrostatic protection circuit 16 can intercept the charges generated instantaneously during the process and prevent the charges generated instantaneously from being transmitted into the surface, thereby reducing the probability of the display panel being damaged by static discharge.

[0052] In some embodiments, the sheet resistance of the resistor 160 is greater than or equal to 0.5 kilo-ohms and less than or equal to 10 kilo-ohms.

[0053] In one embodiment, the electrostatic protection circuit 16 has only one resistor 160 , one end of the resistor 160 is electrically connected to the integrated circuit output terminal 12 , and the other end of the resistor 160 is electrically connected to the array substrate detection terminal 13 , and the sheet resistance of the resistor 160 is 3 kilo-ohms.

[0054] In some other embodiments, the sheet resistance of resistor 160 is not limited to 3 kilo-ohms in the above embodiments, but may also be 0.5 kilo-ohms, 2 kilo-ohms, 5 kilo-ohms, 8 kilo-ohms or 10 kilo-ohms, etc., and only needs to be between 0.5 kilo-ohms and 10 kilo-ohms. This can not only avoid poor interception of electrostatic release due to too small sheet resistance of resistor 160, but also avoid affecting the transmission of array substrate detection signals due to too large sheet resistance of resistor 160.

[0055] In some embodiments, the material of resistor 160 is selected from one of polysilicon and oxide semiconductor. Compared with amorphous metal conductive materials such as polysilicon or oxide semiconductor, the resistance of metal materials is smaller. If metal is used as the material of resistor 160, it is necessary to extend the wiring between resistor 160 and array substrate detection terminal 13 or integrated circuit output terminal 12, and perform winding settings to increase the total resistance of resistor 160 and the wiring, so that the total resistance of resistor 160 and the wiring meets the requirements of intercepting static electricity, but this will increase the space occupied by resistor 160 and the wiring, which is not conducive to the use of small-sized integrated circuit chips. Using polysilicon or oxide semiconductor as the material of resistor 160 can not only meet the requirements of the sheet resistance of resistor 160, but also reduce the space occupied by resistor 160 and the wiring, which is conducive to the use of small-sized integrated circuit chips.

[0056] In one embodiment, the material of the resistor 160 is polysilicon, and the resistor 160 needs to be doped. The doping type of the resistor 160 can be any one of N-type doping and P-type doping. It only needs to ensure that the sheet resistance of the resistor 160 is between 0.5 kilo-ohms and 10 kilo-ohms.

[0057] In one embodiment, if Figure 6 As shown, Figure 6 A schematic diagram of the film layer structure of the display panel in the display area provided in an embodiment of the present application, wherein the film layer structure of the display panel in the display area includes a substrate 10 and a buffer layer 101 stacked on the substrate 10, an active layer 102, a first insulating layer 103, a gate metal layer 104, a second insulating layer 105, a first source-drain electrode metal layer 106, a third insulating layer 107, a second source-drain electrode metal layer 108, a planarization layer 109, an anode 110, a pixel definition layer 111, a light-emitting layer 112, and a cathode 113.

[0058] like Figure 7 As shown, Figure 7 for Figure 3 In the cross-sectional view of the display panel along the A-A' direction, the resistor 160 is arranged on the surface of the buffer layer 101 away from the substrate 10, the array substrate detection terminal 13 is formed by stacking a first metal layer 131 and a second metal layer 132, the resistor 160 and the active layer 102 are arranged on the same layer, and the resistor 160 and the active layer 102 are made of the same material, the first metal layer 131 and the first source-drain electrode metal layer 106 are arranged on the same layer, and the first metal layer 131 and the first source-drain electrode metal layer 106 are made of the same material, the second metal layer 132 and the second source-drain electrode metal layer 108 are arranged on the same layer, and the second metal layer 132 and the second source-drain electrode metal layer 108 are made of the same material.

[0059] The materials of resistor 160 and active layer 102 are both polysilicon, and the resistor 160 and active layer 102 have the same doping type and doping concentration. The resistor 160 can be simultaneously prepared and formed using the process of active layer 102. Therefore, the process steps of the display panel will not increase due to the addition of resistor 160.

[0060] In one embodiment, in combination Figure 3 and Figure 6 As shown, a plurality of array substrate detection terminals 13 are arranged side by side and spaced apart, the orthographic projection of the resistor 160 on the substrate 10 is located between the orthographic projections of adjacent array substrate detection terminals 13 on the substrate 10, and one resistor 160 is arranged between two adjacent array substrate detection terminals 13. By placing the resistor 160 in the gap between the adjacent array substrate detection terminals 13, the probability of electrostatic discharge injury can be reduced while meeting the requirement of using small-sized integrated circuit chips.

[0061] like Figure 8 As shown, Figure 8 A partial structural diagram of another display panel provided in an embodiment of the present application, the structure of which is similar to Figure 3 The structures of the display panels shown are substantially the same, except that the orthographic projection of the resistor 160 on the substrate 10 is located between the orthographic projection of the array substrate detection terminal 13 on the substrate 10 and the orthographic projection of the integrated circuit output terminal 12 on the substrate 10 .

[0062] like Figure 8 As shown, a plurality of array substrate detection terminals 13 are arranged side by side and spaced apart, a plurality of resistors 160 are arranged side by side and spaced apart, the orthographic projection of the resistor 160 on the substrate 10 is located between the orthographic projection of the array substrate detection terminal 13 on the substrate 10 and the orthographic projection of the integrated circuit output terminal 12 on the substrate 10, one end of each resistor 160 is connected to a corresponding array substrate detection terminal 13, and the other end of each resistor 160 is electrically connected to a corresponding integrated circuit output terminal 12. That is, when the space between the integrated circuit input terminal 11 and the integrated circuit output terminal 12 is large, the resistor 160 can also be arranged between the integrated circuit output terminal 12 and the array substrate detection terminal 13.

[0063] like Fig. 9 As shown, Fig. 9 A partial structural diagram of another display panel provided in an embodiment of the present application, the structure of which is similar to Figure 3 The structures of the display panels shown are substantially the same, except that the electrostatic protection circuit 16 includes a plurality of resistors 160 , which are sequentially connected in series and are electrically connected to the array substrate detection terminal 13 and the integrated circuit output terminal 12 , respectively.

[0064] In one embodiment, the electrostatic protection circuit 16 includes two resistors 160, the two resistors 160 are connected along Figure 6 As shown, they are arranged in the vertical direction and connected in series, the lower resistor 160 is electrically connected to the array substrate detection terminal 13 , and the upper resistor 160 is electrically connected to the integrated circuit output terminal 12 .

[0065] In some other embodiments, the number of resistors in the electrostatic protection circuit 16 is not limited to 2 in the above embodiment, but can also be 3 or 4 or more. Figure 8 In practical applications, the specific number and arrangement of resistors in the electrostatic protection circuit 16 can be set according to actual needs and the space between the integrated circuit input terminal 11 and the integrated circuit output terminal 12, and are not limited here.

[0066] According to the display panel provided in the above embodiment of the present application, the embodiment of the present application further provides a display device, such as Fig.10 As shown, Fig.10 The present invention is a schematic diagram of the structure of a display device provided in an embodiment of the present application, wherein the display device comprises a frame 200 and a display module 100, wherein the display module 100 is disposed on the frame 200, and the display module 100 may be a display module provided in any of the above-mentioned embodiments, and the display device may be, but is not limited to, display devices such as smart phones, smart watches, desktop computers, laptop computers, and televisions.

[0067] Beneficial effects of the embodiments of the present application: The embodiments of the present application provide a display panel and a display device, the display panel includes a display area and a frame area arranged on one side of the display area, the display panel also includes an integrated circuit input terminal, an integrated circuit output terminal and an array substrate detection terminal arranged in the frame area, by connecting an electrostatic protection circuit between the array substrate detection terminal and the integrated circuit output terminal, the electrostatic protection circuit includes at least one resistor, and the resistor is used to intercept the charges generated instantaneously in the process to prevent the charges from being transmitted into the surface, thereby reducing the probability of electrostatic discharge injury.

[0068] In summary, although the present application is disclosed as above with preferred embodiments, the above preferred embodiments are not intended to limit the present application. Ordinary technicians in this field can make various changes and modifications without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application is based on the scope defined by the claims.

Claims

1. A display panel, characterized in that: The display panel includes a display area and a frame area arranged on one side of the display area, and the display panel also includes: Integrated circuit input terminals are arranged in the frame area; An integrated circuit output terminal is arranged in the frame area, and the integrated circuit output terminal is located on a side of the integrated circuit input terminal close to the display area; An array substrate detection terminal is arranged in the frame area, and the array substrate detection terminal is located between the integrated circuit input terminal and the integrated circuit output terminal; An electrostatic protection circuit is arranged in the frame area, and the electrostatic protection circuit includes at least one resistor, one end of the resistor is electrically connected to the integrated circuit output terminal, and the other end of the resistor is electrically connected to the array substrate detection terminal.

2. The display panel according to claim 1, wherein: The sheet resistance of the resistor is greater than or equal to 0.5 kilo-ohms and less than or equal to 10 kilo-ohms.

3. The display panel according to claim 1, wherein: The electrostatic protection circuit includes a plurality of resistors, which are sequentially connected in series and are electrically connected to the array substrate detection terminal and the integrated circuit output terminal respectively.

4. The display panel according to claim 1, wherein: The display panel further comprises a substrate, and the integrated circuit input terminal, the integrated circuit output terminal and the array substrate detection terminal are all arranged on the substrate; Wherein, a plurality of the array substrate detection terminals are arranged side by side and spaced apart, and the orthographic projection of the resistor on the substrate is located between the orthographic projections of adjacent array substrate detection terminals on the substrate.

5. The display panel according to claim 1, wherein: The display panel further comprises a substrate, and the integrated circuit input terminal, the integrated circuit output terminal and the array substrate detection terminal are all arranged on the substrate; The plurality of array substrate detection terminals are arranged side by side and spaced apart, and the orthographic projection of the resistor on the substrate is located between the orthographic projection of the array substrate detection terminal on the substrate and the orthographic projection of the integrated circuit output terminal on the substrate.

6. The display panel according to claim 1, wherein: The material of the resistor is selected from one of polysilicon and oxide semiconductor.

7. The display panel according to claim 6, wherein: The display panel further comprises a substrate and an active layer, wherein the active layer is arranged on the substrate, the resistor is arranged in the same layer as the active layer, and the substrate and the active layer are made of the same material.

8. The display panel according to claim 1, wherein: A minimum distance between the integrated circuit input terminal and the integrated circuit output terminal is less than or equal to 200 micrometers.

9. The display panel according to claim 1, wherein: The width of the resistor is greater than or equal to 2 micrometers.

10. A display device, characterized in that: Comprising the display panel as claimed in any one of claims 1 to 9.

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