Power module, power electronic device, and vehicle

Abstract

The utility model discloses a power module, power electronic equipment and a vehicle. The power module comprises a substrate; a plurality of first power chips form a first power chip group; the plurality of second power chips form a second power chip group, and the two first power chips, which are arranged at an interval along the first direction, in the first power chip group are respectively arranged at the two sides of the first direction of the second power chip group; and the first power chip set and the second power chip set are symmetrically arranged about the center line extending in the second direction of the substrate. Therefore, the first power chip and the second power chip are parallel to each other while the first power chip and the second power chip are symmetrically arranged on the substrate, so that the integration level of the power module can be improved, the current directions can be opposite during current conversion of the power module, and mutual inductance is generated; therefore, part of stray inductance in the power module can be offset, and switching loss is reduced.

Description

Technical Field

[0001] The utility model relates to the technical field of vehicles, in particular to a power module, a power electronic device and a vehicle. Background Art

[0002] Power semiconductor modules are circuit modules that combine power semiconductor chips into a whole according to certain functional combinations. They have the advantages of small size and high power density, so they are widely used in the field of new energy vehicles. With the continuous development of the electric vehicle industry, automotive power modules are an indispensable key component in the control system of electric vehicles. The performance of the automotive power module itself has a certain impact on the overall performance optimization of the vehicle.

[0003] In the prior art, the performance of silicon carbide metal field effect semiconductor transistors is better than that of traditional silicon-based devices of the same voltage level. However, since the stray capacitance of the silicon carbide metal field effect semiconductor transistor chip is very small, the switching speed is very fast, which makes it extremely sensitive to stray parameters. Therefore, it will cause large voltage and current overshoots and switching oscillations in the silicon carbide metal field effect semiconductor transistor during the switching process, which may cause device damage or failure in severe cases. Utility Model Content

[0004] The utility model aims to solve at least one of the technical problems existing in the prior art. To this end, one purpose of the utility model is to provide a power module, which can reduce stray inductance.

[0005] Another object of the present invention is to provide a power electronic device.

[0006] Another object of the present invention is to provide a vehicle.

[0007] According to the power module of the embodiment of the utility model, it includes: a substrate, on which an AC region and a first DC region are arranged, and the AC region and the first DC region are arranged at intervals; a first power chip, the first power chip is arranged in the AC region and there are multiple first power chips, and the multiple first power chips form a first power chips group, and the first power chips group includes at least two first power chips arranged at intervals in a first direction; a second power chip, the second power chip is arranged in the first DC region and there are multiple second power chips, and the multiple second power chips form a second power chips group, and the second power chips group includes at least two second power chips arranged at intervals in the first direction, and two of the first power chips in the first power chips group are respectively arranged on both sides of the first direction of the second power chips group, and the first power chips group and the second power chips group are symmetrically arranged about a center line extending in the second direction of the substrate, wherein the first direction and the second direction are perpendicular to each other.

[0008] Therefore, by arranging the first power chip and the second power chip symmetrically on the substrate and making them parallel to each other, not only can the integration of the power module be improved, but also the current direction can be opposite when the power module is switching, thereby generating mutual inductance, thereby offsetting the stray inductance inside the power module and reducing switching losses.

[0009] In some examples of the present invention, there are multiple first power chipsets, and the multiple first power chipsets are arranged at intervals in the second direction. There are multiple second power chipsets, and the multiple second power chipsets are arranged at intervals in the second direction. The multiple first power chipsets and the multiple second power chipsets correspond one to one, and the multiple first power chipsets and the multiple second power chipsets are symmetrically arranged about a center line extending in the second direction of the substrate.

[0010] In some examples of the present invention, a plane perpendicular to the substrate and extending in the second direction is set as a reference plane, and projections of the first power chipsets and the second power chipsets on the reference plane are at least partially offset from each other.

[0011] In some examples of the present invention, the AC region includes a first sub-AC region and a second sub-AC region, the first sub-AC region extends in a first direction and is spaced apart from the first DC region in a second direction, there are two second sub-AC regions and they are respectively connected to the two ends of the first sub-AC region in the first direction, the second sub-AC region is extended in the second direction, and the two second sub-AC regions are respectively located on both sides of the first DC region in the first direction and are spaced apart from the first DC region.

[0012] In some examples of the present invention, the communication area is symmetrically arranged with respect to a center line extending in the second direction of the substrate.

[0013] In some examples of the present invention, the substrate is further provided with a second DC region, the second DC region is located between the first DC region and the AC region, the second DC region is electrically connected to the first power chip, and the AC region is electrically connected to the second power chip.

[0014] In some examples of the present invention, the second DC region includes a first sub-DC region, a second sub-DC region and a third sub-DC region, the first sub-DC region extends in the first direction and is located between the first sub-AC region and the first DC region, there are two second sub-DC regions and they are respectively arranged at both ends of the first sub-DC region in the first direction, the second sub-DC region is extended in the second direction and is located between the second sub-AC region and the first DC region, the third sub-DC region is arranged at one end of the second sub-DC region away from the first sub-DC region and extends in the first direction, and the third sub-DC region and the second sub-AC region are spaced apart in the second direction.

[0015] In some examples of the present invention, a first avoidance gap is provided on the first DC region, a first source signal control area is provided in the first avoidance gap, the first source signal control area and the second power chip group are alternately arranged in sequence in the second direction, the first source signal control area is provided with a first bonding resistor, the first bonding resistor is electrically connected to the second power chip, and the first source signal control area is electrically connected to the second power chip.

[0016] In some examples of the present invention, a second avoidance gap is provided on a side of the first DC region away from the first sub-AC region, a first gate signal control area and a second source signal control area are provided in the second avoidance gap, the first gate signal control area and the second source signal control area are respectively provided with a first metal and a second metal, the first metal is electrically connected to the first bonding resistor, the second metal is electrically connected to the first source signal control area, and the first gate signal control area and the second source signal control area are spaced apart in the second direction.

[0017] In some examples of the present invention, a second gate signal control region and a third source signal control region are arranged on a side of the first DC region away from the first sub-AC region, the second gate signal control region, the third source signal control region and the first DC region are spaced apart in the second direction, a third metal is arranged on the second gate signal control region, a fourth metal is arranged on the third source signal control region, the first metal and the third metal are electrically connected, and the second metal and the fourth metal are electrically connected.

[0018] In some examples of the present invention, a third avoidance gap is provided on one side of the two second sub-AC regions that are away from each other in the first direction, a fourth source signal control area is provided in the third avoidance gap, a second bonding resistor is provided on the fourth source signal control area, and the first power chip is electrically connected to the second bonding resistor and the fourth source signal control area, respectively.

[0019] In some examples of the present invention, a fifth source signal control region and a third gate signal control region are arranged on the side of the first sub-AC region away from the first DC region, the fifth source signal control region, the third gate signal control region and the AC region are spaced apart in the second direction, a fifth metal and a sixth metal are respectively arranged on the fifth source signal control region and the third gate signal control region, the fifth metal is electrically connected to the fourth source signal control region, and the sixth metal is electrically connected to the second bonding resistor.

[0020] The power electronic device according to the utility model comprises the power module mentioned above.

[0021] The vehicle according to the present utility model comprises the power electronic device mentioned above.

[0022] Additional aspects and advantages of the present invention will be given in part in the following description, and in part will become apparent from the following description, or will be learned through the practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The above and / or additional aspects and advantages of the present invention will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0024] Figure 1 is a schematic diagram of a substrate according to an embodiment of the utility model;

[0025] Figure 2 is a schematic diagram of a power module according to an embodiment of the utility model;

[0026] Figure 3 It is a three-dimensional diagram of a power module according to an embodiment of the utility model.

[0027] Reference numerals:

[0028] 100. Power module;

[0029] 10. substrate; 11. AC region; 111. first sub-AC region; 112. second sub-AC region; 113. third avoidance gap; 114. fourth source signal control region; 1141. second bonding resistor; 115. fifth source signal control region; 1151. fifth metal; 116. third gate signal control region; 1161. sixth metal;

[0030] 12, first DC region; 121, first avoidance gap; 1211, first source signal control region; 1212, first bonding resistor; 122, second avoidance gap; 1221, first gate signal control region; 12211, first metal; 1222, second source signal control region; 12221, second metal; 123, second gate signal control region; 1231, third metal; 124, third source signal control region; 1241, fourth metal;

[0031] 13. Second DC region; 131. First sub-DC region; 132. Second sub-DC region; 133. Third sub-DC region;

[0032] 14. Drain sampling area;

[0033] 20. a first power chipset; 21. a first power chip;

[0034] 30. A second power chipset; 31. A second power chip. DETAILED DESCRIPTION

[0035] The embodiments of the present utility model are described in detail below. The embodiments described with reference to the accompanying drawings are exemplary. The embodiments of the present utility model are described in detail below.

[0036] Reference below Figure 1-Figure 3 A power module 100 according to an embodiment of the present invention is described. The power module 100 of the present invention can be applied to power electronic equipment. The power electronic equipment equipped with the power module 100 of the present invention can be applied to vehicles.

[0037] Combination Figure 1-Figure 3 As shown, the power module 100 according to the utility model can mainly include: a substrate 10, a first power chip 21 and a second power chip 31, wherein an AC region 11 and a first DC region 12 are arranged on the substrate 10, and the AC region 11 and the first DC region 12 are arranged at intervals, which can ensure the structural independence of the AC region 11 and the first DC input region on the substrate 10, and can prevent the AC region 11 and the first DC region 12 from contacting each other to cause a short circuit in the power module 100, thereby ensuring the reliability of the power module 100.

[0038] Further, the first power chip 21 is arranged in the AC region 11, and the second power chip 31 is arranged in the first DC region 12. Specifically, the AC region 11 and the first DC region 12 on the substrate 10 of the power module 100 in the utility model are both made of metal and have conductivity. A plurality of first power chips 21 are arranged in the AC region 11, so that the plurality of first power chips 21 are all electrically connected to the AC region 11, ensuring that the current flows smoothly between the plurality of first power chips 21 and the AC region 11. A plurality of second power chips 31 are arranged in the first DC region 12, so that the plurality of second power chips 31 are all electrically connected to the first DC region 12, ensuring that the current flows smoothly between the plurality of second power chips 31 and the first DC region 12.

[0039] In the embodiment of the utility model, the method of electrically connecting the first power chip 21 to the AC region 11 includes but is not limited to electrically connecting the drain of the first power chip 21 to the metal layer of the AC region 11 through a sintering or welding process. The method of electrically connecting the second power chip 31 to the first DC region 12 includes but is not limited to electrically connecting the drain of the second power chip 31 to the metal layer of the first DC region 12 through a sintering or welding process.

[0040] Furthermore, there are multiple first power chips 21 and multiple second power chips 31, and multiple first power chips 21 are arranged in parallel, and multiple second power chips 31 are arranged in parallel, which can ensure the normal operation of the power module 100. Multiple second power chips 31 form a second power chip group 30, and the second power chip group 30 includes at least two second power chips 31 arranged at intervals in the first direction. In this way, while meeting the number requirements of the second power chips 31 on the power module 100, the size of the substrate 10 in the second direction can be reduced, which is beneficial to improving the integration of the power module 100 and the performance of the power module 100.

[0041] Furthermore, multiple first power chips 21 form a first power chip group 20, and the first power chip group 20 includes at least two first power chips 21 located on both sides of the first direction of the second power chip group 30, which can shorten the distance between the first power chip 21 and the second power chip 31, and can make the two parts of the circuit where the first power chip 21 and the second power chip 31 on the power module 100 are located close to each other, thereby generating mutual inductance.

[0042] In addition, the multiple first power chips 21 in the first power chipset group 20 and the two second power chips 31 in the second power chipset group 30 are arranged at intervals along the first direction, so that the first power chips 21 and the second power chips 31 on the substrate 10 can be arranged parallel to each other along the first direction. When the power module 100 is commutating, the first power chips 21 and the second power chips 31 are arranged parallel to each other along the first direction, so that the two circuits where the first power chips 21 and the second power chips 31 on the power module 100 are located can be parallel to each other.

[0043] With such an arrangement, when current is commutated in the power module 100, the two circuit parts where the first power chip 21 and the second power chip 31 are located are parallel and opposite, and close to each other, so that the two parallel and opposite current loops can generate mutual inductance in the power module 100, thereby offsetting the stray inductance in the power module 100, and preventing the power module 100 from experiencing large voltage and current overshoots and switching oscillations during the switching process, thereby protecting the structure of the power module 100 and extending the service life of the power module 100.

[0044] Furthermore, the first power chipset group 20 and the second power chipset group 30 are symmetrically arranged about a center line extending in the second direction of the substrate 10, which not only improves the integration of the power module 100, but also ensures that the second power chipset group 30 and the first power chipset group 20 are parallel to each other, so as to further increase the mutual inductance between the parallel and reverse current loops in the power module 100.

[0045] Furthermore, the first direction and the second direction are perpendicular to each other. In the embodiment of the utility model, the first direction is the width direction of the substrate 10, and the second direction is the length direction of the substrate 10, so that the plurality of first power chips 21 and the plurality of second power chips 31 on the substrate 10 are parallel to each other along the width direction on the substrate 10, and are symmetrically arranged along the center line of the length direction on the substrate 10, which not only facilitates the arrangement of the first power chip 21 and the second power chip 31 on the substrate 10, but also ensures the elimination effect of the stray inductance in the power module 100 by the embodiment of the utility model.

[0046] Therefore, in the present application, the first power chip 21 and the second power chip 31 are arranged symmetrically on the substrate 10 while being parallel to each other. This not only improves the integration of the power module 100, but also makes the current directions opposite when the power module 100 is switching, thereby generating mutual inductance, thereby offsetting the stray inductance inside the power module 100 and reducing switching losses.

[0047] Combination Figure 1-Figure 3As shown, there are multiple first power chipsets 20, and the multiple first power chipsets 20 are arranged at intervals in the second direction, and there are multiple second power chipsets 30. Specifically, the multiple first power chipsets 20 and the multiple second power chipsets 30 can increase the number of chips on the power module 100 and increase the output current of the power module 100. The multiple first power chipsets 20 and the multiple second power chipsets 30 are arranged on the substrate 10 and arranged at intervals along the length direction of the substrate 10, so that the multiple first power chipsets 20 and the multiple second power chipsets 30 can be dispersed on the substrate 10. In this way, when the power module 100 is working, the heat on the substrate 10 can be dispersed, which can not only improve the maximum output power of the power module 100, but also reduce the maximum junction temperature of the second power chip 31 and the first power chip 21, which is conducive to improving the performance of the power module 100.

[0048] Furthermore, multiple first power chip groups 20 and multiple second power chip groups 30 are arranged in one-to-one correspondence, so that a first power chip 21 is arranged on both sides of the first direction of each second power chip group 30. Such an arrangement can increase the parallel and reverse current loops that generate mutual inductance in the power module 100, which is beneficial to increase the magnitude of the mutual inductance generated in the power module 100, and can further reduce the stray inductance in the power module 100. In this way, during the operation of the power module 100, the loss of the switch can be further reduced.

[0049] Furthermore, multiple first power chip groups 20 and multiple second power chip groups 30 are symmetrically arranged about a center line extending in the second direction of the substrate 10, so that it can be ensured that the multiple first power chip groups 20 spaced apart along the second direction on the substrate 10 and the multiple second power chip groups 30 spaced apart along the second direction are symmetrically arranged about a center line extending in the length direction of the substrate 10, so as to increase the number of chips in the power module 100 while ensuring the reliability of the layout of the chips on the substrate 10 in the utility model.

[0050] Combination Figure 1-Figure 3 As shown, a plane perpendicular to the substrate 10 and extending in the second direction is set as a reference plane, and the projections of the plurality of first power chip groups 20 and the plurality of second power chip groups 30 on the reference plane are at least partially staggered, so that the current loop connecting the first power chip 21 and the current loop connecting the second power chip 31 can be staggered. Such a configuration can, on the one hand, facilitate the bonding of the first power chip 21 and the second power chip 31 during the manufacturing process of the power module 100, so as to reduce the difficulty of manufacturing the power module 100, and on the other hand, can increase the heat dissipation area of ​​the first power chip 21 and the second power chip 31, which is conducive to reducing the maximum junction temperature of the second power chip 31 and the first power chip 21, thereby improving the performance of the power module 100.

[0051] Combination Figure 1 and Figure 3 As shown, the AC region 11 includes a first sub-AC region 111 and a second sub-AC region 112. The first sub-AC region 111 extends in the first direction and is spaced apart from the first DC region 12 in the second direction. There are two second sub-AC regions 112, which are respectively connected to the two ends of the first sub-AC region 111 in the first direction. The second sub-AC regions 112 are extended in the second direction. The two second sub-AC regions 112 are respectively located on both sides of the first DC region 12 in the first direction and are spaced apart from the first DC region 12.

[0052] Specifically, the first sub-AC region 111 in the AC region 11 extends in the first direction, which can increase the area of ​​the first sub-AC region 111 on the substrate 10, and can facilitate the arrangement of external terminals on the AC region 11 to ensure the reliability of the connection between the AC region 11 and the external circuit. The first sub-AC region 111 and the first DC region 12 are arranged at intervals from each other in the second direction, which can prevent the first sub-AC region 111 from contacting the first DC region 12 and thus causing a short circuit inside the power module 100, so that the first sub-AC region 111 and the first DC region 12 can be arranged independently on the substrate 10 to ensure the structural reliability of the power module 100.

[0053] Furthermore, the two second sub-AC regions 112 are respectively located at the two ends of the first sub-AC region 111 in the first direction, so that the two second sub-AC regions 112 can be connected to the first sub-AC region 111 to ensure the internal circuit connectivity of the AC region 11. The two sub-AC regions 11 are respectively located on both sides of the first DC region 12 in the first direction, and are both spaced apart from the first DC region 12, which can not only ensure the structural independence of the two second sub-AC regions 112 and the first DC region 12 on the substrate 10, and prevent a short circuit from occurring inside the power module 100, but also make the two second sub-AC regions 112 close to the first DC region 12, so that the flow path of the current between the AC region 11 and the first DC region 12 can be shortened, so as to reduce the stray inductance generated by the power module 100 at the moment of switch disconnection, and improve the reliability of the power module 100.

[0054] Furthermore, the two second sub-AC regions 112 are extended in the second direction, which can increase the setting area of ​​the second sub-AC regions 112 on the substrate 10, increase the number of first power chips 21 on the AC region 11, and thus increase the total number of chips on the power module 100 to improve the maximum output power of the power module 100.

[0055] Combination Figure 1As shown, the AC region 11 is symmetrically arranged about the center line extending in the second direction of the substrate 10. Specifically, the AC region 11 includes a first sub-AC region 111 and two second sub-AC regions 112, the first sub-AC region 111 extends in the first direction, the two second sub-AC regions 112 are respectively arranged at two ends of the first sub-AC region 111 in the first direction, and both extend toward the second direction, the first sub-AC region 111 and the two second sub-AC regions 112 are symmetrically arranged about the center line extending in the second direction of the substrate 10 as a whole, and such an arrangement is conducive to offsetting the stray inductance in the power module 100, reducing the large voltage and current overshoot and switching oscillation phenomenon in the power module 100 during the switching process, thereby protecting the structure of the power module 100 and extending the service life of the power module 100.

[0056] In the embodiment of the present invention, the first DC region 12 is located between the two second sub-AC regions 112 on the substrate 10, and the two second sub-AC regions 112 and the first DC region 12 are arranged at intervals in the first direction, and the first DC region 12 is located in the middle of the substrate 10. In addition, the first DC region 12 and the first sub-AC region 111 are arranged at intervals in the second direction of the substrate 10. Further, originally the first DC region 12 is rectangular, and the first DC region 12 and the AC region 11 are both arranged symmetrically about the center line extending in the second direction of the substrate 10; however, since the second avoidance notch 122 is arranged near the first metal 12211 and the second metal 12221 of the first DC region 12, the first DC region 12 is not completely symmetrically arranged about the center line extending in the second direction of the substrate 10. Although the first DC region 12 is not completely symmetrically arranged about the center line extending in the second direction of the substrate 10, it can also be beneficial to offset the stray inductance in the power module 100 to a certain extent.

[0057] Combination Figure 1-Figure 3 As shown, the substrate 10 is further provided with a second DC region 13, the second DC region 13 is located between the first DC region 12 and the AC region 11, the second DC region 13 is electrically connected to the first power chip 21, and the AC region 11 is electrically connected to the second power chip 31. Specifically, in the embodiment of the utility model, the first DC region 12 is a DC input region, and the second DC region 13 is a DC output region. During the operation of the power module 100, the current flows along two paths: the first DC region 12-the second power chip-the AC region 11 and the AC region 11-the first power chip 21-the second DC region 13.

[0058] Furthermore, by arranging the second DC region 13 between the first DC region 12 and the AC region 11, the distance between the second DC region 13 and the first DC region 12 and the distance between the second DC region 13 and the AC region 11 can be shortened at the same time, which not only facilitates the electrical connection between the AC region 11 and the second power chip 31, but also facilitates the electrical connection between the second DC region 13 and the first power chip 21. This is conducive to reducing the current flow path in the power module 100, so as to reduce the stray inductance generated by the power module 100 at the moment of switch disconnection. In an embodiment of the utility model, the source of the first power chip 21 is electrically connected to the second DC region 13, and the source of the second power chip 31 is electrically connected to the AC region 11.

[0059] Combination Figure 2 and Figure 3 As shown, in the embodiment of the utility model, the structure for realizing electrical connection between the second power chip 31 and the AC region 11 includes but is not limited to at least one of an electrical connection wire, an electrical connection sheet, and an electrical connection belt, wherein the electrical connection wire includes but is not limited to a bonding wire. The structure for realizing electrical connection between the first power chip 21 and the first DC region 12 includes but is not limited to at least one of an electrical connection wire, an electrical connection sheet, and an electrical connection belt, wherein the electrical connection wire includes but is not limited to a bonding wire.

[0060] Combination Figure 1 and Figure 3 As shown, the second DC region 13 includes a first sub-DC region 131, a second sub-DC region 132 and a third sub-DC region 133. The first sub-DC region 131 extends in the first direction and is located between the first sub-AC region 111 and the first DC region 12. There are two second sub-DC regions 132, which are respectively arranged at the two ends of the first sub-DC region 131 in the first direction. The second sub-DC region 132 is extended in the second direction and is located between the second sub-AC region 112 and the first DC region 12. The third sub-DC region 133 is arranged at one end of the second sub-DC region 132 away from the first sub-DC region 131 and extends in the first direction. The third sub-DC region 133 and the second sub-AC region 112 are spaced apart in the second direction.

[0061] Specifically, the first sub-DC region 131 in the second DC region 13 is extended along the first direction between the first sub-AC region 111 and the first DC region 12. This not only ensures the basic structural independence of the first sub-DC region 131 and prevents short circuits in the internal circuits of the power module 100, but also enables the first sub-DC region 131 to be connected to the second sub-DC regions 132 arranged on both sides of the first direction of the power module 100 to ensure circuit connectivity within the DC region.

[0062] Furthermore, the two second sub-DC regions 132 in the second DC region 13 are respectively arranged at the two ends of the first direction of the first sub-DC region 131, so that the two second sub-DC regions 132 can correspond to the two second sub-AC regions 112 arranged at the two ends of the first direction of the first DC region 12. In this way, the extension direction of the two second sub-DC regions 132 is the same as the spacing direction of the multiple first power chips 21 on the two second sub-AC regions 112, which can facilitate the simultaneous electrical connection of the multiple first power chips 21 with the second sub-DC region 132, which is beneficial to shortening the distance between the second sub-DC region 132 and the multiple first power chips 21, and further beneficial to improving the integration of the power module 100 and shortening the current path in the power module 100.

[0063] Further, the third sub-DC region 133 in the second DC region 13 is used to set an external terminal to ensure the connection reliability between the second DC region 13 and the external circuit, and the third sub-DC region 133 can be far away from the first sub-AC region 111. The external terminal on the first sub-AC region 111 is an AC circulation channel, and the external terminal on the third sub-DC region 133 is a DC circulation channel. The third sub-DC region 133 is set at an end of the second sub-DC region 132 away from the first sub-DC region 131, so that the external terminal on the first sub-AC region 111 and the external terminal on the third sub-DC region 133 can be far away from each other, and the external AC circuit and the external DC circuit can be connected separately on the power module 100 to ensure the reliability of the power module 100.

[0064] Furthermore, the third DC sub-region 133 is extended in the first direction, which can increase the area of ​​the third branch sub-region on the substrate 10, and can improve the convenience of setting and the connection reliability of the external terminal and the second DC region 13. The third DC sub-region 133 and the second AC sub-region 112 are spaced apart in the second direction, so that the external terminal on the third DC sub-region 133 and the second AC sub-region 112 on the substrate 10 can be spaced apart from each other, which is conducive to improving the reliability of the DC circuit and the AC circuit in the power module 100.

[0065] Combination Figure 1-Figure 3 As shown, a first avoidance gap 121 is provided on the first DC region 12, a first source signal control area 1211 is provided in the first avoidance gap 121, the first source signal control area 1211 and the second power chip group 30 are alternately arranged in sequence in the second direction, the first source signal control area 1211 is provided with a first bonding resistor 1212, the first bonding resistor 1212 is electrically connected to the second power chip 31, and the first source signal control area 1211 is electrically connected to the second power chip 31.

[0066] Specifically, the first avoidance gap 121 in the first DC region 12 can provide a setting space for the first source signal control area 1211. The first source signal control area 1211 and the second power chip group 30 are alternately arranged in the second direction, so that the first source signal control area 1211 is arranged around each group of the second power chip group 30, so that the chips in the second power chip group 30 are electrically connected to the first source signal control area 1211, and then the first source signal control area 1211 can control the source current of the second power chip 31. The first source signal control area 1211 is provided with a first bonding resistor 1212, and the first bonding resistor 1212 and the first source signal control area 1211 are electrically connected to different areas of the second power chip 31 respectively. In an embodiment of the utility model, the gate of the second power chip 31 is electrically connected to the first bonding resistor 1212, and the first source signal control area 1211 is directly electrically connected to the Kelvin sampling area of ​​the second power chip 31.

[0067] In an embodiment of the utility model, a plurality of first avoidance gaps 121 and a plurality of first source signal control areas 1211 are provided, and the plurality of first avoidance gaps 121 correspond one-to-one to the plurality of first source signal control areas 1211, so that a plurality of first bonding resistors 1212 are provided on the substrate 10, and the number of the first bonding resistors 1212 corresponds to the number of the second power chips 31, so that the gate on each second power chip 31 is electrically connected to the corresponding first bonding resistor 1212.

[0068] Combination Figure 2 and Figure 3 As shown, in the embodiment of the utility model, the structure for realizing electrical connection between the first bonding resistor 1212 and the first power chip 21 includes but is not limited to at least one of an electrical connection wire, an electrical connection sheet, and an electrical connection belt, wherein the electrical connection wire includes but is not limited to a bonding wire. The structure for realizing electrical connection between the first source signal control region 1211 and the second power chip 31 includes but is not limited to at least one of an electrical connection wire, an electrical connection sheet, and an electrical connection belt, wherein the electrical connection wire includes but is not limited to a bonding wire.

[0069] Combination Figure 1 and Figure 3As shown, a second avoidance gap 122 is provided on a side of the first DC region 12 away from the first sub-AC region 111, and a first gate signal control area 1221 and a second source signal control area 1222 are provided in the second avoidance gap 122. The first gate signal control area 1221 and the second source signal control area 1222 are respectively provided with a first metal 12211 and a second metal 12221, the first metal 12211 and the first bonding resistor 1212 are electrically connected, the second metal 12221 and the first source signal control area 1211 are electrically connected, and the first gate signal control area 1221 and the second source signal control area 1222 are spaced apart in the second direction.

[0070] Specifically, the second avoidance gap 122 disposed on the side of the first DC region 12 away from the first sub-AC region 111 can provide a space for the first gate signal control region 1221 and the second source signal control region 1222. The first gate signal control region 1221 is provided with a first metal 12211, which is used to enable the first gate signal control region 1221 to receive and transmit electrical signals. The second source signal control region 1222 is provided with a second metal 12221, which is used to enable the second source signal control region 1222 to receive and transmit electrical signals.

[0071] Furthermore, the first metal 12211 and the first bonding resistor 1212 are electrically connected, so that the gate on the second power chip 31 can be electrically connected to the first gate signal control area 1221, so that the first gate signal control area 1221 controls the gate current on the second power chip 31. The second metal 12221 is electrically connected to the first source signal control area 1211, so that the second source signal control area 1222 can be electrically connected to the first source signal control area 1211, so that the second source signal control area 1222 can be electrically connected to the Kelvin sampling area on the second power chip 31, so as to monitor the working state and load condition of the second power chip 31, and ensure the working safety of the second power chip 31. The first gate signal control area 1221 and the second source signal control area 1222 are arranged in the second avoidance gap 122 along the second direction, which can ensure the structural reliability and working independence of the first gate signal control area 1221 and the second source signal control area 1222.

[0072] Combination Figure 2 and Figure 3 As shown, in the embodiment of the utility model, the structure for realizing electrical connection between the first metal 12211 and the first bonding resistor 1212 includes but is not limited to at least one of an electrical connection line, an electrical connection sheet, and an electrical connection belt, wherein the electrical connection line includes but is not limited to a bonding wire. The structure for realizing electrical connection between the second metal 12221 and the first source signal control area 1211 includes but is not limited to at least one of an electrical connection line, an electrical connection sheet, and an electrical connection belt, wherein the electrical connection line includes but is not limited to a bonding wire.

[0073] Combination Figure 1 and Figure 3 As shown, a second gate signal control region 123 and a third source signal control region 124 are arranged on a side of the first DC region 12 away from the first sub-AC region 111, the second gate signal control region 123, the third source signal control region 124 and the first DC region 12 are spaced apart in the second direction, a third metal 1231 is arranged on the second gate signal control region 123, a fourth metal 1241 is arranged on the third source signal control region 124, the first metal 12211 and the third metal 1231 are electrically connected, and the second metal 12221 and the fourth metal 1241 are electrically connected.

[0074] Specifically, the first metal 12211 and the third metal 1231 are electrically connected, so that the second gate signal control area 123 can be used to be electrically connected to the first gate signal control area 1221, and used to form a gate signal control circuit in the upper bridge circuit of the power module 100. The second metal 12221 is electrically connected to the fourth metal 1241, so that the third source signal control area 124 and the second source signal control area 1222 are electrically connected, and the first source signal control area 1211, the second source signal control area 1222 and the third source signal control area 124 can form a sampling circuit in the upper bridge circuit of the power module 100. In this way, the upper bridge circuit of the power module 100 can be formed, so that the upper bridge circuit of the power module 100 can work normally.

[0075] Combination Figure 2 and Figure 3 As shown, in the embodiment of the utility model, the structure for realizing electrical connection between the first metal 12211 and the third metal 1231 includes but is not limited to at least one of an electrical connection line, an electrical connection sheet, and an electrical connection belt, wherein the electrical connection line includes but is not limited to a bonding wire. The structure for realizing electrical connection between the second metal 12221 and the fourth metal 1241 includes but is not limited to at least one of an electrical connection line, an electrical connection sheet, and an electrical connection belt, wherein the electrical connection line includes but is not limited to a bonding wire.

[0076] Furthermore, by arranging the second gate signal control area 123 and the third source signal control area 124 on the substrate 10 on a side of the first DC region 12 away from the first sub-AC region 111, the upper bridge circuit of the power module 100 can be kept away from the first sub-AC region 111, and the control reliability of the gate current and the sampling current of the second power chip 31 in the upper bridge circuit of the power module 100 can be improved. The second gate signal control area 123, the third source signal control area 124 and the first DC region 12 are arranged at intervals in the second direction, which can make full use of the space in the second direction of the substrate 10, prevent the size of the power module 100 in the first direction from increasing, and help improve the integration of the power module 100 and reduce the overall size of the power module 100.

[0077] Combination Figure 2 and Figure 3 As shown, in the embodiment of the present utility model, a drain sampling region 14 is further provided on one side of the first DC region 12 away from the first sub-AC region 111, and the drain sampling region 14 is electrically connected to the second sub-AC region 112. The structure for realizing the electrical connection between the drain sampling region 14 and the second sub-AC region 112 includes but is not limited to at least one of an electrical connection wire, an electrical connection sheet, and an electrical connection belt, wherein the electrical connection wire includes but is not limited to a bonding wire.

[0078] Combination Figure 1 and Figure 3 As shown, the third avoidance gap 113 is provided on the side of the two second sub-AC regions 112 that are away from each other in the first direction, the third avoidance gap 113 is provided with a fourth source signal control area 114, the fourth source signal control area 114 is provided with a second bonding resistor 1141, and the first power chip 21 is electrically connected to the second bonding resistor 1141 and the fourth source signal control area 114 respectively. Specifically, the third avoidance gap 113 is provided at the position where the two second sub-AC regions 112 are away from each other along the first direction, which can not only provide a setting space for the fourth source signal control area 114, but also prevent the fourth source signal control area 114 from occupying the space between the second sub-AC region 112 and the second power chip 31, which is conducive to reducing the current path between the second sub-AC region 112 and the second power chip 31, and can reduce the stray inductance in the power module 100, which is conducive to reducing the switching loss of the power module 100.

[0079] Furthermore, a second bonding resistor 1141 is provided on the fourth source signal control area 114, and the second bonding resistor 1141 and the fourth source signal control area 114 are respectively electrically connected to different areas of the first power chip 21. In an embodiment of the present utility model, the gate on the first power chip 21 is electrically connected to the second bonding resistor 1141, and the Kelvin sampling area of ​​the first power chip 21 is directly electrically connected to the fourth source signal control area 114.

[0080] In an embodiment of the utility model, a plurality of third avoidance gaps 113 and a plurality of fourth source signal control areas 114 are provided, and the plurality of third avoidance gaps 113 and the plurality of fourth source signal control areas 114 correspond to each other one by one and are symmetrically arranged about a center line extending in the second direction of the substrate 10, so that a plurality of second bonding resistors 1141 can be provided on the substrate 10, and the plurality of second bonding resistors 1141 and the plurality of first power chips 21 are arranged in sequence along the second direction at intervals so that the gate on each first power chip 21 is electrically connected to the second bonding resistor 1141.

[0081] Combination Figure 2 and Figure 3 As shown, in the embodiment of the utility model, the structure for realizing electrical connection between the first power chip 21 and the second bonding resistor 1141 includes but is not limited to at least one of an electrical connection line, an electrical connection sheet, and an electrical connection belt, wherein the electrical connection line includes but is not limited to a bonding wire. The structure for realizing electrical connection between the first power chip 21 and the fourth source signal control area 114 includes but is not limited to at least one of an electrical connection line, an electrical connection sheet, and an electrical connection belt, wherein the electrical connection line includes but is not limited to a bonding wire.

[0082] Combination Figure 1 and Figure 3 As shown, a fifth source signal control region 115 and a third gate signal control region 116 are provided on the side of the first sub-AC region 111 away from the first DC region 12. The fifth source signal control region 115, the third gate signal control region 116 and the AC region 11 are spaced apart in the second direction. A fifth metal 1151 and a sixth metal 1161 are respectively provided on the fifth source signal control region 115 and the third gate signal control region 116. The fifth metal 1151 is electrically connected to the fourth source signal control region 114, and the sixth metal 1161 is electrically connected to the second bonding resistor 1141.

[0083] Specifically, the fifth metal 1151 is electrically connected to the fourth source signal control area 114, so that the fifth source signal control area 115 is electrically connected to the Kelvin sampling area of ​​the first power chip 21 to form a sampling control circuit in the lower bridge circuit of the power module 100. The sixth metal 1161 is electrically connected to the second bonding resistor 1141, so that the third gate signal control area 116 is electrically connected to the gate on the first power chip 21 to form a gate current control circuit in the lower bridge circuit of the power module 100. In this way, the lower bridge circuit of the power module 100 can be formed, so that the lower bridge circuit of the power module 100 can work normally.

[0084] Combination Figure 2 and Figure 3As shown, in the embodiment of the utility model, the structure for realizing electrical connection between the fifth metal 1151 and the fourth source signal control area 114 includes but is not limited to at least one of an electrical connection line, an electrical connection sheet and an electrical connection belt, wherein the electrical connection line includes but is not limited to a bonding wire. The structure for realizing electrical connection between the sixth metal 1161 and the second bonding resistor 1141 includes but is not limited to at least one of an electrical connection line, an electrical connection sheet and an electrical connection belt, wherein the electrical connection line includes but is not limited to a bonding wire.

[0085] According to the embodiment of the utility model, the power module 100 can be applied to power electronic equipment, and the power electronic equipment equipped with the power module 100 of the utility model can be applied to vehicles. The power module 100 of the utility model generates lower stray inductance and less switching loss during the startup process, which can make the structure of the power module 100 used in the power electronic equipment in the vehicle more reliable and have a longer service life, thereby helping to improve the working reliability and service life of the power electronic equipment, and further helping to reduce the cost of vehicle use and maintenance.

[0086] In the description of the present invention, it needs to be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "circumferential", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present invention.

[0087] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the utility model. In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment or example.

[0088] Although the embodiments of the present invention have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the claims and their equivalents.

Claims

1. A power module, characterized in that: include: A substrate (10), wherein an AC region (11) and a first DC region (12) are arranged on the substrate (10), and the AC region (11) and the first DC region (12) are arranged at intervals; a first power chip (21), wherein the first power chip (21) is arranged in the AC region (11) and is in plurality, wherein the plurality of first power chips (21) form a first power chip group (20), and the first power chip group (20) comprises at least two first power chips (21) arranged at intervals in a first direction; A second power chip (31), wherein the second power chip (31) is arranged in the first DC region (12) and is in plurality, wherein the plurality of second power chips (31) form a second power chip group (30), wherein the second power chip group (30) comprises at least two second power chips (31) arranged at intervals in a first direction, wherein two first power chips (21) in the first power chip group (20) are respectively arranged on both sides of the second power chip group (30) in the first direction, and wherein the first power chip group (20) and the second power chip group (30) are symmetrically arranged about a center line extending in a second direction of the substrate (10), wherein the first direction and the second direction are perpendicular to each other.

2. The power module according to claim 1, characterized in that: There are a plurality of the first power chipset (20), and the plurality of the first power chipset (20) are arranged at intervals in the second direction; there are a plurality of the second power chipset (30), and the plurality of the second power chipset (30) are arranged at intervals in the second direction; the plurality of the first power chipset (20) and the plurality of the second power chipset (30) correspond one to one; and the plurality of the first power chipset (20) and the plurality of the second power chipset (30) are symmetrically arranged about a center line extending in the second direction of the substrate (10).

3. The power module according to claim 2, characterized in that: A plane perpendicular to the substrate (10) and extending in the second direction is set as a reference plane, and projections of the first power chip groups (20) and the second power chip groups (30) on the reference plane are at least partially offset from each other.

4. The power module according to claim 3, characterized in that: The AC region (11) comprises a first sub-AC region (111) and a second sub-AC region (112); the first sub-AC region (111) extends in a first direction and is spaced apart from the first DC region (12) in a second direction; the second sub-AC region (112) is two and is respectively connected to two ends of the first sub-AC region (111) in the first direction; the second sub-AC region (112) is extended in the second direction; the two second sub-AC regions (112) are respectively located on two sides of the first DC region (12) in the first direction and are spaced apart from the first DC region (12).

5. The power module according to claim 4, characterized in that: The exchange region (11) is symmetrically arranged with respect to a center line extending in the second direction of the substrate (10).

6. The power module according to claim 4, characterized in that: The substrate (10) is further provided with a second DC region (13), the second DC region (13) being located between the first DC region (12) and the AC region (11), the second DC region (13) being electrically connected to the first power chip (21), and the AC region (11) being electrically connected to the second power chip (31).

7. The power module according to claim 6, characterized in that: The second DC region (13) comprises a first sub-DC region (131), a second sub-DC region (132) and a third sub-DC region (133); the first sub-DC region (131) extends in a first direction and is located between the first sub-AC region (111) and the first DC region (12); the second sub-DC region (132) is two and is respectively arranged at two ends of the first sub-DC region (131) in the first direction; the second sub-DC region (132) is extended in a second direction and is located between the second sub-AC region (112) and the first DC region (12); the third sub-DC region (133) is arranged at one end of the second sub-DC region (132) away from the first sub-DC region (131) and extends in the first direction; the third sub-DC region (133) and the second sub-AC region (112) are spaced apart in the second direction.

8. The power module according to claim 7, characterized in that: The first DC region (12) is provided with a first avoidance notch (121), the first avoidance notch (121) is provided with a first source signal control area (1211), the first source signal control area (1211) and the second power chip group (30) are arranged alternately in sequence in a second direction, the first source signal control area (1211) is provided with a first bonding resistor (1212), the first bonding resistor (1212) is electrically connected to the second power chip (31), and the first source signal control area (1211) is electrically connected to the second power chip (31).

9. The power module according to claim 8, characterized in that: A second avoidance gap (122) is provided on a side of the first DC region (12) away from the first sub-AC region (111); a first gate signal control area (1221) and a second source signal control area (1222) are provided in the second avoidance gap (122); the first gate signal control area (1221) and the second source signal control area (1222) are respectively provided with a first metal (12211) and a second metal (12221); the first metal (12211) and the first bonding resistor (1212) are electrically connected; the second metal (12221) and the first source signal control area (1211) are electrically connected; the first gate signal control area (1221) and the second source signal control area (1222) are spaced apart in a second direction.

10. The power module according to claim 9, characterized in that: A second gate signal control region (123) and a third source signal control region (124) are arranged on a side of the first DC region (12) away from the first sub-AC region (111); the second gate signal control region (123), the third source signal control region (124) and the first DC region (12) are arranged at intervals in a second direction; a third metal (1231) is arranged on the second gate signal control region (123); a fourth metal (1241) is arranged on the third source signal control region (124); the first metal (12211) and the third metal (1231) are electrically connected; and the second metal (12221) and the fourth metal (1241) are electrically connected.

11. The power module according to claim 7, characterized in that: A third avoidance gap (113) is provided on one side of the two second AC sub-regions (112) that are away from each other in the first direction; a fourth source signal control area (114) is provided in the third avoidance gap (113); a second bonding resistor (1141) is provided on the fourth source signal control area (114); and the first power chip (21) is electrically connected to the second bonding resistor (1141) and the fourth source signal control area (114), respectively.

12. The power module according to claim 11, characterized in that: A fifth source signal control region (115) and a third gate signal control region (116) are arranged on a side of the first sub-AC region (111) away from the first DC region (12); the fifth source signal control region (115), the third gate signal control region (116) and the AC region (11) are arranged at intervals in the second direction; a fifth metal (1151) and a sixth metal (1161) are arranged on the fifth source signal control region (115) and the third gate signal control region (116), respectively; the fifth metal (1151) is electrically connected to the fourth source signal control region (114), and the sixth metal (1161) is electrically connected to the second bonding resistor (1141).

13. A power electronic device, characterized in that: A power module (100) comprising any one of claims 1 to 12.

14. A vehicle, characterized in that: The invention comprises the power electronic device as claimed in claim 13.

Images