Input detection current-limiting turn-off control circuit

Abstract

The utility model discloses an input detection current-limiting turn-off control circuit, and relates to the technical field of product test detection circuits. According to the utility model, input voltage detection, input current detection, detection indication and alarm, input current limitation, detection turn-off input protection post-stage circuit and alarm entering a locking state can be realized, the detection speed can reach an ns level, and the circuit is added at the input end of a product to limit transient current limiting, detect and turn off power supply input and protect the post-stage circuit, so that the reliability of the product is improved. A test product can be effectively prevented from being damaged; voltage and current detection can be realized by replacing a resistor, a detection resistor is connected in series at a power supply end, voltages at two ends of a detection resistor RSV are compared through an nS-stage voltage comparator U2, and if the voltage passing through the detection resistor RSV is lower than a set value, the voltage comparator U2 outputs a high level and sends the high level to a next-stage D latch U3; the resistance can be adjusted, and the input current can be limited.

Description

Technical Field

[0001] The utility model relates to the technical field of product testing detection circuits, in particular to an input detection current limiting shutdown control circuit. Background Art

[0002] Chip testing methods include principle analysis, electrical characteristics testing, appearance inspection, packaging testing and other aspects; electrical characteristics testing is to test the electrical performance of the chip, which requires the use of professional testing instruments and equipment. The electrical characteristics of the chip can be tested through the connection pins of the test instrument to obtain the electrical characteristics data of the chip. Chip electrical testing includes DC parameter testing, AC parameter testing and high-speed digital signal performance testing. The items for chip electrical characteristics testing include voltage, current, electric field, impedance, magnetic field, EDM, response time, etc. Electrical testing is an important part of evaluating chip performance, ensuring the reliability and stability of the chip and ensuring its normal operation.

[0003] Traditional product testing basically uses a constant voltage power supply for electrical testing, but the current and voltage are not detected and limited during the test. During the chip product testing process, the product cannot be protected due to product defects and is damaged. Utility Model Content

[0004] The purpose of the utility model is to provide an input detection current limiting shutdown control circuit to solve the problems raised in the above background technology.

[0005] In order to solve the above technical problems, the utility model provides the following technical solutions:

[0006] An input detection current limiting shutdown control circuit comprises an input voltage and current detection circuit, an overcurrent locking circuit, an alarm circuit and a subsequent protection circuit, wherein the output end of the input voltage and current detection circuit is electrically connected to the input end of the overcurrent locking circuit and the subsequent protection circuit respectively, and the input end of the alarm circuit and the subsequent protection circuit is electrically connected to the output end of the overcurrent locking circuit respectively.

[0007] Preferably, the input voltage and current detection circuit includes an input interface J1, a diode DS0, a resistor RJ0, a resistor RJ1, a resistor R3, a resistor R5, a differential proportional amplifier U1, a resistor R7, a diode DS1, a resistor R9, a voltage comparator U2, and a resistor RSV;

[0008] The 1 interface of the input interface J1, the diode DS0, the resistor RJ0, the resistor RJ1, the resistor R3, the resistor R5 and the 4 interface of the differential proportional amplifier U1 are connected in series in sequence;

[0009] The connection line between the diode DS0 and the resistor RJ0 is externally connected to the resistor R1 and the resistor RJ2, and the resistor R1 is electrically connected to the 3 interface of the differential proportional amplifier U1 through the resistor R6; the resistor RJ2 is electrically connected between the resistor RJ1 and the resistor R3 through the resistor RJ3;

[0010] The 4th interface of the differential proportional amplifier U1 is connected to the 1th interface of the differential proportional amplifier U1 through the resistor R7, and the 1th interface of the differential proportional amplifier U1, the diode DS1, the resistor R9 and the 3rd interface of the voltage comparator U2 are connected in series in sequence; the resistor RSV is electrically connected between the 3rd interface of the voltage comparator U2 and the 1th interface of the voltage comparator U2;

[0011] An external 12V terminal is connected between the input interface J1 and the diode DS0, an external resistor R2 is connected between the resistor R1 and the resistor R6, an external resistor R4 is connected between the resistor R3 and the resistor R5, an external resistor R8 is connected between the resistor R6 and the 3 interface of the differential proportional amplifier U1, an external 5V terminal is connected to the 5 interface of the differential proportional amplifier U1, an external capacitor C1 is connected between the 5 interface and the 5V terminal of the differential proportional amplifier U1, and the resistor R2, the resistor R4, the resistor R8, the capacitor C1 and the 2 interface of the differential proportional amplifier U1 are grounded respectively;

[0012] A resistor RS1, a capacitor CU1 and a resistor RX1 are externally connected between the diode DS1 and the resistor R9. The resistor RS1 is externally connected to a 5V terminal, and the capacitor CU1 and the resistor RX1 are both grounded.

[0013] Preferably, capacitor CC0, capacitor CC1, capacitor CC3, transient voltage suppression diode TVS1 and resistor RR0 are externally connected between the 12V terminal and the diode DS0, the resistor RR0 is connected in series with the power indicator LED1, the capacitor CC3 is grounded, and the capacitor CC0, capacitor CC1, transient voltage suppression diode TVS1 and power indicator LED1 are all grounded in parallel;

[0014] Interfaces 2 and 3 of the input interface J1 are electrically connected between the 12V terminal and the diode DS0;

[0015] Interfaces 4 and 5 of the input interface J1 are both grounded.

[0016] Preferably, the 4th interface of the voltage comparator U2 is externally connected to a resistor R10, the resistor R10 is externally connected to a 5V terminal, and a resistor R11 is externally connected between the 4th interface of the voltage comparator U2 and the resistor R10, and the resistor R11 is grounded;

[0017] The 5 interface of the voltage comparator U2 is externally connected to the 5V terminal, and a capacitor C2 is externally connected between the 5 interface of the voltage comparator U2 and the 5V terminal; the capacitor C2 and the 2 interface of the voltage comparator U2 are grounded respectively;

[0018] The 1 interface of the voltage comparator U2 is connected to the resistor RSV through the resistor R12, and the resistor RS2, the resistor RX2 and the capacitor CU2 are externally connected between the 1 interface of the voltage comparator U2 and the resistor R12, and the resistor RS2 is externally connected to the 5V terminal; the resistor RX2 and the capacitor CU2 are both grounded;

[0019] The over-current locking circuit includes a D latch U3 and a NOT gate U4;

[0020] The resistor R12 is connected to the 4 interface of the D latch U3, the 16 interface of the D latch U3 is connected to the 5V terminal, an external capacitor C3 is connected between the 16 interface of the D latch U3 and the 5V terminal, and the 6 interface of the D latch U3 is connected between the 16 interface of the D latch U3 and the capacitor C3; the capacitor C3 and the 8 interface of the D latch U3 are grounded respectively;

[0021] Interface 5 of the D latch U3 is connected to interface 7 of the NAND gate U4, and interface 2 of the D latch U3 is connected to interface 1 of the NAND gate U4; interface 2 of the NAND gate U4 is externally connected to the 5V terminal through resistor R13; interface 8 of the NAND gate U4 is externally connected to the 5V terminal; interface 4 of the NAND gate U4 is grounded.

[0022] Preferably, the post-stage protection circuit includes a transistor T1, a MOS transistor Q1 and an output interface J2;

[0023] The 3rd interface of the D latch U3, the resistor R17, the B electrode of the transistor T1, the E electrode of the transistor T1, the S electrode of the MOS transistor Q1, the G electrode of the MOS transistor Q1 and the C electrode of the transistor T1 are sequentially connected in series, the D electrode of the MOS transistor Q1 is connected to the 1st interface of the output interface J2, the 2nd interface of the output interface J2 and the 3rd interface of the output interface J2, and the 4th interface of the output interface J2 and the 5th interface of the output interface J2 are both grounded;

[0024] The S pole of the MOS tube Q1 is electrically connected between the resistor RJ1 and the resistor R3;

[0025] A capacitor C4 is connected in parallel to the S pole of the MOS tube Q1 and the D pole of the MOS tube Q1, a resistor R20 and a voltage-stabilizing diode Zener are connected in parallel to the C pole of the transistor T1 and the E pole of the transistor T1, the resistor R20 and the voltage-stabilizing diode Zener are connected in parallel, an external resistor R19 is connected between the C pole of the transistor T1 and the G pole of the MOS tube Q1, and the resistor R19 is grounded;

[0026] A resistor R18 and a capacitor C5 are externally connected between the resistor R17 and the B pole of the transistor T1; the resistor R18 is externally connected to the 5V terminal, and the capacitor C5 is grounded; a VOUT_12V terminal is externally connected between the D pole of the MOS tube Q1 and the 1 interface of the output interface J2.

[0027] Preferably, the alarm circuit includes a resistor R14, a transistor T2, and a buzzer BZ1;

[0028] The resistor 14, the B pole of the transistor T2, the C pole of the transistor T2, the buzzer BZ1 and the resistor R16 are connected in series in sequence, the resistor 14 is connected between the 2 interface of the D latch U3 and the 1 interface of the NOT gate U4, and the resistor R16 is externally connected to the 5V terminal; the buzzer interface J5 and the diode DS3 are connected in parallel to the outside of the buzzer BZ1; the resistor R15 is connected in parallel to the outside of the B pole of the transistor T2 and the E pole of the transistor T2, and the E pole of the transistor T2 is grounded.

[0029] Compared with the prior art, the beneficial effects achieved by the utility model are:

[0030] The circuit of the utility model can realize input voltage detection, input current detection, detection indication and alarm, input current limitation, detection and shutting down of input protection circuit, alarm entering lock state, and detection speed can reach ns level by setting input voltage and current detection circuit, overcurrent locking circuit, alarm circuit and post-stage protection circuit. The circuit is added to the input end of the product to limit transient current limiting and detect and shut down the power input, protect the post-stage circuit, and effectively avoid damage to the test product. When the input voltage and current detection circuit performs input voltage detection: by replacing the resistor, voltage detection is realized, the detection resistor is connected in series at the power supply end, and the voltage across the detection resistor RSV is compared by the nS-level voltage comparator U2. If the voltage after passing through the detection resistor RSV is lower than the set value, the voltage comparator U2 outputs a high level and sends it to the next-level D latch U3. When the input voltage and current detection circuit performs input current detection: by replacing the resistor, current detection is realized, a current detection resistor is connected in series at the power supply end, and the voltage across the current detection resistor is amplified by the nS-level differential proportional amplifier U1 and sent to the next-level voltage comparator U2. The resistance value is adjusted to limit the input current. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The accompanying drawings are used to provide a further understanding of the present invention and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the present invention and do not constitute a limitation of the present invention. In the accompanying drawings:

[0032] Figure 1 It is a circuit diagram of the utility model as a whole;

[0033] Figure 2It is a circuit diagram of the input voltage and current detection circuit of the utility model;

[0034] Figure 3 It is a circuit diagram of the overcurrent locking circuit of the utility model;

[0035] Figure 4 It is a circuit diagram of the rear-stage protection circuit of the utility model;

[0036] Figure 5 It is a circuit diagram of the alarm circuit of the utility model. DETAILED DESCRIPTION

[0037] The following will be combined with the drawings in the embodiments of the utility model to clearly and completely describe the technical solutions in the embodiments of the utility model. Obviously, the described embodiments are only part of the embodiments of the utility model, not all of the embodiments. Based on the embodiments in the utility model, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the utility model.

[0038] refer to Figure 1-Figure 5The utility model provides a technical solution: an input detection current limiting shutdown control circuit, including an input voltage and current detection circuit, an overcurrent locking circuit, an alarm circuit and a post-stage protection circuit, wherein the output end of the input voltage and current detection circuit is electrically connected to the overcurrent locking circuit and the input end of the post-stage protection circuit respectively, and the input end of the alarm circuit and the post-stage protection circuit is electrically connected to the output end of the overcurrent locking circuit respectively; the input voltage and current detection circuit includes an input interface J1, a diode DS0, a resistor RJ0, a resistor RJ1, a resistor R3, a resistor R5, a differential ratio For example, an amplifier U1, a resistor R7, a diode DS1, a resistor R9, a voltage comparator U2, and a resistor RSV; the 1 interface of the input interface J1, the diode DS0, the resistor RJ0, the resistor RJ1, the resistor R3, the resistor R5, and the 4 interface of the differential proportional amplifier U1 are connected in series in sequence; the connection line between the diode DS0 and the resistor RJ0 is externally connected to the resistor R1 and the resistor RJ2, and the resistor R1 is electrically connected to the 3 interface of the differential proportional amplifier U1 through the resistor R6; the resistor RJ2 is electrically connected to the resistor RJ1 and the resistor R3 through the resistor RJ3 The 4th interface of the differential proportional amplifier U1 is connected to the 1st interface of the differential proportional amplifier U1 through the resistor R7, and the 1st interface of the differential proportional amplifier U1, the diode DS1, the resistor R9 and the 3rd interface of the voltage comparator U2 are connected in series in sequence; the resistor RSV is electrically connected between the 3rd interface of the voltage comparator U2 and the 1st interface of the voltage comparator U2; the 12V terminal is externally connected between the input interface J1 and the diode DS0, the resistor R2 is externally connected between the resistor R1 and the resistor R6, and the resistor R4 is externally connected between the resistor R3 and the resistor R5. An external resistor R8 is connected between the resistor R6 and the 3 interface of the differential proportional amplifier U1, the 5 interface of the differential proportional amplifier U1 is externally connected to the 5V terminal, the capacitor C1 is externally connected between the 5 interface and the 5V terminal of the differential proportional amplifier U1, and the resistor R2, resistor R4, resistor R8, capacitor C1 and the 2 interface of the differential proportional amplifier U1 are grounded respectively; an external resistor RS1, capacitor CU1 and resistor RX1 are connected between the diode DS1 and the resistor R9, the resistor RS1 is externally connected to the 5V terminal, and the capacitor CU1 and the resistor RX1 are both grounded.

[0039] The 4th interface of the voltage comparator U2 is externally connected to a resistor R10, and the resistor R10 is externally connected to a 5V terminal. A resistor R11 is externally connected between the 4th interface of the voltage comparator U2 and the resistor R10, and the resistor R11 is grounded; the 5th interface of the voltage comparator U2 is externally connected to a 5V terminal, and a capacitor C2 is externally connected between the 5th interface of the voltage comparator U2 and the 5V terminal; the capacitor C2 and the 2nd interface of the voltage comparator U2 are grounded respectively; the 1st interface of the voltage comparator U2 is connected to the resistor RSV through the resistor R12, and the 1st interface of the voltage comparator U2 and the resistor R12 are externally connected to a resistor RS2, a resistor RX2 and a capacitor CU2, and the resistor RS2 is externally connected to a 5V terminal; the resistor RX2 and the capacitor CU2 are both grounded; the overcurrent The locking circuit includes a D latch U3 and a negative gate U4; the resistor R12 is connected to the 4 interface of the D latch U3, the 16 interfaces of the D latch U3 are all connected to the 5V terminal, the 16 interface of the D latch U3 and the 5V terminal are externally connected to a capacitor C3, and the 6 interface of the D latch U3 is connected between the 16 interface of the D latch U3 and the capacitor C3; the capacitor C3 and the 8 interface of the D latch U3 are grounded respectively; the 5 interface of the D latch U3 is connected to the 7 interface of the negative gate U4, and the 2 interface of the D latch U3 is connected to the 1 interface of the negative gate U4; the 2 interface of the negative gate U4 is externally connected to the 5V terminal through the resistor R13; the 8 interface of the negative gate U4 is externally connected to the 5V terminal; the 4 interface of the negative gate U4 is grounded.

[0040] The post-stage protection circuit includes a transistor T1, a MOS transistor Q1 and an output interface J2; the 3rd interface of the D latch U3, the resistor R17, the B pole of the transistor T1, the E pole of the transistor T1, the S pole of the MOS transistor Q1, the G pole of the MOS transistor Q1 and the C pole of the transistor T1 are connected in series in sequence, the D pole of the MOS transistor Q1 is connected to the 1st interface of the output interface J2, the 2nd interface of the output interface J2 and the 3rd interface of the output interface J2, and the 4th interface of the output interface J2 and the 5th interface of the output interface J2 are both grounded; the S pole of the MOS transistor Q1 is electrically connected between the resistor RJ1 and the resistor R3; the S pole of the MOS transistor Q1 is electrically connected to ... A capacitor C4 is connected in parallel to the outer side of the D pole of the MOS tube Q1, a resistor R20 and a voltage stabilizing diode Zener are connected in parallel to the outer side of the C pole of the transistor T1 and the E pole of the transistor T1, the resistor R20 and the voltage stabilizing diode Zener are connected in parallel, an external resistor R19 is connected between the C pole of the transistor T1 and the G pole of the MOS tube Q1, and the resistor R19 is grounded; an external resistor R18 and a capacitor C5 are connected between the resistor R17 and the B pole of the transistor T1; the resistor R18 is externally connected to a 5V terminal, and the capacitor C5 is grounded; a VOUT_12V terminal is externally connected between the D pole of the MOS tube Q1 and the 1 interface of the output interface J2.

[0041] The alarm circuit includes a resistor R14, a transistor T2, and a buzzer BZ1; the resistor 14, the B pole of the transistor T2, the C pole of the transistor T2, the buzzer BZ1 and the resistor R16 are connected in series in sequence, the resistor 14 is connected between the 2 interface of the D latch U3 and the 1 interface of the NOT gate U4, and the resistor R16 is externally connected to the 5V terminal; the buzzer interface J5 and the diode DS3 are connected in parallel to the outside of the buzzer BZ1; the resistor R15 is connected in parallel to the outside of the B pole of the transistor T2 and the E pole of the transistor T2, and the E pole of the transistor T2 is grounded.

[0042] Capacitor CC0, capacitor CC1, capacitor CC3, transient voltage suppression diode TVS1 and resistor RR0 are externally connected between the 12V terminal and the diode DS0. The resistor RR0 is connected in series with the power indicator LED1, and the capacitor CC3 is grounded. The capacitor CC0, capacitor CC1, transient voltage suppression diode TVS1 and power indicator LED1 are all grounded in parallel; interface 2 and interface 3 of the input interface J1 are electrically connected between the 12V terminal and the diode DS0; interface 4 and interface 5 of the input interface J1 are both grounded; capacitor CC0, capacitor CC1, capacitor CC3 can add capacitor filtering to the input voltage and current detection circuit, transient voltage suppression diode TVS1 can add TVS surge protection function to the input voltage and current detection circuit, diode DS0 is reverse polarity protected and the power indicator LED1 is protected; adding filtering, surge protection and reverse polarity protection performance to the input voltage and current detection circuit can effectively improve the safety of the detection circuit.

[0043] Specific working principle: The utility model can realize input voltage detection, input current detection, detection indication and alarm, input current limitation, detection and shutdown of input protection circuit, alarm and lock state by setting input voltage and current detection circuit, overcurrent lock circuit, alarm and lock state, and the detection speed can reach ns level. This circuit is added to the input end of the product to limit transient current limiting and detect and shut down the power input to protect the subsequent circuit, which can effectively avoid damage to the test product;

[0044] When the input voltage and current detection circuit performs input voltage detection: the voltage detection is realized by replacing the resistor, the detection resistor is connected in series at the power supply end, and the voltage across the detection resistor RSV is compared by the nS-level voltage comparator U2. If the voltage after passing through the detection resistor RSV is lower than the set value, the voltage comparator U2 outputs a high level and sends it to the next-level D latch U3; when the input voltage and current detection circuit performs input current detection: the current detection is realized by replacing the resistor, the current detection resistor is connected in series at the power supply end, and the voltage across the current detection resistor is amplified by the nS-level differential proportional amplifier U1 and sent to the next-level voltage comparator U2. The input current can be limited by adjusting the resistance value;

[0045] Overcurrent lock circuit: When the input voltage of the voltage comparator U2 is higher than the set value, it outputs a high level to drive the D latch U3. On the one hand, the 3 interface of the D latch U3 outputs a high level, and at the same time, the NAND gate U4 outputs a low level to the D latch U3 to lock the state. On the other hand, the 2 interface of the D latch U3 outputs a low level to the transistor T2 of the alarm circuit.

[0046] Alarm circuit: After transistor T2 obtains a high level, it drives buzzer BZ1 to produce sound;

[0047] Post-stage protection circuit: The transistor T1 is turned on after obtaining a low level, short-circuiting the G and S poles of the MOS tube Q1, so that the MOS tube Q1 is cut off, thereby shutting off the power supply to protect the post-stage circuit, and at the same time the power indicator light at the input end goes out.

[0048] Finally, it should be noted that the above description is only a preferred embodiment of the utility model and is not intended to limit the utility model. Although the utility model is described in detail with reference to the above embodiments, those skilled in the art can still modify the technical solutions recorded in the above embodiments or replace some of the technical features therein by equivalents. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the utility model shall be included in the protection scope of the utility model.

Claims

1. An input detection current limiting shutdown control circuit, comprising an input voltage and current detection circuit, an overcurrent locking circuit, an alarm circuit and a post-stage protection circuit, characterized in that: The output end of the input voltage and current detection circuit is electrically connected to the overcurrent locking circuit and the input end of the subsequent protection circuit respectively, and the input ends of the alarm circuit and the subsequent protection circuit are electrically connected to the output end of the overcurrent locking circuit respectively.

2. The input detection current limiting shutdown control circuit according to claim 1, characterized in that: The input voltage and current detection circuit includes an input interface J1, a diode DS0, a resistor RJ0, a resistor RJ1, a resistor R3, a resistor R5, a differential proportional amplifier U1, a resistor R7, a diode DS1, a resistor R9, a voltage comparator U2, and a resistor RSV; The 1 interface of the input interface J1, the diode DS0, the resistor RJ0, the resistor RJ1, the resistor R3, the resistor R5 and the 4 interface of the differential proportional amplifier U1 are connected in series in sequence; The connection line between the diode DS0 and the resistor RJ0 is externally connected to the resistor R1 and the resistor RJ2, and the resistor R1 is electrically connected to the 3 interface of the differential proportional amplifier U1 through the resistor R6; the resistor RJ2 is electrically connected between the resistor RJ1 and the resistor R3 through the resistor RJ3; The 4th interface of the differential proportional amplifier U1 is connected to the 1th interface of the differential proportional amplifier U1 through the resistor R7, and the 1th interface of the differential proportional amplifier U1, the diode DS1, the resistor R9 and the 3rd interface of the voltage comparator U2 are connected in series in sequence; the resistor RSV is electrically connected between the 3rd interface of the voltage comparator U2 and the 1th interface of the voltage comparator U2; An external 12V terminal is connected between the input interface J1 and the diode DS0, an external resistor R2 is connected between the resistor R1 and the resistor R6, an external resistor R4 is connected between the resistor R3 and the resistor R5, an external resistor R8 is connected between the resistor R6 and the 3 interface of the differential proportional amplifier U1, an external 5V terminal is connected to the 5 interface of the differential proportional amplifier U1, an external capacitor C1 is connected between the 5 interface and the 5V terminal of the differential proportional amplifier U1, and the resistor R2, the resistor R4, the resistor R8, the capacitor C1 and the 2 interface of the differential proportional amplifier U1 are grounded respectively; A resistor RS1, a capacitor CU1 and a resistor RX1 are externally connected between the diode DS1 and the resistor R9. The resistor RS1 is externally connected to a 5V terminal, and the capacitor CU1 and the resistor RX1 are both grounded.

3. The input detection current limiting shutdown control circuit according to claim 2, characterized in that: A capacitor CC0, a capacitor CC1, a capacitor CC3, a transient voltage suppressor diode TVS1 and a resistor RR0 are externally connected between the 12V terminal and the diode DS0, the resistor RR0 is connected in series with the power indicator LED1, the capacitor CC3 is grounded, and the capacitor CC0, the capacitor CC1, the transient voltage suppressor diode TVS1 and the power indicator LED1 are all grounded in parallel; Interfaces 2 and 3 of the input interface J1 are electrically connected between the 12V terminal and the diode DS0; Interfaces 4 and 5 of the input interface J1 are both grounded.

4. The input detection current limiting shutdown control circuit according to claim 2, characterized in that: The 4th interface of the voltage comparator U2 is externally connected to a resistor R10, the resistor R10 is externally connected to a 5V terminal, and an external resistor R11 is connected between the 4th interface of the voltage comparator U2 and the resistor R10, and the resistor R11 is grounded; The 5 interface of the voltage comparator U2 is externally connected to the 5V terminal, and a capacitor C2 is externally connected between the 5 interface of the voltage comparator U2 and the 5V terminal; the capacitor C2 and the 2 interface of the voltage comparator U2 are grounded respectively; The 1 interface of the voltage comparator U2 is connected to the resistor RSV through the resistor R12, and the resistor RS2, the resistor RX2 and the capacitor CU2 are externally connected between the 1 interface of the voltage comparator U2 and the resistor R12, and the resistor RS2 is externally connected to the 5V terminal; the resistor RX2 and the capacitor CU2 are both grounded; The over-current locking circuit includes a D latch U3 and a NOT gate U4; The resistor R12 is connected to the 4 interface of the D latch U3, the 16 interface of the D latch U3 is connected to the 5V terminal, an external capacitor C3 is connected between the 16 interface of the D latch U3 and the 5V terminal, and the 6 interface of the D latch U3 is connected between the 16 interface of the D latch U3 and the capacitor C3; the capacitor C3 and the 8 interface of the D latch U3 are grounded respectively; Interface 5 of the D latch U3 is connected to interface 7 of the NAND gate U4, and interface 2 of the D latch U3 is connected to interface 1 of the NAND gate U4; interface 2 of the NAND gate U4 is externally connected to the 5V terminal through resistor R13; interface 8 of the NAND gate U4 is externally connected to the 5V terminal; interface 4 of the NAND gate U4 is grounded.

5. The input detection current limiting shutdown control circuit according to claim 4, characterized in that: The post-stage protection circuit includes a transistor T1, a MOS tube Q1 and an output interface J2; The 3rd interface of the D latch U3, the resistor R17, the B electrode of the transistor T1, the E electrode of the transistor T1, the S electrode of the MOS transistor Q1, the G electrode of the MOS transistor Q1 and the C electrode of the transistor T1 are sequentially connected in series, the D electrode of the MOS transistor Q1 is connected to the 1st interface of the output interface J2, the 2nd interface of the output interface J2 and the 3rd interface of the output interface J2, and the 4th interface of the output interface J2 and the 5th interface of the output interface J2 are both grounded; The S pole of the MOS tube Q1 is electrically connected between the resistor RJ1 and the resistor R3; A capacitor C4 is connected in parallel to the S pole of the MOS tube Q1 and the D pole of the MOS tube Q1, a resistor R20 and a voltage-stabilizing diode Zener are connected in parallel to the C pole of the transistor T1 and the E pole of the transistor T1, the resistor R20 and the voltage-stabilizing diode Zener are connected in parallel, an external resistor R19 is connected between the C pole of the transistor T1 and the G pole of the MOS tube Q1, and the resistor R19 is grounded; A resistor R18 and a capacitor C5 are externally connected between the resistor R17 and the B pole of the transistor T1; the resistor R18 is externally connected to the 5V terminal, and the capacitor C5 is grounded; a VOUT_12V terminal is externally connected between the D pole of the MOS tube Q1 and the 1 interface of the output interface J2.

6. The input detection current limiting shutdown control circuit according to claim 5, characterized in that: The alarm circuit includes a resistor R14, a transistor T2, and a buzzer BZ1; The resistor 14, the B pole of the transistor T2, the C pole of the transistor T2, the buzzer BZ1 and the resistor R16 are connected in series in sequence, the resistor 14 is connected between the 2 interface of the D latch U3 and the 1 interface of the NOT gate U4, and the resistor R16 is externally connected to the 5V terminal; the buzzer interface J5 and the diode DS3 are connected in parallel to the outside of the buzzer BZ1; the resistor R15 is connected in parallel to the outside of the B pole of the transistor T2 and the E pole of the transistor T2, and the E pole of the transistor T2 is grounded.

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