Communication device and cascade system
By designing a communication device, using the slave and master protocol conversion module and the LDVS communication protocol, the problem of high-speed input and output pins in FPGAs is solved, and the extended connection and communication between FPGAs is realized, and communication efficiency and reliability are improved.
Patent Information
- Application Number
- CN202420529549.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-03-19
- Publication Date
- 2025-04-25
- Estimated Expiration
- 2034-03-19
AI Technical Summary
In FPGAs, high-speed input and output pins are occupied, making it difficult to achieve extended connections between FPGAs.
A communication device is designed, including a slave protocol conversion module and a first communication module, as well as a master protocol conversion module and a second communication module, and communicates through an LDVS communication protocol to realize extended connection and communication between programmable logic chips.
Extended connection and communication between programmable logic chips can be achieved without the use of high-speed input and output pins, improving communication efficiency and reliability between FPGAs.
Smart Images
Figure CN222802893U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of communication, in particular to a communication device and a cascade system. Background Art
[0002] With the development of communication technology, most of the FPGA (Field Programmable Gate Array) series of Xillinx (a supplier of complete programmable logic solutions) use the AXI (Advanced eXtensibleInterface) data communication protocol to realize the communication between the processor system module and the programmable editing module, as well as the communication between the soft core and the peripheral control module. This communication method can realize the real-time task management of the soft core processor.
[0003] However, in a system, multiple FPGAs need to be used, and multiple FPGAs need to be able to communicate with each other. For the extended connection between FPGAs, Xillinx officially provides the Xillinx series FPGA communication connection IP core (Aurora). The use of this IP core can realize the communication connection between the Xillinx series FPGAs. However, this IP core needs to occupy a large amount of FPGA internal resources, and the communication connection is realized by using the IP core. However, the IP cores can only be connected using high-speed input and output pins. When the high-speed input and output pins in the FPGA are occupied, it is difficult to realize the extended connection between FPGAs. Utility Model Content
[0004] Based on this, it is necessary to provide a communication device and a cascade system to address the problem that it is difficult to extend connections between FPGAs when the high-speed input and output pins in the FPGA are occupied.
[0005] A communication device, comprising: a slave-end protocol conversion module and a first communication module connected to a master control programmable logic chip, and a master-end protocol conversion module and a second communication module connected to a controlled programmable logic chip;
[0006] The slave-side protocol conversion module is connected to the first communication module, and is used to convert the received communication information based on the slave-side AXI protocol and send it to the first communication module;
[0007] The first communication module is connected to the second communication module, and is used to obtain target communication information according to the converted communication information and send it to the second communication module;
[0008] The second communication module is connected to the master-end protocol conversion module, and is used to parse the target communication information to obtain the converted communication information and send it to the master-end protocol conversion module; the master-end protocol conversion module is used to complete its corresponding read and write operations according to the converted communication information.
[0009] In one of the embodiments, the first communication module includes a first sending module, and the second communication module includes: a second receiving module; the first sending module and the second receiving module are connected, and the first sending module and the second receiving module communicate based on the LDVS communication protocol.
[0010] In one of the embodiments, the first communication module includes: a first receiving module, the second communication module includes: a second sending module, the second sending module is connected to the first receiving module, and the second sending module and the first receiving module communicate based on the LDVS communication protocol.
[0011] In one embodiment, the communication device also includes: a first communication port, which is connected to the slave-end protocol conversion module and the master programmable logic chip respectively, and the first communication port is used to receive and cache the communication information output by the master programmable logic chip, so as to send the communication information to the slave-end protocol conversion module when the master programmable logic chip sends a transmission start instruction.
[0012] In one embodiment, the communication device also includes: a second communication port, which is respectively connected to the master-end protocol conversion module and the controlled programmable logic chip, and the second communication port is used to send the converted communication information to the controlled programmable logic chip to instruct the controlled programmable logic chip to complete its corresponding read and write operations.
[0013] In one of the embodiments, the communication device further includes: a third communication module, the third communication module is connected to the master-end protocol conversion module, and the third communication module is also connected to the slave controlled programmable logic chip.
[0014] In one of the embodiments, the first communication module is also connected to at least one slave controlled programmable logic chip, and is used to obtain target communication information according to the converted communication information and send it to the at least one slave controlled programmable logic chip.
[0015] In one of the embodiments, the first communication module further includes: a cache module, which is connected to the slave-end protocol conversion module and is used to cache the communication information.
[0016] In one of the embodiments, the communication device further includes: a reset module, which is connected to the cache module and is used to clear the cached communication information.
[0017] In the second aspect, the utility model also provides a cascade system, which includes: a master programmable logic chip, at least one controlled programmable logic chip and a communication device described in any of the above embodiments; the communication device includes: a slave-end protocol conversion module and a first communication module connected to the master programmable logic chip, and a master-end protocol conversion module and a second communication module connected to each controlled programmable logic chip.
[0018] In the above communication device and cascade system, the communication information is converted by the slave-side protocol conversion and transmitted to the first communication module. The first communication module receives the converted communication information, obtains the target communication information according to the converted communication information and sends it to the second communication module. Finally, the second communication module parses the converted target communication information and sends it to the master-side protocol conversion, and the master-side protocol conversion module completes its corresponding read and write operations according to the converted communication information. The whole process can realize the extended connection between programmable logic chips without using high-speed input and output pins, and can realize communication between programmable logic chips. BRIEF DESCRIPTION OF THE DRAWINGS
[0019] Figure 1 is a schematic structural diagram of a communication device in one embodiment;
[0020] Figure 2 A schematic diagram of the structure of a first communication module and a second communication module in an embodiment;
[0021] Figure 3 A schematic diagram of the structure of a first communication port and a second communication port in one embodiment;
[0022] Figure 4 A schematic diagram of a structure in which a third communication module is connected to a slave controlled programmable logic chip in one embodiment;
[0023] Figure 5 A schematic diagram of a structure in which a first communication module is connected to a slave controlled programmable logic chip in one embodiment;
[0024] Figure 6 A schematic diagram of the structure of a cache module and a reset module in one embodiment;
[0025] Figure 7 FIG. 4 is a schematic diagram of the structure of a cascade system in an embodiment.
[0026] The components in the accompanying drawings are marked as follows: 100, communication device; 122, slave-side protocol conversion module; 124, first communication module; 142, master-side protocol conversion module; 144, second communication module; 1241, first sending module; 1242, first receiving module; 1441, second sending module; 1442, second receiving module; 126, first communication port; 146, second communication port; 1243, cache module; 160, reset module. DETAILED DESCRIPTION
[0027] In order to make the above-mentioned purposes, features and advantages of the utility model more obvious and easy to understand, the specific implementation methods of the utility model are described in detail below in conjunction with the accompanying drawings. In the following description, many specific details are set forth to facilitate a full understanding of the utility model. However, the utility model can be implemented in many other ways different from those described herein, and those skilled in the art can make similar improvements without violating the connotation of the utility model, so the utility model is not limited by the specific embodiments disclosed below.
[0028] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of the present utility model, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.
[0029] See also Figure 1 , Figure 1 The schematic diagram of the structure of the communication device 100 in one embodiment of the utility model is shown. One embodiment of the utility model provides a communication device 100, including: a slave-end protocol conversion module 122 and a first communication module 124 connected to a master programmable logic chip, and a master-end protocol conversion module 142 and a second communication module 144 connected to a controlled programmable logic chip. It should be noted that the first communication module 124 and the slave-end protocol conversion module 122 can be arranged outside the master programmable logic chip, and the slave-end protocol conversion module 122 is connected to the master programmable logic chip, or can be arranged inside the master programmable logic chip, and the slave-end protocol conversion module 122 is connected to the master programmable logic chip. The second communication module 144 and the master-end protocol conversion module 142 can be arranged outside the controlled programmable logic chip, and the master-end protocol conversion module 142 is connected to the controlled programmable logic chip, or can be arranged inside the controlled programmable logic chip, and the master-end protocol conversion module 142 is connected to the controlled programmable logic chip.
[0030] The slave-side protocol conversion module 122 is connected to the first communication module 124 , and is configured to convert the received communication information based on the slave-side AXI protocol and send the converted information to the first communication module 124 .
[0031] Among them, the first communication module 124 can be an LVDS (Low Voltage Differential Signaling) communication module. The first communication module can use low voltage differential signal communication technology and use low voltage differential signal communication protocol to perform digital signal transmission and high-speed data communication. The low voltage differential signal communication protocol can be an LVDS protocol, which is a low voltage differential signal transmission protocol for high-speed data transmission. By dividing the data signal into positive and negative paths for transmission, the use of differential transmission can improve the anti-interference ability and reduce noise and distortion during signal transmission. The communication information may include: communication address information and data information that needs to be transmitted in the communication, etc. In some embodiments of the utility model, the communication address information may be the address information of other programmable logic chips (for example, the controlled programmable logic chip). The slave-end protocol conversion module 122 and the master-end protocol conversion module 142 can generally be modules that convert communication parameter information into a format that conforms to the communication protocol of the programmable logic chip. The communication protocol formats that conform to programmable logic chips may include: AXI (Advanced Xtensible Interface) protocol, APB (Advanced Peripheral Bus) protocol, SPI (Serial Peripheral Interface) protocol, I2C (Inter-Integrated Circuit) protocol, UART (Universal Asynchronous Receiver / Transmitter) protocol, etc. Depending on different communication scenarios or communication requirements, the protocols that can be used by programmable logic chips are also different.
[0032] Specifically, the slave-end protocol conversion module 122 is connected to the master programmable logic chip. The master programmable logic chip can send communication parameter information (communication information) to the slave-end protocol conversion module 122. Generally, since the communication information format sent by the master programmable logic chip is a format readable by the master programmable logic chip, in order to ensure the data transmission speed and to ensure the reliable transmission of data. The slave-end protocol conversion module 122 can convert the communication information into the first communication parameter information that complies with the LVDS protocol.
[0033] In some exemplary embodiments, the utility model further defines a communication format of the first communication parameter information that complies with the LVDS protocol, and the communication format may include: a synchronization word, a control word, and data. The synchronization word, the control word, and the data may be 32 bits. The synchronization word may be used for synchronization between the sender and the receiver, indicating the start of data transmission during a communication process. The control word is used to control the communication logic, indicating whether the communication is read or write. The data may include address and data information, indicating that the internal address and data of the FPGA that needs to be written (read) are transmitted between the sender and the receiver.
[0034] The first communication module 124 is connected to the second communication module 144, and is used to obtain target communication information according to the converted communication information and send it to the second communication module 144;
[0035] The second communication module 144 may also be an LVDS (Low Voltage Differential Signaling) communication module.
[0036] Specifically, after receiving the converted communication information, the first communication module 124 can obtain target communication information according to the converted communication information and send the target communication information to the second communication module 144 .
[0037] The second communication module 144 is connected to the master-end protocol conversion module 142, and is used to parse the target communication information to obtain the converted communication information and send it to the master-end protocol conversion module 142; the master-end protocol conversion module 142 is used to complete its corresponding read and write operations according to the converted communication information.
[0038] Specifically, when the communication mode between the master programmable logic chip and the controlled programmable logic chip is a read operation, the communication information is address information, and the master-end protocol conversion module 142 is used to complete the read operation of the corresponding target data according to the address information.
[0039] In this embodiment, the communication information is converted by using the slave protocol conversion and transmitted to the first communication module 124. The first communication module 124 receives the converted communication information, obtains the target communication information according to the converted communication information and sends it to the second communication module 144. Finally, the second communication module 144 parses the converted target communication information and sends it to the master protocol conversion module 142, and the master protocol conversion module 142 completes its corresponding read and write operations according to the converted communication information. The whole process does not need to use high-speed input and output pins to realize the extended connection between programmable logic chips and realize communication between programmable logic chips. In addition, since the first communication module 124 and the second communication module 144 are LVDS modules and use the LVDS protocol, reliability can be guaranteed during the communication process, and the communication rate is relatively fast, which can reach 200Mbps.
[0040] Combination Figure 2 As shown, Figure 2 A connection diagram of a first communication module 124 and a second communication module 144 in an embodiment of the utility model is shown. The first communication module 124 includes a first sending module 1241, and the second communication module 144 includes: a second receiving module 1442; the first sending module 1241 and the second receiving module 1442 are connected, and the first sending module 1241 and the second receiving module 1442 communicate based on the LDVS communication protocol. The first communication module includes: a first receiving module, and the second communication module includes: a second sending module 1441, the second sending module 1441 is connected to the first receiving module, and the second sending module 1441 and the first receiving module communicate based on the LDVS communication protocol.
[0041] The second sending module 1441 is used to send the target data it receives to the first receiving module 1242, so as to transmit the target data to the slave protocol conversion module 122. When the communication mode between the master programmable logic chip and the controlled programmable logic chip is a read operation, the slave protocol conversion module 122 is used to determine that the current read operation is completed after receiving the sending completion feedback information sent by the first sending module 1241 and receiving the receiving completion feedback information sent by the first receiving module 1242. When the communication mode between the master programmable logic chip and the controlled programmable logic chip is a write operation, the communication information includes address information and data information, and the master protocol conversion module 142 is used to complete the write operation of the data information according to the address information. When the communication mode between the master programmable logic chip and the controlled programmable logic chip is a write operation, the slave protocol conversion module 122 is used to determine that the current write operation is completed after receiving the feedback information sent by the first sending module 1241. The slave-side protocol conversion module 122 is used to determine whether there is a next read or write operation when the current read or write operation is completed, and to determine that the communication process is finished when there is no next read or write operation.
[0042] In this embodiment, the first sending module 1241 is connected to the second receiving module 1442, and the second sending module 1441 is connected to the first receiving module 1242, that is, the first communication module 124 sends data to the second communication module 144, and the first sending module 1241 is used to send data to the second receiving module 1442. When the first communication module 124 receives data sent by the second communication module 144, the first receiving module 1242 is used to receive the data sent by the second sending module 1441. In the process of transmitting data between the first communication module 124 and the second communication module 144, data sending and data receiving are independent channels. It can be ensured that data reception and data sending will not be interfered.
[0043] In one embodiment, the first sending module 1241 is connected to the second receiving module 1442 via an LVDS interface; the second sending module 1441 is connected to the first receiving module 1242 via an LVDS interface.
[0044] Specifically, since the first sending module 1241 and the second receiving module 1442 and the second sending module 1441 and the first receiving module 1242 both use the LVDS protocol for communication, the first sending module 1241 and the second receiving module 1442 are connected via an LVDS interface. The second sending module 1441 and the first receiving module 1242 are connected via an LVDS interface, thereby supporting the LVDS protocol.
[0045] Figure 3 Schematic diagram of the structure of the first communication port 126 and the second communication port 146 in one embodiment of the present invention.
[0046] In some embodiments, the communication device also includes: a first communication port 126, which is respectively connected to the slave-end protocol conversion module 122 and the master programmable logic chip, and the first communication port 126 is used to receive and cache the communication information output by the master programmable logic chip, so as to send the communication information to the slave-end protocol conversion module 122 when the master programmable logic chip sends a transmission start instruction.
[0047] The communication device also includes: a second communication port 146, which is connected to the master-end protocol conversion module 142 and the controlled programmable logic chip respectively, and the second communication port 146 is used to send the converted communication information to the controlled programmable logic chip to instruct the controlled programmable logic chip to complete its corresponding read and write operations.
[0048] According to the communication protocol format that can be read and written by the programmable logic chip, the type of the first communication port 126 and the type of the second communication port 146 are also different. For example, if the AXI protocol is used, the corresponding type of the first communication port 126 and the type of the second communication port 146 can be a port. If the UART protocol is used, the corresponding type of the first communication port 126 and the type of the second communication port 146 can be a UART port. In some embodiments of the present disclosure, there is no absolute restriction on the type of the first communication port 126 and the type of the second communication port 146.
[0049] Specifically, the slave protocol conversion module 122 is connected to the first communication port 126. The master programmable logic chip can also be connected to the first communication port 126. The master programmable logic chip sends the communication information to the slave protocol conversion module 122 through the first communication port 126. Furthermore, when the master programmable logic chip sends the communication information and the start instruction to the first communication port 126. The first communication port 126 can transmit the received communication information to the slave protocol conversion module 122.
[0050] The master-side protocol conversion module 142 is connected to the second communication port 146. The controlled programmable logic chip can also be connected to the second communication port 146. In this way, the master-side protocol conversion module 142 can send the converted communication information to the controlled programmable logic chip via the second communication port 146.
[0051] In this embodiment, by using the first communication port 126 to connect with the master programmable logic chip and using the second communication port 146 to connect with the controlled programmable logic chip, it is possible to support different communication protocol formats of the master programmable logic chip and adapt to communication scenarios with a variety of different communication protocol formats.
[0052] In one embodiment, Figure 4 As shown, the communication device also includes: a third communication module. The third communication module is connected to the master-end protocol conversion module 142. The third communication module also needs to be connected from the controlled programmable logic chip. It should be noted that the third communication module here can refer to the above description of the first communication module 124, which will not be repeated here. It should be noted that how to communicate and transmit data here can refer to the processing process of the first communication module 124 and the second communication module 144 in the above embodiment, which will not be repeated here. The controlled programmable logic chip can be one or more. When there are multiple modules, the modules connected to the controlled programmable logic chip and the modules connected to the controlled programmable logic chip are basically the same. In this way, multiple data can be transmitted to different programmable logic chips at the same time through the master programmable logic chip without the need for a high-speed input and output interface, and data communication between programmable logic chips can also be realized.
[0053] In one embodiment, Figure 5 As shown, the first communication module 124 is also connected to at least one slave controlled programmable logic chip, and is used to obtain target communication information according to the converted communication information and send it to the at least one slave controlled programmable logic chip. It should be noted that, regarding the way in which the first communication module 124 is connected to at least one slave controlled programmable logic chip, please refer to the above-mentioned first communication module 124 and second communication module 144, which will not be repeated here. In addition, in this embodiment, the modules in the communication device connected to the slave controlled programmable logic chip and the modules in the communication device connected to the controlled programmable logic chip are basically the same.
[0054] In one embodiment, Figure 6 As shown, the first communication module 124 further includes: a cache module 1243, and the cache module 1243 is connected to the slave-end protocol conversion module 122 and is used to cache the communication information.
[0055] The device further includes: a reset module 160, which is connected to the cache module 1243 and is used to clear the cached communication information.
[0056] Specifically, the first communication module 124 may also include a cache module 1243. The cache module 1243 may be connected to the slave-end protocol conversion module 122. When the slave-end protocol conversion module 122 converts the communication information. In order to ensure that data is not lost, the cache module 1243128 may cache the communication information after and before the conversion, thereby ensuring the reliability of this data communication process. In addition, the communication device 100 may also include a reset module 160, and the reset module 160 is connected to the cache module 1243. Since the cache module 1243 can cache the communication information after and before the conversion, if the last data communication is completed, and the cache module 1243 still caches the communication information after and before the conversion, additional storage space will be wasted. Therefore, at the beginning of this communication, the reset module 160 may first clear the communication information after and before the conversion cached by the cache module 1243.
[0057] In one embodiment, a cascade system is provided, such as Figure 7 As shown, the cascade system includes: a master programmable logic chip, at least one controlled programmable logic chip and the communication device described in any one of the above embodiments; the communication device includes: a slave-end protocol conversion module and a first communication module connected to the master programmable logic chip, and a master-end protocol conversion module and a second communication module connected to each controlled programmable logic chip; the multiple second communication modules are connected in series in sequence, and the first communication module is connected to any of the second communication modules.
[0058] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0059] The above-mentioned embodiments only express several implementation methods of the utility model, and the description is relatively specific and detailed, but it cannot be understood as limiting the scope of the utility model patent. It should be pointed out that for ordinary technicians in this field, several modifications and improvements can be made without departing from the concept of the utility model, which all belong to the protection scope of the utility model. Therefore, the protection scope of the utility model patent shall be based on the attached claims.
Claims
1. A communication device, characterized in that: include: A slave-side protocol conversion module and a first communication module connected to the master programmable logic chip, and a master-side protocol conversion module and a second communication module connected to the controlled programmable logic chip; The slave-side protocol conversion module is connected to the first communication module, and is used to convert the received communication information based on the slave-side AXI protocol and send it to the first communication module; The first communication module is connected to the second communication module, and is used to obtain target communication information according to the converted communication information and send it to the second communication module; The second communication module is connected to the master-end protocol conversion module, and is used to parse the target communication information to obtain the converted communication information and send it to the master-end protocol conversion module; the master-end protocol conversion module is used to complete its corresponding read and write operations according to the converted communication information.
2. The communication device according to claim 1, characterized in that The first communication module includes a first sending module, and the second communication module includes: a second receiving module; the first sending module and the second receiving module are connected, and the first sending module and the second receiving module communicate based on the LDVS communication protocol.
3. The communication device according to claim 1, characterized in that The first communication module includes: a first receiving module, and the second communication module includes: a second sending module, the second sending module is connected to the first receiving module, and the second sending module and the first receiving module communicate based on the LDVS communication protocol.
4. The communication device according to claim 1, characterized in that: The communication device also includes: a first communication port, which is connected to the slave-end protocol conversion module and the master programmable logic chip respectively, and the first communication port is used to receive and cache the communication information output by the master programmable logic chip, so as to send the communication information to the slave-end protocol conversion module when the master programmable logic chip sends a transmission start instruction.
5. The communication device according to claim 1, characterized in that: The communication device also includes: a second communication port, which is connected to the master-end protocol conversion module and the controlled programmable logic chip respectively, and the second communication port is used to send the converted communication information to the controlled programmable logic chip to instruct the controlled programmable logic chip to complete its corresponding read and write operations.
6. The communication device according to claim 1, characterized in that: The communication device further includes: a third communication module, the third communication module is connected to the master-end protocol conversion module, and the third communication module is also connected to the slave controlled programmable logic chip.
7. The communication device according to claim 1, characterized in that: The first communication module is also connected to at least one slave controlled programmable logic chip, and is used to obtain target communication information according to the converted communication information and send it to the at least one slave controlled programmable logic chip.
8. The communication device according to claim 1, characterized in that: The first communication module further includes: a cache module, which is connected to the slave-end protocol conversion module and is used to cache the communication information.
9. The communication device according to claim 8, characterized in that: The communication device further includes: a reset module, which is connected to the cache module and is used to clear the cached communication information.
10. A cascade system, characterized in that: The cascade system includes: a master programmable logic chip, at least one controlled programmable logic chip and the communication device described in any one of claims 1 to 9; the communication device includes: a slave-end protocol conversion module and a first communication module connected to the master programmable logic chip, and a master-end protocol conversion module and a second communication module connected to each controlled programmable logic chip.