Control circuit and control equipment

Abstract

The embodiment of the utility model discloses a control circuit and control equipment, which are used for solving the problem of single implementation mode of the control circuit in the related technology. The control circuit comprises a main control module, a switch module, a latch control module, a driving module and a relay, wherein the main control module comprises an enable signal output end and a latch signal output end; the latch signal output end is connected with the latch control module; the main control module outputs a control signal through the latch signal output end so as to control the on-off of the latch control module; the enable signal output end is connected to the relay through the switch module, the latch control module and the driving module in sequence; and under the condition that the latch control module is interrupted, the signal between the driving module and the main control module is interrupted, and the driving module drives the relay to maintain the working state of the relay. According to the technical scheme, the stability of a relay loop can be ensured, dependence on a fixed chip is avoided, and various control circuits can be realized.

Description

Technical Field

[0001] The utility model relates to the technical field of electronic circuits, and in particular to a control circuit and a control device. Background Art

[0002] Smart control products on the market generally have OTA upgrade (Over The Air upgrade, a technology for upgrading device firmware via the Internet) activities. During this process, the MCU (Microcontroller Unit) in the product will restart. In addition, if the product is disturbed by other external factors such as static electricity, the MCU in the product will also restart, causing the relay circuit controlled by the MCU to be disconnected, thereby affecting the load connected to the relay.

[0003] In order to solve this problem, the related technology adds a latch integrated chip to the product, which latches the control signal of the relay to maintain the stability of the relay circuit. However, this solution needs to rely on a fixed chip, and the implementation method is relatively simple. If there is no latch integrated chip, the effect cannot be achieved. Therefore, it is particularly necessary to design a better control circuit. Utility Model Content

[0004] The purpose of the embodiments of the present application is to provide a control circuit and a control device to solve the problem of a single control circuit implementation method in the related art.

[0005] To solve the above technical problems, the embodiments of the present application are implemented as follows:

[0006] On the one hand, an embodiment of the present application provides a control circuit, including a main control module, a switch module, a latch control module, a drive module and a relay; wherein,

[0007] The main control module includes an enable signal output terminal and a latch signal output terminal;

[0008] The latch signal output terminal is connected to the latch control module; the main control module outputs a control signal through the latch signal output terminal to control the on and off of the latch control module;

[0009] The enable signal output end is connected to the relay through the switch module, the latch control module and the drive module in sequence; when the latch control module is interrupted, the signal between the drive module and the main control module is interrupted, and the drive module drives the relay to maintain its own working state.

[0010] On the other hand, an embodiment of the present application provides a control device, including the control circuit as described above.

[0011] The control circuit provided by the embodiment of the present application is adopted, and the working state of the relay is controlled by the main control module, the switch module, the latch control module and the driver module. Wherein, the latch signal output terminal of the main control module is connected to the latch control module, so that the main control module can output a control signal through the latch signal output terminal to control the on-off of the latch control module. The enable signal output terminal of the main control module is connected to the relay through the switch module, the latch control module and the driver module in turn, so that when the latch control module is interrupted, the signal between the driver module and the main control module is interrupted, and the driver module drives the relay to maintain its own working state. It can be seen that in the technical scheme, by arranging the latch control module and the driver module between the relay and the main control module, the control circuit can be interrupted by controlling the latch control module, so that the working state of the relay is no longer controlled by the main control module, and the working state of the relay is maintained under the drive of the driver module, effectively avoiding the abnormality (such as OTA upgrade, interference from the outside, etc.) that may occur in the main control module. The influence on the working state of the relay is ensured, and the stability of the relay circuit is ensured, thereby avoiding the influence on the load connected to the relay, and improving the stability of the product containing the control circuit. Moreover, compared with the solution of using chips to implement control circuits in related technologies, this technical solution uses several modules to form a control circuit, does not rely on fixed chips, reduces development costs and difficulty, and can realize a variety of control circuits by designing modules. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0013] Figure 1 is a schematic block diagram of a control circuit according to an embodiment of the present application;

[0014] Figure 2 is a schematic block diagram of a control circuit according to another embodiment of the present application;

[0015] Figure 3 is a schematic block diagram of a control circuit according to another embodiment of the present application;

[0016] Figure 4 is a schematic block diagram of a control circuit according to another embodiment of the present application;

[0017] Figure 5 is a schematic block diagram of a control circuit according to another embodiment of the present application;

[0018] Figure 6 is a schematic block diagram of a control circuit according to another embodiment of the present application;

[0019] Figure 7 is a schematic block diagram of a control circuit according to another embodiment of the present application;

[0020] Figure 8 is a schematic block diagram of a control circuit according to another embodiment of the present application;

[0021] Fig. 9 is a schematic block diagram of a control circuit according to another embodiment of the present application;

[0022] Fig.10 is a schematic block diagram of a control circuit according to another embodiment of the present application;

[0023] Fig.11 is a schematic block diagram of a control circuit according to another embodiment of the present application;

[0024] Fig.12 is a structural schematic diagram of a control circuit according to an embodiment of the present application;

[0025] Fig.13 It is a schematic block diagram of a control device according to an embodiment of the present application. DETAILED DESCRIPTION

[0026] The embodiments of the present application provide a control circuit and a control device to solve the problem of a single control circuit implementation method in the related art.

[0027] In order to enable those skilled in the art to better understand the technical solutions in this application, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the drawings in the embodiments of this application. Obviously, the described embodiments are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of this application.

[0028] Figure 1 is a schematic block diagram of a control circuit according to an embodiment of the present application, such as Figure 1 As shown, the control circuit includes a main control module 10, a switch module 20, a latch control module 30, a drive module 40 and a relay 50. The main control module 10 includes an enable signal output terminal 110 and a latch signal output terminal 120. The latch signal output terminal 120 is connected to the latch control module 30, and the enable signal output terminal 110 is connected to the relay 50 through the switch module 20, the latch control module 30 and the drive module 40 in sequence.

[0029] In this embodiment, the main control module outputs a control signal through the latch signal output terminal to control the on and off of the latch control module. When the latch control module is interrupted, the signal between the drive module and the main control module is interrupted, and the drive module drives the relay to maintain its own working state. When the latch control module is connected, the main control module outputs an enable signal through the enable signal output terminal to control the drive module, and the drive module drives the relay to be closed or disconnected. Among them, the working state of the relay includes an on state or an off state.

[0030] Optionally, the main control module is an MCU in an intelligent control product. The enable signal output terminal and the latch signal output terminal are I / O (Input / Output) ports of the MCU. The enable signal output terminal is used to output an enable signal, and the latch signal output terminal is used to output a control signal. The enable signal and the control signal can be high-level signals or low-level signals output by the I / O port of the MCU. It should be understood that the main control module also includes other ports, which are not limited in the embodiments of the present application.

[0031] The control circuit provided by the embodiment of the present application is adopted, and the working state of the relay is controlled by the main control module, the switch module, the latch control module and the driver module. Wherein, the latch signal output terminal of the main control module is connected to the latch control module, so that the main control module can output a control signal through the latch signal output terminal to control the on-off of the latch control module. The enable signal output terminal of the main control module is connected to the relay through the switch module, the latch control module and the driver module in turn, so that when the latch control module is interrupted, the signal between the driver module and the main control module is interrupted, and the driver module drives the relay to maintain its own working state. It can be seen that in the technical scheme, by arranging the latch control module and the driver module between the relay and the main control module, the control circuit can be interrupted by controlling the latch control module, so that the working state of the relay is no longer controlled by the main control module, and the working state of the relay is maintained under the drive of the driver module, effectively avoiding the abnormality (such as OTA upgrade, interference from the outside, etc.) that may occur in the main control module. The influence on the working state of the relay is ensured, and the stability of the relay circuit is ensured, thereby avoiding the influence on the load connected to the relay, and improving the stability of the product containing the control circuit. Moreover, compared with the solution of using chips to implement control circuits in related technologies, this technical solution uses several modules to form a control circuit, does not rely on fixed chips, reduces development costs and difficulty, and can realize a variety of control circuits by designing modules.

[0032] In one embodiment, Figure 2As shown, the latch control module 30 includes a first transistor Q1, a first transistor Q2 and a second transistor Q3. The latch signal output terminal 120 is connected to the first transistor Q1. The first transistor Q1 is connected to the first transistor Q2 and the second transistor Q3 respectively. The first transistor Q2 is connected to the switch module 20 and the second transistor Q3 respectively, and the second transistor Q3 is connected to the driving module 40. It should be noted that Figure 2 is Figure 1 The schematic block diagram obtained by refining the latch control module 30 based on , therefore, Figure 2 Zhongyu Figure 1 For the connection relationship between the parts with the same number, please refer to Figure 1 , I will not go into details here.

[0033] In this embodiment, the latch signal output terminal outputs a control signal that can control the on-off of the first transistor Q1, thereby controlling the on-off of the first transistor Q2 and the second transistor Q3, so as to achieve on-off control of the latch control module.

[0034] In one embodiment, Figure 3 As shown, the latch signal output terminal 120 is connected to the base of the first transistor Q1, the collector of the first transistor Q1 is connected to the gate of the first transistor Q2 and the gate of the second transistor Q3 respectively, and the emitter of the first transistor Q1 is grounded. The source of the first transistor Q2 is connected to the first power supply voltage VDD and is connected to the switch module 20, and the drain of the first transistor Q2 is connected to the drain of the second transistor Q3. The source of the second transistor Q3 is connected to the second power supply voltage VDD and is connected to the driving module 40, and the gate of the second transistor Q3 is connected to the third power supply voltage VDD and is connected to the gate of the first transistor Q2.

[0035] To make the connection relationship between components clearer, Figure 3 The main control module 10 is no longer shown in the control circuit shown. The connection line is marked with Latch at the dangling position to indicate that the connection line is connected to the latch signal output terminal 120 of the main control module 10, and the connection line is marked with EN_Relay at the dangling position to indicate that the connection line is connected to the enable signal output terminal 110 of the main control module 10. In addition, due to Figure 3 is Figure 2 The schematic block diagram obtained by refining the connection relationship based on , therefore, Figure 3 Zhongyu Figure 2 For the connection relationship between the parts with the same number, please refer to Figure 2 , I will not go into details here.

[0036] In this embodiment, the first power supply voltage, the second power supply voltage and the third power supply voltage are named to distinguish the power supply voltages connected to different pins. It should be understood that the first power supply voltage, the second power supply voltage and the third power supply voltage can be the same or different power supply voltages, and the embodiment of the present application is not limited to this.

[0037] Optionally, to protect components and ensure their service life, e.g. Figure 4 As shown, a first resistor R1 can be connected between the collector of the first transistor Q1 and the gate of the first transistor Q2, a second resistor R2 can be connected between the source of the first transistor Q2 and the first power supply voltage VDD, a third resistor R3 can be connected between the gate of the second transistor Q3 and the third power supply voltage VDD, and a fourth resistor R4 can be connected between the source of the second transistor Q3 and the second power supply voltage VDD.

[0038] In the present embodiment, in order to achieve the purpose of interrupting the signal between the main control module and the driving module, a latch control module is provided in the control circuit, and the latch control module can be controlled to be interrupted or connected through the control signal output by the main control module. However, due to the presence of parasitic diodes in transistors, if only one transistor is provided in the latch control module, then, even if the transistor is not conducting, it is impossible to prevent the signal from being transmitted through the parasitic diode, and the purpose of the present application cannot be achieved. Therefore, the embodiment of the present application provides two transistors with drains connected in the latch control module. In this way, when the two transistors are not conducting, since the directions of the two parasitic diodes are opposite, the power supply voltage cannot pass, and the signal between the main control module and the driving module can be effectively interrupted.

[0039] In one embodiment, Figure 5 As shown, the driving module 40 includes a driving circuit 410 and a level holding circuit 420. The driving circuit 410 is connected to the latch control module 30, the level holding circuit 420 and the relay 50 respectively. It should be noted that, Figure 5 is Figure 4 The schematic block diagram obtained by refining the driving module 40 based on , therefore, Figure 5 Zhongyu Figure 4 For the connection relationship between the parts with the same number, please refer to Figure 4 , I will not go into details here.

[0040] In this embodiment, by setting a driving circuit and a level holding circuit in the driving module, the driving module can be prompted to maintain the received enable signal sent by the main control module, so that when the latch control module is interrupted, the relay can still maintain its own working state unchanged.

[0041] In one embodiment, Figure 6As shown, the driving circuit 410 includes a third transistor Q4, and the level holding circuit 420 includes a second triode Q5 and a voltage dividing unit 4210. The third transistor Q4 is connected to the second transistor Q3, the second triode Q5, the voltage dividing unit 4210 and the relay 50 respectively, and the voltage dividing unit 4210 is connected to the second triode Q5. It should be noted that Figure 6 is Figure 5 The schematic block diagram obtained by refining the driving circuit 410 and the level holding circuit 420 on the basis of FIG. Figure 6 Zhongyu Figure 5 For the connection relationship between the parts with the same number, please refer to Figure 5 , I will not go into details here.

[0042] In this embodiment, the third transistor can be turned on or off under the action of an enable signal. Afterwards, through a closed loop formed by the second transistor, the voltage divider unit and the relay, the working state of the third transistor (including the conducting state or the non-conducting state) can be maintained, thereby maintaining the working state of the relay.

[0043] In one embodiment, Figure 7 As shown, the source of the third transistor Q4 is connected to the second power supply voltage VDD and is connected to the source of the second transistor Q3, the gate of the third transistor Q4 is respectively connected to the source of the second transistor Q3 and the collector of the second triode Q5, and the drain of the third transistor Q4 is respectively connected to the voltage dividing unit 4210 and the relay 50. The voltage dividing unit 4210 is respectively connected to the base and emitter of the second triode Q5, and the emitter of the second triode Q5 is grounded.

[0044] It should be noted that in order to make the connection relationship between the components clearer, Figure 7 The driving circuit 410 and the level holding circuit 420 are no longer marked in the control circuit shown. Figure 7 is Figure 6 The schematic block diagram obtained by refining the connection relationship based on , therefore, Figure 7 Zhongyu Figure 6 For the connection relationship between the parts with the same number, please refer to Figure 6 , I will not go into details here.

[0045] In this embodiment, the source of the third transistor Q4 is connected between the second power supply voltage VDD and the fourth resistor R4 , that is, the source of the third transistor Q4 is connected to the source of the second transistor Q3 through the fourth resistor R4 .

[0046] The voltage division unit may adopt any resistor voltage division circuit structure. For example, Figure 8 As shown, the voltage dividing unit 4210 includes a fifth resistor R5, a sixth resistor R6 and a first capacitor C1. Figure 8 As shown, the fifth resistor R5 is respectively connected to the drain of the third transistor Q4, the base of the second triode Q5, the sixth resistor R6 and the first capacitor C1, and the sixth resistor R6 and the first capacitor C1 are respectively connected to the emitter of the second triode Q5. It should be noted that in order to make the connection relationship of each component clearer, Figure 8 The voltage divider unit 4210 is no longer marked in the control circuit shown.

[0047] Optionally, to protect components and ensure their service life, e.g. Figure 8 As shown, a seventh resistor R7 may be connected between the gate of the third transistor Q4 and the collector of the second transistor Q5.

[0048] Optionally, the first transistor, the second transistor and the third transistor are PMOS (Positive Channel Metal Oxide Semiconductor) transistors.

[0049] In one embodiment, Fig. 9 As shown, the switch module 20 includes a third transistor Q6. The base of the third transistor Q6 is connected to the enable signal output terminal 110, the collector of the third transistor Q6 is connected to the first power supply voltage VDD and is connected to the source of the first transistor Q2, and the emitter of the third transistor Q6 is grounded. In this embodiment, Figure 8 After refining the switch module 20, we can get Fig. 9 Therefore, Fig. 9 Zhongyu Figure 8 For the connection relationship between the parts with the same number, please refer to Figure 8 , I will not go into details here.

[0050] The collector of the third transistor Q6 is connected to the first power supply voltage VDD through the second resistor R2, and the source of the first transistor Q2 is connected between the second resistor R2 and the collector of the third transistor Q6. Optionally, to protect components and ensure the service life of components, Fig. 9 As shown, an eighth resistor R8 may be connected between the enable signal output terminal 110 and the base of the third transistor Q6.

[0051] In one embodiment, Fig.10 As shown, the control circuit includes an input protection module 60, and the input protection module 60 is connected between the latch signal output terminal 120 and the latch control module 30. In this embodiment, Fig. 9 After refining the control circuit based on Fig.10 Therefore, Fig.10 Zhongyu Fig. 9 For the connection relationship between the parts with the same number, please refer to Fig. 9 , I will not go into details here.

[0052] Optionally, the input protection module may adopt any circuit structure that can play an input protection role. For example, Fig.11 As shown, the input protection module 60 includes a ninth resistor R9 and a second capacitor C2. The ninth resistor R9 is connected between the latch signal output terminal 120 and the base of the first transistor Q1, and the second capacitor C2 is connected between the base of the first transistor Q1 and the ground.

[0053] In this embodiment, by providing an input protection module in the control circuit, it is possible to prevent the pulses emitted by the main control module when an abnormality occurs (such as OTA upgrade, external interference, etc.) from interfering with the control circuit.

[0054] The above is the control circuit provided in the embodiment of the present application. The working principle of the control circuit provided in the present application is described in detail below in combination with a specific circuit structure.

[0055] Smart control products on the market generally have OTA upgrade activities, during which the MCU in the product will restart; in addition, if the product is disturbed by other external factors such as static electricity, the MCU in the product will also restart, causing the relay circuit controlled by the MCU to be disconnected. If the relay circuit is connected to a fish tank or other important function control system, then during the OTA upgrade process or when subjected to abnormal external interference, the restart of the MCU will cause major malfunctions. To this end, an embodiment of the present application provides a control circuit that can prevent possible abnormalities in the main control module (such as OTA upgrades, external interference, etc.) from affecting the working state of the relay, ensuring the stability of the relay circuit, thereby avoiding affecting the load connected to the relay.

[0056] Fig.12 is a structural diagram of a control circuit according to an embodiment of the present application, such as Fig.12 As shown, the relay 50 includes a control part and a switch part, wherein the pin 2 of the control part is respectively connected to the cathode of the diode D and the drain of the third transistor Q4, the pin 3 of the control part is respectively connected to the anode of the diode D and the ground, and the pins 1 and 4 of the switch part are used to connect to the load.

[0057] Optionally, the control unit is a relay coil, and the switch unit is a relay switch. By energizing the relay coil, the relay switch can be controlled to be closed, and by de-energizing the relay coil, the relay switch can be controlled to be opened.

[0058] In this embodiment, in order to explain the working principle of the control circuit, Fig.12In the diagram, for each transistor, 1 is used to mark the base, 2 is used to mark the emitter, and 3 is used to mark the collector. For each transistor, 1 is used to mark the gate, 2 is used to mark the source, and 3 is used to mark the drain. In addition, Fig.12 is Fig.11 Based on the schematic block diagram obtained by refining the relay working circuit, therefore, Fig.12 Zhongyu Fig.11 For the connection relationship between the parts with the same number, please refer to Fig.11 , I will not go into details here.

[0059] In this embodiment, EN_Relay is used to represent the enable signal output from the enable signal output terminal, and Latch is used to represent the control signal output from the latch signal output terminal.

[0060] In use Fig.12 When the control circuit shown is used as a control circuit in an intelligent control product, the relay can be controlled to be closed by setting the Latch signal and the EN_Relay signal to a high level. At this time, Q1 is turned on, so that the 3rd pin of Q1 is at a low level, so that the 1st pins of Q2 and Q3 are both at a low level. Since a voltage difference is generated between the gate and the source of the transistor (because the 2nd pin of Q2 and the 2nd pin of Q3 are both connected to VDD, that is, connected to the power supply voltage), Q2 and Q3 are turned on. In addition, Q6 is turned on, so that the 3rd pin of Q6 is at a low level, and the low level is transmitted to Q4 through the transmission of Q2 and Q3, so that the 1st pin of Q4 is at a low level. Since a voltage difference is generated between the gate and the source of the transistor, Q4 is turned on, and the voltage of VDD is transmitted to the relay through Q4, and the relay coil is energized, so that the relay switch is closed, and the working state of the relay is the closed state. In addition, since the level of pin 1 of Q5 is consistent with that of pin 3 of Q4, both are high levels transmitted by VDD, Q5 is turned on. In this way, a closed loop is formed between the drive module and the relay, so that the energized state of the relay can be maintained.

[0061] After the control relay is energized, the Latch signal can be set to a low level. In this case, Q1 is not conducting, so that pin 3 of Q1, pin 1 of Q2, and pin 1 of Q3 are all high levels transmitted from VDD. Since there is no voltage difference between the gate and source of the transistor, Q2 and Q3 are not conducting. When both Q2 and Q3 are not conducting, the EN_Relay signal cannot be transmitted to the relay. Therefore, even if an abnormality occurs in the main control module at this time, causing the main control module to frequently change the EN_Relay signal, it will not affect the working state of the relay, and the relay will still maintain the energized state under the drive of the drive module.

[0062] Similarly, the relay can be controlled to disconnect by setting the Latch signal to a high level and the EN_Relay signal to a low level. At this time, Q1 is turned on, so that pin 3 of Q1 is at a low level, so that pins 1 of Q2 and Q3 are both at a low level. Since a voltage difference is generated between the gate and source of the transistor, Q2 and Q3 are turned on. However, Q6 is not turned on, so that pin 3 of Q6 is at a high level. Through the transmission of Q2 and Q3, the high level is transmitted to Q4, so that pin 1 of Q4 is at a high level. Since there is no voltage difference between the gate and source of the transistor, Q4 is not turned on, and the voltage of VDD cannot be transmitted to the relay through Q4. The relay coil is powered off, so that the relay switch is disconnected, and the working state of the relay is the disconnected state. In addition, since the level of pin 1 of Q5 is consistent with that of pin 3 of Q4, when the power supply voltage cannot be transmitted, pin 1 of Q5 and pin 3 of Q4 are both at a low level, so Q5 is not turned on. In this way, a closed loop cannot be formed between the drive module and the relay, so that the disconnected state of the relay can be maintained.

[0063] After the control relay is disconnected, the Latch signal can be set to a low level. In this case, Q1 is not conducting, so that pin 3 of Q1, pin 1 of Q2, and pin 1 of Q3 are all high levels transmitted from VDD. Since there is no voltage difference between the gate and source of the transistor, Q2 and Q3 are not conducting. When both Q2 and Q3 are not conducting, the EN_Relay signal cannot be transmitted to the relay. Therefore, even if an abnormality occurs in the main control module at this time, causing the main control module to frequently change the EN_Relay signal, it will not affect the working state of the relay, and the relay can still maintain the disconnected state.

[0064] The control circuit provided by the embodiment of the present application is adopted, and the working state of the relay is controlled by the main control module, the switch module, the latch control module and the driver module. Wherein, the latch signal output terminal of the main control module is connected to the latch control module, so that the main control module can output a control signal through the latch signal output terminal to control the on-off of the latch control module. The enable signal output terminal of the main control module is connected to the relay through the switch module, the latch control module and the driver module in turn, so that when the latch control module is interrupted, the signal between the driver module and the main control module is interrupted, and the driver module drives the relay to maintain its own working state. It can be seen that in the technical scheme, by arranging the latch control module and the driver module between the relay and the main control module, the control circuit can be interrupted by controlling the latch control module, so that the working state of the relay is no longer controlled by the main control module, and the working state of the relay is maintained under the drive of the driver module, effectively avoiding the abnormality (such as OTA upgrade, interference from the outside, etc.) that may occur in the main control module. The influence on the working state of the relay is ensured, and the stability of the relay circuit is ensured, thereby avoiding the influence on the load connected to the relay, and improving the stability of the product containing the control circuit. Moreover, compared with the solution of using chips to implement control circuits in related technologies, this technical solution uses several modules to form a control circuit, does not rely on fixed chips, reduces development costs and difficulty, and can realize a variety of control circuits by designing modules.

[0065] Fig.13 is a schematic block diagram of a control device according to an embodiment of the present application. Fig.13 The control device 1300 includes a control circuit 1310 provided in any of the above embodiments. The circuit structure of the control circuit 1310 has been described in detail in the above embodiments, so it will not be repeated here.

[0066] In summary, specific embodiments of the present subject matter have been described. Other embodiments are within the scope of the appended claims. In some cases, the actions recorded in the claims can be performed in a different order and still achieve the desired results. In addition, the processes depicted in the accompanying drawings do not necessarily require the specific order or sequential order shown to achieve the desired results. In some embodiments, multitasking and parallel processing can be advantageous.

[0067] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0068] The above is only an embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the scope of the claims of the present application.

Claims

1. A control circuit, characterized in that: It includes a main control module, a switch module, a latch control module, a drive module and a relay; among which, The main control module includes an enable signal output terminal and a latch signal output terminal; The latch signal output terminal is connected to the latch control module; the main control module outputs a control signal through the latch signal output terminal to control the on and off of the latch control module; The enable signal output end is connected to the relay through the switch module, the latch control module and the drive module in sequence; when the latch control module is interrupted, the signal between the drive module and the main control module is interrupted, and the drive module drives the relay to maintain its own working state.

2. The control circuit according to claim 1, characterized in that: The latch control module includes a first triode, a first transistor and a second transistor; The latch signal output terminal is connected to the first transistor; The first triode is connected to the first transistor and the second transistor respectively; the first transistor is connected to the switch module and the second transistor respectively; the second transistor is connected to the driving module.

3. The control circuit according to claim 2, characterized in that: The latch signal output terminal is connected to the base of the first transistor; The collector of the first triode is connected to the gate of the first transistor and the gate of the second transistor respectively, and the emitter of the first triode is grounded; The source of the first transistor is connected to the first power supply voltage and is connected to the switch module, and the drain of the first transistor is connected to the drain of the second transistor; The source of the second transistor is connected to the second power supply voltage and to the driving module, and the gate of the second transistor is connected to the third power supply voltage and to the gate of the first transistor.

4. The control circuit according to claim 3, characterized in that: The driving module includes a driving circuit and a level holding circuit; The driving circuit is connected to the latch control module, the level holding circuit and the relay respectively.

5. The control circuit according to claim 4, characterized in that: The driving circuit includes a third transistor; the level holding circuit includes a second triode and a voltage dividing unit; The third transistor is respectively connected to the second transistor, the second triode, the voltage dividing unit and the relay; The voltage dividing unit is connected to the second transistor.

6. The control circuit according to claim 5, characterized in that: The source of the third transistor is connected to the second power supply voltage and is connected to the source of the second transistor, the gate of the third transistor is respectively connected to the source of the second transistor and the collector of the second triode, and the drain of the third transistor is respectively connected to the voltage dividing unit and the relay; The voltage dividing unit is connected to the base and the emitter of the second triode respectively, and the emitter of the second triode is grounded.

7. The control circuit according to claim 6, characterized in that: The first transistor, the second transistor and the third transistor are P-type metal oxide semiconductor (PMOS) transistors.

8. The control circuit according to claim 3, characterized in that: The switch module includes a third triode; The base of the third transistor is connected to the enable signal output terminal, the collector of the third transistor is connected to the first power supply voltage and to the source of the first transistor, and the emitter of the third transistor is grounded.

9. The control circuit according to claim 1, characterized in that: The control circuit also includes an input protection module; The input protection module is connected between the latch signal output terminal and the latch control module.

10. A control device, characterized in that: The method comprises a control circuit as claimed in any one of claims 1 to 9.

Images