Mainboard, daughter card and electronic equipment

Abstract

The embodiment of the utility model provides a mainboard, a daughter card and electronic equipment. The first mainboard comprises a selection switch, a phase-locked loop and at least one first clock buffer, the output end of the selection switch is connected with the input end of the phase-locked loop, and the selection switch is used for gating one of the input ends of the selection switch and the output end of the selection switch; a plurality of input ends of the selection switch are respectively used for inputting a first clock source signal and a second clock source signal, the first clock source signal is generated by a clock source of the first mainboard, and the second clock source signal is generated by a clock source of the daughter card; the output end of the phase-locked loop is connected with the input end of the first clock buffer, and the phase-locked loop is used for outputting a first output clock signal to the first clock buffer; the first clock buffers are used for buffering first output clock signals and outputting second output clock signals to the daughter cards, and one first clock buffer corresponds to one daughter card.

Description

Technical Field

[0001] The utility model relates to the technical field of signal measurement, in particular to a mainboard, a daughter card and an electronic device. Background Art

[0002] Traditional test and measurement instruments are large, heavy and have single functions. As modular hardware standards become more and more complete and popular, more and more test and measurement instruments are beginning to use modular platforms. Unlike traditional test instruments, modular test and measurement platforms can accommodate more functional modules and share a power supply system, saving resources and costs to a certain extent.

[0003] Mixed signal test instruments contain multiple digital and analog daughter cards, which usually require multiple daughter cards to work simultaneously. When performing analog-to-digital conversion (ADC) and digital-to-analog conversion (DAC) tests, the synchronous sampling system requires synchronization between the clocks of each daughter card. Modular test and measurement instruments generate and collect signals simultaneously, requiring synchronization between the clocks of the signal generator and the signal collector. For example, in a distributed measurement scenario using multiple instruments, the cascade between multiple instruments also requires clock synchronization. Utility Model Content

[0004] Embodiments of the present disclosure provide a mainboard, a daughter card, and an electronic device.

[0005] According to a first aspect of an embodiment of the present disclosure, a first mainboard is provided, wherein the first mainboard is used to connect at least one daughter card;

[0006] The first mainboard includes: a selection switch, a phase-locked loop and at least one first clock buffer, wherein:

[0007] The output end of the selection switch is connected to the input end of the phase-locked loop, and the selection switch is used to select one of the multiple input ends of the selection switch and the output end of the selection switch, wherein the multiple input ends of the selection switch are used to input a first clock source signal and a second clock source signal respectively, wherein the first clock source signal is generated by the clock source of the first mainboard, and the second clock source signal is generated by the clock source of the daughter card;

[0008] The output end of the phase-locked loop is connected to the input end of the first clock buffer, and the phase-locked loop is used to output a first output clock signal to the first clock buffer;

[0009] The first clock buffer is used to buffer the first output clock signal and output a second output clock signal to the daughter card, wherein one first clock buffer corresponds to one daughter card.

[0010] In some embodiments, one of the multiple input terminals of the selection switch is also used to input a third clock source signal, wherein the third clock source signal is generated by a clock source of the second mainboard.

[0011] In some embodiments, the first mainboard further includes: at least one first frequency divider disposed between the first clock buffer and the daughter card, wherein one first frequency divider corresponds to one first clock buffer;

[0012] The first frequency divider is used to perform M-frequency division on the first output clock signal buffered by the first clock buffer, and output a second output clock signal obtained after the M-frequency division to the daughter card for use.

[0013] In some embodiments, the phase-locked loop includes: a second frequency divider;

[0014] The second frequency divider is used to divide the first output clock signal by N to obtain a third output clock signal, wherein the third output clock signal is used to be output to a third mainboard, and N is an integer greater than or equal to 1.

[0015] In some embodiments, the third output clock signal is input into a phase detector of the phase-locked loop as a frequency feedback signal of the phase-locked loop.

[0016] In some embodiments, the first mainboard further includes at least one of the following:

[0017] a second clock buffer, for buffering the third output clock signal output to the third mainboard;

[0018] A filter is used to filter the third output clock signal output to the third mainboard.

[0019] According to a second aspect of an embodiment of the present disclosure, a daughter card is provided, wherein the daughter card is used to connect to a first mainboard;

[0020] The daughter card includes a clock source for generating a second clock source signal, and the second clock source signal is output to the first mainboard;

[0021] The daughter card is used to receive the second output clock signal output by the first mainboard, wherein the second output clock signal is obtained by buffering the first output clock signal output by the phase-locked loop of the first mainboard through the first clock buffer of the first mainboard; wherein the input end of the phase-locked loop is connected to the output end of the selection switch of the first mainboard, and the output end of the selection switch is connected to one of the selected multiple input ends selected by the selection switch, wherein the multiple input ends of the selection switch are respectively used to input the first clock source signal and the second clock source signal, wherein the first clock source signal is generated by the clock source of the first mainboard.

[0022] In some embodiments, one of the multiple input terminals of the selection switch is also used to input a third clock source signal, wherein the third clock source signal is generated by a clock source of the second mainboard.

[0023] In some embodiments, the second output clock signal is obtained by buffering the first output clock signal output by the phase-locked loop through the first clock buffer of the first mainboard and dividing it by M through the first divider on the first mainboard, where M is an integer greater than or equal to 1.

[0024] According to a third aspect of an embodiment of the present disclosure, an electronic device is provided, wherein the electronic device includes at least one of the following:

[0025] The first mainboard according to the first aspect;

[0026] The daughter card described in the second aspect.

[0027] According to an embodiment of the present disclosure, a first mainboard is disclosed, wherein the first mainboard is used to connect at least one daughter card; the first mainboard also includes: a selection switch, a phase-locked loop and at least one first clock buffer, wherein the output end of the selection switch is connected to the input end of the phase-locked loop, and the selection switch is used to select one of the multiple input ends of the selection switch and the output end of the selection switch, wherein the multiple input ends of the selection switch are respectively used to input a first clock source signal and a second clock source signal, wherein the first clock source signal is generated by the clock source of the first mainboard, and the second clock source signal is generated by the clock source of the daughter card; the output end of the phase-locked loop is connected to the input end of the first clock buffer, and the phase-locked loop is used to output a first output clock signal to the first clock buffer; the first clock buffer is used to buffer the first output clock signal and output a second output clock signal to the daughter card, wherein one first clock buffer corresponds to one daughter card. In this way, the mainboard selects the clock source signal through the selection switch, and locks the phase of the clock signal output to the daughter card through the phase-locked loop and the clock buffer. On the one hand, the flexibility of selecting the clock source signal is improved to meet the needs of different scenarios. On the other hand, the synchronization of the clock signals output to each daughter card is achieved. On the other hand, the clock source signal with higher performance parameters on the daughter card can be used as the clock source of the first mainboard, which improves the clock quality and makes the entire system clock have the same source to meet the synchronization requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 is a schematic diagram of the architecture of a mainboard and a daughter card according to an exemplary embodiment;

[0029] Figure 2 is a schematic diagram of the architecture of a mainboard according to an exemplary embodiment;

[0030] Figure 3 is a schematic diagram of the architecture of a mainboard according to an exemplary embodiment;

[0031] Figure 4 is a schematic diagram of the architecture of a mainboard and a daughter card according to an exemplary embodiment;

[0032] Figure 5 is a schematic diagram of an architecture of a clock unit according to an exemplary embodiment;

[0033] Figure 6 is a schematic diagram of the architecture of a mainboard according to an exemplary embodiment;

[0034] Figure 7 is a schematic diagram of the architecture of a mainboard according to an exemplary embodiment;

[0035] Figure 8is a schematic diagram of the architecture of a mainboard according to an exemplary embodiment;

[0036] Fig. 9 is a schematic diagram of a cascade architecture according to an exemplary embodiment;

[0037] Fig.10 is a schematic diagram of the architecture of a mainboard and a daughter card according to an exemplary embodiment;

[0038] Fig.11 is a schematic diagram of an electronic device according to an exemplary embodiment;

[0039] Fig.12 The figure is a schematic diagram showing the architecture of a mainboard according to an exemplary embodiment. DETAILED DESCRIPTION

[0040] In order to make the technical solutions and beneficial effects of the utility model more obvious and easy to understand, the following is a detailed description by listing specific embodiments. The drawings are not necessarily drawn to scale, and local features may be enlarged or reduced to more clearly show the details of the local features; unless otherwise defined, the technical and scientific terms used herein have the same meanings as those in the technical field to which this application belongs.

[0041] The embodiments of the present disclosure are not exhaustive, but are only illustrative of some embodiments, and are not intended to be a specific limitation on the scope of protection of the present disclosure. In the absence of contradiction, each step in a certain embodiment can be implemented as an independent embodiment, and the steps can be arbitrarily combined. For example, a solution after removing some steps in a certain embodiment can also be implemented as an independent embodiment, and the order of the steps in a certain embodiment can be arbitrarily exchanged. In addition, the optional implementation methods in a certain embodiment can be arbitrarily combined; in addition, the embodiments can be arbitrarily combined, for example, some or all of the steps of different embodiments can be arbitrarily combined, and a certain embodiment can be arbitrarily combined with the optional implementation methods of other embodiments.

[0042] In each embodiment of the present disclosure, unless otherwise specified or there is a logical conflict, the terms and / or descriptions between the embodiments are consistent and can be referenced to each other, and the technical features in different embodiments can be combined to form a new embodiment based on their internal logical relationships.

[0043] The terms used in the embodiments of the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0044] In the embodiments of the present disclosure, unless otherwise specified, elements expressed in the singular form, such as "a", "an", "the", "above", "said", "aforementioned", "this", etc., may mean "one and only one", or "one or more", "at least one", etc. For example, when using articles such as "a", "an", "the" in English in translation, the noun after the article may be understood as a singular expression or a plural expression.

[0045] In the embodiments of the present disclosure, “plurality” refers to two or more.

[0046] In some embodiments, the terms "at least one", "one or more", "a plurality of", "multiple", etc. can be used interchangeably.

[0047] In some embodiments, "at least one of A and B", "A and / or B", "A in one case, B in another case", "A in one case, B in another case", etc., may include the following technical solutions according to the situation: in some embodiments, A (A is executed independently of B); in some embodiments, B (B is executed independently of A); in some embodiments, execution is selected from A and B (A and B are selectively executed); in some embodiments, A and B (both A and B are executed). When there are more branches such as A, B, C, etc., the above is also similar.

[0048] In some embodiments, the recording method of "A or B" may include the following technical solutions according to the situation: in some embodiments, A (A is executed independently of B); in some embodiments, B (B is executed independently of A); in some embodiments, execution is selected from A and B (A and B are selectively executed). When there are more branches such as A, B, C, etc., the above is also similar.

[0049] The prefixes such as "first" and "second" in the embodiments of the present disclosure are only used to distinguish different description objects, and do not constitute restrictions on the position, order, priority, value or content of the description objects. The statement of the description object refers to the description in the context of the claims or embodiments, and should not constitute redundant restrictions due to the use of prefixes. For example, if the description object is a "field", the ordinal number before the "field" in the "first field" and the "second field" does not limit the position or order between the "fields", and the "first" and "second" do not limit whether the "fields" they modify are in the same message, nor do they limit the order of the "first field" and the "second field". For another example, if the description object is a "level", the ordinal number before the "level" in the "first level" and the "second level" does not limit the priority between the "levels". For another example, the numerical value of the description object is not limited by the ordinal number, and can be one or more. Taking the "first device" as an example, the numerical value of the "device" can be one or more. In addition, the objects modified by different prefixes may be the same or different. For example, if the description object is "device", then the "first device" and the "second device" may be the same device or different devices, and their types may be the same or different. For another example, if the description object is "information", then the "first information" and the "second information" may be the same information or different information, and their contents may be the same or different.

[0050] In some embodiments, “including A”, “comprising A”, “used to indicate A”, and “carrying A” can be interpreted as directly carrying A or indirectly indicating A.

[0051] In some embodiments, terms such as “…”, “determine…”, “in the case of…”, “at the time of…”, “when…”, “if…”, “if…”, etc. can be used interchangeably.

[0052] In some embodiments, terms such as "greater than", "greater than or equal to", "not less than", "more than", "more than or equal to", "not less than", "higher than", "higher than or equal to", "not lower than", and "above" can be replaced with each other, and terms such as "less than", "less than or equal to", "not greater than", "less than", "less than or equal to", "no more than", "lower than", "lower than or equal to", "not higher than", and "below" can be replaced with each other.

[0053] In some embodiments, devices, etc. can be interpreted as physical or virtual, and their names are not limited to the names recorded in the embodiments. Terms such as "device", "equipment", "device", "circuit", "network element", "node", "function", "unit", "section", "system", "network", "chip", "chip system", "entity", and "subject" can be used interchangeably.

[0054] In addition, each element, each row, or each column in the table of the embodiments of the present disclosure may be implemented as an independent embodiment, and the combination of any elements, any rows, and any columns may also be implemented as an independent embodiment.

[0055] In some embodiments, for a system with a mainboard and multiple daughter cards, there are three main schemes for achieving clock synchronization between multiple daughter cards: (1) multiple daughter cards obtain a common sampling clock from the mainboard; (2) an onboard reference clock is set, which is a clock source set on the backplane of the measuring instrument. The main card and each daughter card use this clock source as a reference clock source; (3) a dedicated clock daughter card is set, and this clock is used as the reference clock source for the entire system.

[0056] For example, in modular instruments based on the PCI Express eXtensions Instrumentation (PXIe) bus standard for instrumentation systems, the PXIe 100 MHz system clock (called PXIe_CLK100 in the specification) is distributed to all peripheral modules in the system. This common reference clock is used to measure or control the synchronization of multiple modules in the system.

[0057] The performance characteristics of digital clocks are often measured by parameters such as skew and jitter. Skew refers to the phase shift between different digital clocks, and the impact on synchronization accuracy is a systematic error; while jitter refers to the instability of the clock signal caused by the transmission of noise carried by components such as oscillators and filters in the clock signal loop, and the impact on synchronization accuracy is a random error.

[0058] In some embodiments, if the daughter card has high requirements for system clock performance, the daughter card requirements can only be met by modifying the motherboard clock unit or the onboard clock unit, which has a long development cycle and high costs.

[0059] In some embodiments, the clock of the daughter card can be provided by the daughter card onboard crystal oscillator or by the mainboard. The system lacks flexibility. When the daughter card needs a high-quality clock, the mainboard clock unit needs to be modified, or provided by the daughter card onboard clock unit. The daughter card onboard clock unit solution will cause the daughter card and the mainboard and other daughter cards to have different clock sources. In applications with synchronization requirements, the design is not suitable.

[0060] In summary, in a system with a motherboard and multiple daughter cards, the problems that need to be solved include:

[0061] 1. When the daughter card has higher requirements for the system clock performance, the clock signal requirements of the daughter card can only be met by modifying the motherboard clock unit or the onboard clock unit, resulting in a lack of flexibility in the system, a long instrument development cycle, and high development costs;

[0062] 2. The clock signal scheme of the daughter card's onboard clock unit will cause the clocks of the daughter card, the mainboard and other daughter cards to be different from each other, and high synchronization accuracy cannot be achieved;

[0063] 3. Using a daughter card onboard clock unit will occupy an extra card slot, the instrument size will increase, and setting up a dedicated clock card slot will increase the complexity of instrument design. Moreover, when the user does not need to use a dedicated clock daughter card, the design cost of the clock card slot still needs to be borne, and the overall cost will increase.

[0064] Figure 1 A first mainboard 100 is shown according to an embodiment of the present disclosure, and the first mainboard 100 is used to connect at least one daughter card 200;

[0065] like Figure 2 As shown, the first mainboard 100 includes: a selection switch 110, a phase-locked loop 120 and at least one first clock buffer 130, wherein:

[0066] The output end of the selection switch 110 is connected to the input end of the phase-locked loop 120, and the selection switch 110 is used to select one of the multiple input ends of the selection switch 110 and the output end of the selection switch 110, wherein the multiple input ends of the selection switch 110 are used to input a first clock source signal and a second clock source signal respectively, wherein the first clock source signal is generated by the clock source of the first mainboard 100, and the second clock source signal is generated by the clock source of the daughter card 200;

[0067] The output end of the phase-locked loop 120 is connected to the input end of the first clock buffer 130, and the phase-locked loop 120 is used to output a first output clock signal to the first clock buffer 130;

[0068] The first clock buffer 130 is used to buffer the first output clock signal and output a second output clock signal to the daughter card 200 , wherein one first clock buffer 130 corresponds to one daughter card 200 .

[0069] Figure 2 In the embodiment, the selection switch 110 , the phase-locked loop 120 and the first clock buffer 130 constitute a clock unit of the first main board 100 .

[0070] Here, the first mainboard 100 may include a system mainboard (module) of an electronic device. The daughter card 200 may include a peripheral daughter card 200 (module) of an electronic device. The daughter card 200 may implement or expand the functions of the electronic device, such as implementing ADC and / or DAC, etc., but is not limited thereto.

[0071] In a possible implementation, the first mainboard 100 and the daughter card 200 may be connected via an intermediate connecting board (also referred to as a backplane). The intermediate connecting board may be provided with a first connector for connecting the first mainboard 100 and a second connector for connecting the daughter card 200. At least one second connector may be provided.

[0072] Exemplarily, the first mainboard 100 may be a system module in an electronic device that adopts the PXIe bus standard, and the daughter card 200 may be a peripheral module in the electronic device. The first mainboard 100 and the daughter card 200 may be connected via a backplane in the electronic device. The backplane may be provided with a system slot for connecting the first mainboard 100, and at least one peripheral slot for connecting the daughter card 200.

[0073] In a possible implementation, at least one connector for connecting the sub-card 200 may be provided on the first mainboard 100 , and the sub-card 200 may be connected to the first mainboard 100 via the connector.

[0074] In a possible implementation, the electronic device may include signal measurement related devices such as an oscilloscope, a signal generator, etc. The daughter card 200 may include a signal acquisition card, a signal generation card, etc.

[0075] In a possible implementation, the selection switch 110 may be a switch having a plurality of input terminals and an output terminal. The first clock source signal and the second clock source signal may be respectively connected to an input terminal of the selection switch 110. The selection switch 110 may be controlled to select one of the first clock source signal and the second clock source signal to be output from the output terminal of the selection switch 110.

[0076] In practical applications, the selection switch 110 can be implemented by a relay, an electronic switch, etc.

[0077] In some embodiments, Figure 3 As shown, one of the multiple input terminals of the selection switch 110 is also used to input a third clock source signal, wherein the third clock source signal is generated by a clock source of the second mainboard.

[0078] Different input terminals of the selection switch 110 are used to input the first clock source signal, the second clock source signal and the third clock source signal respectively.

[0079] The first clock source signal, the second clock source signal and the third clock source signal can be respectively connected to one input terminal of the selection switch 110. The selection switch 110 can be controlled to select one of the first clock source signal, the second clock source signal and the third clock source signal to be output from the output terminal of the selection switch 110.

[0080] In a possible implementation, the clock source may include at least one of the following: a crystal oscillator, a clock oscillator, and a semiconductor device that generates a clock signal.

[0081] In a possible implementation, the clock source of the first mainboard 100, the clock source of the daughter card 200 and the clock source of the second mainboard may be the same, may not be completely the same, or may be completely different. For example, the performance of the clock source of the daughter card 200 may be better than the clock source of the first mainboard 100, that is, the clock parameters of the second clock source signal are better than the clock parameters of the first clock source signal, wherein the clock parameters include at least one of the following: offset and jitter.

[0082] In a possible implementation, the second mainboard may include a mainboard that does not belong to the same electronic device as the first mainboard 100. For example, the first mainboard 100 is a mainboard in an oscilloscope, and the second mainboard may be a mainboard in a signal generator.

[0083] In a possible implementation, the first mainboard 100 and the second mainboard may be mainboards of the same type. For example, the first mainboard 100 and the second mainboard may be mainboards having the same software and hardware.

[0084] In a possible implementation, the first mainboard 100 and the second mainboard may be mainboards of different types. For example, the first mainboard 100 and the second mainboard may have at least one different item of software and hardware.

[0085] The phase-locked loop 120 can be used to lock the phase of the output clock signal with the input clock signal, thereby outputting stable clock information.

[0086] When one of the first clock source signal, the second clock source signal and the third clock source signal is used as the input clock signal of the phase-locked loop 120, the frequency of the first output clock signal can be the same as the frequency of the input clock signal, or the frequency of the first output clock signal can be a multiple of the frequency of the input clock signal.

[0087] The second output clock signal is a clock signal obtained after the first output clock signal is buffered by the first clock buffer 130. The first clock buffer 130 can be used to improve the driving capability of the clock signal and reduce the change of clock parameters caused by the load of the second output clock signal.

[0088] In a possible implementation, the first mainboard 100 may generate a plurality of second output clock signals through a plurality of first clock buffers 130 . The second output clock signals may be output to the daughter card 200 or may be used by the first mainboard 100 .

[0089] In a possible implementation, the second output clock signal is provided to the daughter card 200 for performing at least one of the following: data processing; data transmission; analog-to-digital conversion; and digital-to-analog conversion.

[0090] In a possible implementation, the first output clock signal and / or the second output clock signal is also used by the first mainboard 100 to perform at least one of the following: data processing; data transmission; analog-to-digital conversion; digital-to-analog conversion.

[0091] Each daughter card 200 uses the second output clock to achieve synchronization between the daughter cards 200 .

[0092] In a possible implementation, the first mainboard 100 may select one of the first clock source signal, the second clock source signal, and the third clock source signal as the input of the phase-locked loop 120 according to actual needs.

[0093] In a possible implementation, the first mainboard 100 may select a clock source on the first mainboard 100 as an input of the phase-locked loop 120 to output a second output clock signal to meet synchronization requirements of the first mainboard 100 and / or the daughter card 200 .

[0094] In a possible implementation, when the performance of the clock source on the first mainboard 100 cannot meet the requirements of the first mainboard 100 and / or the daughter card 200 (such as the performance parameter is lower than the performance threshold), the first mainboard 100 can select the clock source of the daughter card 200 (the performance parameter is higher than the performance threshold) as the input of the phase-locked loop 120, so that the phase-locked loop 120 can output the second output clock signal based on the second clock source signal with better clock parameters to meet the requirements of the first mainboard 100 and / or the daughter card 200. The performance parameter includes at least one of the following: offset and jitter.

[0095] In one possible implementation, when the electronic device corresponding to the first mainboard 100 and the electronic device corresponding to the second mainboard need to work in cascade, the first mainboard 100 can select the clock source of the second mainboard as the input of the phase-locked loop 120, so that the phase-locked loop 120 can output a second output clock signal synchronized with the second mainboard, thereby meeting the synchronization requirements of the electronic device corresponding to the first mainboard 100 and the electronic device corresponding to the first mainboard 100.

[0096] In one possible implementation, Figure 4As shown (some components are not shown), daughter card 1 can provide a second clock source signal to the first mainboard 100, and daughter card 1 can receive a second output clock signal, wherein the second output clock signal can be generated by the first mainboard 100 through the second clock source signal.

[0097] In one possible implementation, Figure 4 As shown, daughter card 1 can have the ability to provide a second clock source signal to the first mainboard 100, and daughter card 1 can receive a second output clock signal, wherein the second output clock signal can be generated by the first mainboard 100 through any one of the first clock source signal, the second clock source signal and the third clock source signal.

[0098] In one possible implementation, Figure 4 As shown, sub-card 2 may not have the ability to provide a second clock source signal to the first mainboard 100, and sub-card 2 may receive a second output clock signal, wherein the second output clock signal may be generated by the first mainboard 100 through any one of the first clock source signal, the second clock source signal and the third clock source signal, wherein the second clock source signal may be sent by sub-card 1 to the first mainboard 100.

[0099] In one possible implementation, multiple daughter cards 200 may have the ability to provide second clock source signals to the first mainboard 100 , and a multiple selection switch may be provided on the first mainboard 100 to select one of the multiple second clock source signals and output it to the input end of the selection switch 110 .

[0100] In one possible implementation, multiple daughter cards 200 may have the ability to provide a second clock source signal to the first main board 100. In addition to the input terminals for inputting the first clock source signal and the third clock source signal, the selection switch 110 also has multiple input terminals for inputting the second clock source signal for respectively receiving the second clock source signals of the multiple daughter cards 200.

[0101] In practical applications, such as Figure 5 As described above, the mainboard clock unit of the first mainboard 100 can send the second output clock signal to the daughter card 200 clock unit of the daughter card 200, so that the first mainboard 100 and the daughter card 200 can be synchronized. The daughter card 200 clock unit of the daughter card 200 can also provide a clock source signal to the mainboard clock unit of the first mainboard 100 to meet different requirements for the clock source signal.

[0102] In this way, the mainboard selects the clock source signal through the selection switch 110, and locks the phase of the clock signal output to the daughter card 200 through the phase-locked loop 120 and the clock buffer. On the one hand, the flexibility of selecting the clock source signal is improved to meet the needs of different scenarios. On the other hand, the synchronization of the clock signals output to each daughter card 200 is achieved. On the other hand, the clock source signal with higher performance parameters on the daughter card 200 can be used as the clock source of the first mainboard 100, which improves the clock quality and makes the entire system clock have the same source to meet the synchronization requirements.

[0103] In some embodiments, Figure 6 As shown, the first mainboard 100 further includes: at least one first frequency divider 140 disposed between the first clock buffer 130 and the daughter card 200 , wherein one first frequency divider 140 corresponds to one first clock buffer 130 ;

[0104] The first frequency divider 140 is used to perform M-frequency division on the first output clock signal buffered by the first clock buffer 130, and output a second output clock signal obtained after the M-frequency division to the daughter card 200 for use.

[0105] M is an integer greater than or equal to 1.

[0106] Figure 6 In the embodiment, the selection switch 110 , the phase-locked loop 120 , the first clock buffer 130 and the first frequency divider 140 constitute a clock unit of the first main board 100 .

[0107] Here, the first clock buffer 130 may be connected to the first frequency divider 140 to divide the second output clock signal output by the first clock buffer 130 by M frequency, and output the M-divided second output clock signal to the daughter card 200 .

[0108] In a possible implementation, the daughter card 200 may not have a corresponding first frequency divider 140 , and the second output clock may be directly output to the daughter card 200 .

[0109] In a possible implementation, the M value of the first frequency divider 140 corresponding to each sub-card 200 is the same.

[0110] In a possible implementation, the M value of the first frequency divider 140 corresponding to each daughter card 200 is not completely the same. The first frequency divider 140 can be set based on the clock frequency required by the daughter card 200.

[0111] In some embodiments, Figure 7 As shown, the phase-locked loop 120 includes: a second frequency divider 121;

[0112] The second frequency divider 121 is used to divide the first output clock signal by N to obtain a third output clock signal, wherein the third output clock signal is used to be output to a third mainboard, and N is an integer greater than or equal to 1.

[0113] A second frequency divider 121 may be provided in the phase-locked loop 120, and the frequency of the first output clock signal is N times the frequency of the input clock signal of the phase-locked loop 120 (ie, one of the selected first clock source signal, second clock source signal and third clock source signal), and the phases are the same.

[0114] According to the working principle of the phase-locked loop 120, here, the frequency of the third output clock signal may be the same as the frequency of the input clock of the phase-locked loop 120 (ie, one of the selected first clock source signal, second clock source signal and third clock source signal).

[0115] In a possible implementation, the third mainboard may include a mainboard that does not belong to the same electronic device as the first mainboard 100. For example, the first mainboard 100 is a mainboard in an oscilloscope, and the third mainboard may be a mainboard in a signal generator.

[0116] In a possible implementation, the first mainboard 100 and the third mainboard may be mainboards of the same type. For example, the first mainboard 100 and the second mainboard may be mainboards having the same software and hardware.

[0117] In a possible implementation, the first mainboard 100 and the third mainboard may be mainboards of different types. For example, the first mainboard 100 and the second mainboard are different in at least one of software and hardware.

[0118] In a possible implementation, the third mainboard may use the third output clock signal as the clock source signal of the third mainboard (equivalent to the third clock source signal on the first mainboard 100). When the electronic device corresponding to the first mainboard 100 and the electronic device corresponding to the third mainboard need to be cascaded, since the first output clock signal, the second output clock source signal in the first mainboard 100, and the clock source signal (third output clock signal) used by the third mainboard have the same phase, synchronization between the electronic device corresponding to the first mainboard 100 and the electronic device corresponding to the third mainboard is achieved.

[0119] In some embodiments, Figure 7 As shown, the third output clock signal is input into the phase detector 122 of the phase locked loop 120 as a frequency feedback signal of the phase locked loop 120 .

[0120] The third output clock signal serves as a frequency feedback signal of the phase-locked loop 120, which can reduce the phase difference between the first output clock signal and the input clock signal of the phase-locked loop 120 (i.e., one of the selected first clock source signal, second clock source signal and third clock source signal), and further reduce the phase difference between the third output clock signal and the input clock signal of the phase-locked loop 120, thereby improving the synchronization of the direct clock signals of the first mainboard 100 and the third mainboard.

[0121] In some embodiments, Figure 8 As shown, the first mainboard 100 further includes at least one of the following:

[0122] A second clock buffer 150, for buffering the third output clock signal output to the third mainboard;

[0123] The filter 160 is used to filter the third output clock signal output to the third mainboard.

[0124] Figure 8 In the embodiment, the selection switch 110 , the phase-locked loop 120 , the first clock buffer 130 , the first frequency divider 140 , the second clock buffer 150 and the filter 160 constitute a clock unit of the first mainboard 100 .

[0125] In order to reduce the impact of interference on the third output clock signal during transmission and / or reduce the impact of the load on the third output clock signal, after the phase-locked loop 120 outputs the third output clock signal, the third output clock signal can be buffered by the second clock buffer 150 to improve the driving capability of the third output clock signal. The third output clock signal can also be filtered by the filter 160 to improve the signal integrity of the third output clock signal.

[0126] In practical applications, such as Fig. 9 As shown, the first mainboard 100 in instrument 2 (i.e., electronic device) can use the output clock CLK REF OUT (i.e., the third clock source signal) of the second mainboard in instrument 1 as the clock source signal input CLK REFIN, and the third mainboard in instrument 3 uses the output clock CLK REF OUT (i.e., the third output clock signal) of the first mainboard 100 as the clock source signal input CLK REF IN, and so on. The output clock CLK REF OUT output by the third mainboard can be used as the clock source signal input CLK REF IN of the subsequent mainboard, thereby realizing the cascading of instruments, and then enabling the cascaded instruments (electronic devices) to achieve clock synchronization.

[0127] Fig.10 A daughter card 200 is shown according to an embodiment of the present disclosure, and the daughter card 200 is used to connect to the first mainboard 100;

[0128] The daughter card 200 includes a clock source for generating a second clock source signal, and the second clock source signal is output to the first mainboard 100;

[0129] The daughter card 200 is used to receive the second output clock signal output by the first mainboard 100, wherein the second output clock signal is the first output clock signal output by the phase-locked loop 120 of the first mainboard 100, and is obtained after being buffered by the first clock buffer 130 of the first mainboard 100; wherein the input end of the phase-locked loop 120 is connected to the output end of the selection switch 110 of the first mainboard 100, and the output end of the selection switch 110 is connected to one of the multiple selected input ends selected by the selection switch 110, wherein the multiple input ends of the selection switch 110 are respectively used to input the first clock source signal and the second clock source signal, wherein the first clock source signal is generated by the clock source of the first mainboard 100.

[0130] In a possible implementation, the connection between the subcard 200 and the first mainboard 100 is as follows: Figure 1 shown.

[0131] In a possible implementation, the structure of the first mainboard 100 is as follows: Figure 2 shown. Figure 2 In the embodiment, the selection switch 110 , the phase-locked loop 120 and the first clock buffer 130 constitute a clock unit of the first main board 100 .

[0132] Here, the first mainboard 100 may include a system mainboard (module) of an electronic device. The daughter card 200 may include a peripheral daughter card 200 (module) of an electronic device. The daughter card 200 may implement or expand the functions of the electronic device, such as implementing ADC and / or DAC, etc., but is not limited thereto.

[0133] In a possible implementation, the first mainboard 100 and the daughter card 200 may be connected via an intermediate connecting board (also referred to as a backplane). The intermediate connecting board may be provided with a first connector for connecting the first mainboard 100 and a second connector for connecting the daughter card 200. At least one second connector may be provided.

[0134] Exemplarily, the first mainboard 100 may be a system module in an electronic device that adopts the PXIe bus standard, and the daughter card 200 may be a peripheral module in the electronic device. The first mainboard 100 and the daughter card 200 may be connected via a backplane in the electronic device. The backplane may be provided with a system slot for connecting the first mainboard 100, and at least one peripheral slot for connecting the daughter card 200.

[0135] In a possible implementation, at least one connector for connecting the sub-card 200 may be provided on the first mainboard 100 , and the sub-card 200 may be connected to the first mainboard 100 via the connector.

[0136] In a possible implementation, the electronic device may include signal measurement related devices such as an oscilloscope, a signal generator, etc. The daughter card 200 may include a signal acquisition card, a signal generation card, etc.

[0137] In a possible implementation, the selection switch 110 may be a switch having a plurality of input terminals and an output terminal. The first clock source signal and the second clock source signal may be respectively connected to an input terminal of the selection switch 110. The selection switch 110 may be controlled to select one of the first clock source signal and the second clock source signal to be output from the output terminal of the selection switch 110.

[0138] In practical applications, the selection switch 110 can be implemented by a relay, an electronic switch, etc.

[0139] In some embodiments, Figure 3 As shown, one of the multiple input terminals of the selection switch 110 is also used to input a third clock source signal, wherein the third clock source signal is generated by a clock source of the second mainboard.

[0140] Different input terminals of the selection switch 110 are used to input the first clock source signal, the second clock source signal and the third clock source signal respectively.

[0141] The first clock source signal, the second clock source signal and the third clock source signal can be respectively connected to one input terminal of the selection switch 110. The selection switch 110 can be controlled to select one of the first clock source signal, the second clock source signal and the third clock source signal to be output from the output terminal of the selection switch 110.

[0142] In a possible implementation, the clock source may include at least one of the following: a crystal oscillator, a clock oscillator, and a semiconductor device that generates a clock signal.

[0143] In a possible implementation, the clock source of the first mainboard 100, the clock source of the daughter card 200 and the clock source of the second mainboard may be the same, may not be completely the same, or may be completely different. For example, the performance of the clock source of the daughter card 200 may be better than the clock source of the first mainboard 100, that is, the clock parameters of the second clock source signal are better than the clock parameters of the first clock source signal, wherein the clock parameters include at least one of the following: offset and jitter.

[0144] In a possible implementation, the second mainboard may include a mainboard that does not belong to the same electronic device as the first mainboard 100. For example, the first mainboard 100 is a mainboard in an oscilloscope, and the second mainboard may be a mainboard in a signal generator.

[0145] In a possible implementation, the first mainboard 100 and the second mainboard may be mainboards of the same type. For example, the first mainboard 100 and the second mainboard may be mainboards having the same software and hardware.

[0146] In a possible implementation, the first mainboard 100 and the second mainboard may be mainboards of different types. For example, the first mainboard 100 and the second mainboard may have at least one different item of software and hardware.

[0147] The phase-locked loop 120 can be used to lock the phase of the output clock signal with the input clock signal, thereby outputting stable clock information.

[0148] When one of the first clock source signal, the second clock source signal and the third clock source signal is used as the input clock signal of the phase-locked loop 120, the frequency of the first output clock signal can be the same as the frequency of the input clock signal, or the frequency of the first output clock signal can be a multiple of the frequency of the input clock signal.

[0149] The second output clock signal is a clock signal obtained after the first output clock signal is buffered by the first clock buffer 130. The first clock buffer 130 can be used to improve the driving capability of the clock signal and reduce the change of clock parameters caused by the load of the second output clock signal.

[0150] In a possible implementation, the first mainboard 100 may generate a plurality of second output clock signals through a plurality of first clock buffers 130 . The second output clock signals may be output to the daughter card 200 or may be used by the first mainboard 100 .

[0151] In a possible implementation, the second output clock signal is provided to the daughter card 200 for performing at least one of the following: data processing; data transmission; analog-to-digital conversion; and digital-to-analog conversion.

[0152] In a possible implementation, the first output clock signal and / or the second output clock signal is also used by the first mainboard 100 to perform at least one of the following: data processing; data transmission; analog-to-digital conversion; digital-to-analog conversion.

[0153] Each daughter card 200 uses the second output clock to achieve synchronization between the daughter cards 200 .

[0154] In a possible implementation, the first mainboard 100 may select one of the first clock source signal, the second clock source signal, and the third clock source signal as the input of the phase-locked loop 120 according to actual needs.

[0155] In a possible implementation, the first mainboard 100 may select a clock source on the first mainboard 100 as an input of the phase-locked loop 120 to output a second output clock signal to meet synchronization requirements of the first mainboard 100 and / or the daughter card 200 .

[0156] In a possible implementation, when the performance of the clock source on the first mainboard 100 cannot meet the requirements of the first mainboard 100 and / or the daughter card 200 (such as the performance parameter is lower than the performance threshold), the first mainboard 100 can select the clock source of the daughter card 200 (the performance parameter is higher than the performance threshold) as the input of the phase-locked loop 120, so that the phase-locked loop 120 can output the second output clock signal based on the second clock source signal with better clock parameters to meet the requirements of the first mainboard 100 and / or the daughter card 200. The performance parameter includes at least one of the following: offset and jitter.

[0157] In one possible implementation, when the electronic device corresponding to the first mainboard 100 and the electronic device corresponding to the second mainboard need to work in cascade, the first mainboard 100 can select the clock source of the second mainboard as the input of the phase-locked loop 120, so that the phase-locked loop 120 can output a second output clock signal synchronized with the second mainboard, thereby meeting the synchronization requirements of the electronic device corresponding to the first mainboard 100 and the electronic device corresponding to the first mainboard 100.

[0158] In one possible implementation, Figure 4 As shown (some components are not shown), daughter card 1 can provide a second clock source signal to the first mainboard 100, and daughter card 1 can receive a second output clock signal, wherein the second output clock signal can be generated by the first mainboard 100 through the second clock source signal.

[0159] In one possible implementation, Figure 4 As shown, daughter card 1 can have the ability to provide a second clock source signal to the first mainboard 100, and daughter card 1 can receive a second output clock signal, wherein the second output clock signal can be generated by the first mainboard 100 through any one of the first clock source signal, the second clock source signal and the third clock source signal.

[0160] In one possible implementation, Figure 4As shown, sub-card 2 may not have the ability to provide a second clock source signal to the first mainboard 100, and sub-card 2 may receive a second output clock signal, wherein the second output clock signal may be generated by the first mainboard 100 through any one of the first clock source signal, the second clock source signal and the third clock source signal, wherein the second clock source signal may be sent by sub-card 1 to the first mainboard 100.

[0161] In one possible implementation, multiple daughter cards 200 may have the ability to provide second clock source signals to the first mainboard 100 , and a multiple selection switch may be provided on the first mainboard 100 to select one of the multiple second clock source signals and output it to the input end of the selection switch 110 .

[0162] In one possible implementation, multiple daughter cards 200 may have the ability to provide a second clock source signal to the first main board 100. In addition to the input terminals for inputting the first clock source signal and the third clock source signal, the selection switch 110 also has multiple input terminals for inputting the second clock source signal for respectively receiving the second clock source signals of the multiple daughter cards 200.

[0163] In practical applications, such as Figure 5 As described above, the mainboard clock unit of the first mainboard 100 can send the second output clock signal to the daughter card 200 clock unit of the daughter card 200, so that the first mainboard 100 and the daughter card 200 can be synchronized. The daughter card 200 clock unit of the daughter card 200 can also provide a clock source signal to the mainboard clock unit of the first mainboard 100 to meet different requirements for the clock source signal.

[0164] In this way, the clock source signal with higher performance parameters on the daughter card 200 can be used as the clock source of the first mainboard 100, thereby improving the clock quality and making the clock of the entire system the same source to meet the synchronization requirements.

[0165] In some embodiments, Figure 6 As shown, the second output clock signal is obtained by buffering the first output clock signal output by the phase-locked loop 120 through the first clock buffer 130 of the first mainboard and dividing it by M through the first divider 140 on the first mainboard, where M is an integer greater than or equal to 1.

[0166] Figure 6 In the embodiment, the selection switch 110 , the phase-locked loop 120 , the first clock buffer 130 and the first frequency divider 140 constitute a clock unit of the first main board 100 .

[0167] Here, the first clock buffer 130 may be connected to the first frequency divider 140 to divide the second output clock signal output by the first clock buffer 130 by M frequency, and output the M-divided second output clock signal to the daughter card 200 .

[0168] In a possible implementation, the daughter card 200 may not have a corresponding first frequency divider 140 , and the second output clock may be directly output to the daughter card 200 .

[0169] In a possible implementation, the M value of the first frequency divider 140 corresponding to each sub-card 200 is the same.

[0170] In a possible implementation, the M value of the first frequency divider 140 corresponding to each daughter card 200 is not completely the same. The first frequency divider 140 can be set based on the clock frequency required by the daughter card 200.

[0171] In some embodiments, Figure 7 As shown, the phase-locked loop 120 includes: a second frequency divider 121;

[0172] The second frequency divider 121 is used to divide the first output clock signal by N to obtain a third output clock signal, wherein the third output clock signal is used to be output to a third mainboard, and N is an integer greater than or equal to 1.

[0173] A second frequency divider 121 may be provided in the phase-locked loop 120, and the frequency of the first output clock signal is N times the frequency of the input clock signal of the phase-locked loop 120 (ie, one of the selected first clock source signal, second clock source signal and third clock source signal), and the phases are the same.

[0174] According to the working principle of the phase-locked loop 120, here, the frequency of the third output clock signal may be the same as the frequency of the input clock of the phase-locked loop 120 (ie, one of the selected first clock source signal, second clock source signal and third clock source signal).

[0175] In a possible implementation, the third mainboard may include a mainboard that does not belong to the same electronic device as the first mainboard 100. For example, the first mainboard 100 is a mainboard in an oscilloscope, and the third mainboard may be a mainboard in a signal generator.

[0176] In a possible implementation, the first mainboard 100 and the third mainboard may be mainboards of the same type. For example, the first mainboard 100 and the second mainboard may be mainboards having the same software and hardware.

[0177] In a possible implementation, the first mainboard 100 and the third mainboard may be mainboards of different types. For example, the first mainboard 100 and the second mainboard are different in at least one of software and hardware.

[0178] In a possible implementation, the third mainboard may use the third output clock signal as the clock source signal of the third mainboard (equivalent to the third clock source signal on the first mainboard 100). When the electronic device corresponding to the first mainboard 100 and the electronic device corresponding to the third mainboard need to be cascaded, since the first output clock signal, the second output clock source signal in the first mainboard 100, and the clock source signal (third output clock signal) used by the third mainboard have the same phase, synchronization between the electronic device corresponding to the first mainboard 100 and the electronic device corresponding to the third mainboard is achieved.

[0179] In some embodiments, Figure 7 As shown, the third output clock signal is input into the phase detector 122 of the phase locked loop 120 as a frequency feedback signal of the phase locked loop 120 .

[0180] The third output clock signal serves as a frequency feedback signal of the phase-locked loop 120, which can reduce the phase difference between the first output clock signal and the input clock signal of the phase-locked loop 120 (i.e., one of the selected first clock source signal, second clock source signal and third clock source signal), and further reduce the phase difference between the third output clock signal and the input clock signal of the phase-locked loop 120, thereby improving the synchronization of the direct clock signals of the first mainboard 100 and the third mainboard.

[0181] In some embodiments, Figure 8 As shown, the first mainboard 100 further includes at least one of the following:

[0182] A second clock buffer 150, for buffering the third output clock signal output to the third mainboard;

[0183] The filter 160 is used to filter the third output clock signal output to the third mainboard.

[0184] Figure 8 In the embodiment, the selection switch 110 , the phase-locked loop 120 , the first clock buffer 130 , the first frequency divider 140 , the second clock buffer 150 and the filter 160 constitute a clock unit of the first mainboard 100 .

[0185] In order to reduce the impact of interference on the third output clock signal during transmission and / or reduce the impact of the load on the third output clock signal, after the phase-locked loop 120 outputs the third output clock signal, the third output clock signal can be buffered by the second clock buffer 150 to improve the driving capability of the third output clock signal. The third output clock signal can also be filtered by the filter 160 to improve the signal integrity of the third output clock signal.

[0186] In practical applications, such as Fig. 9As shown, the first mainboard 100 in instrument 2 (i.e., electronic device) can use the output clock CLK REF OUT (i.e., the third clock source signal) of the second mainboard in instrument 1 as the clock source signal input CLK REFIN, and the third mainboard in instrument 3 uses the output clock CLK REF OUT (i.e., the third output clock signal) of the first mainboard 100 as the clock source signal input CLK REF IN, and so on. The output clock CLK REF OUT output by the third mainboard can be used as the clock source signal input CLK REF IN of the subsequent mainboard, thereby realizing the cascading of instruments, and then enabling the cascaded instruments (electronic devices) to achieve clock synchronization.

[0187] Fig.11 An electronic device 10 according to an embodiment of the present disclosure includes at least one of the following:

[0188] The first main board 100 described in the first aspect;

[0189] The daughter card 200 according to the second aspect.

[0190] The first mainboard 100 is specifically implemented as follows Figures 1 to 9 The embodiments are shown in the figure and will not be described in detail here.

[0191] The specific implementation of the daughter card 200 is as follows Figures 1 to 10 The embodiments are shown in the figure and will not be described in detail here.

[0192] The following provides multiple specific examples in combination with any of the above embodiments:

[0193] like Fig.12 As shown, the system clock source of the mainboard can be provided by the daughter card A (i.e., the second clock source signal), CLK REF IN (instrument external reference clock input) (i.e., the third clock source signal), or the local crystal oscillator XO of the mainboard (i.e., the first clock source signal), and the clock source selection is switched by a switch (i.e., a selection switch). The PD phase detector, the filter filter, and the VCO voltage-controlled oscillator form a phase-locked loop, and the stable clock signal is buffered and then divided and output to each daughter card.

[0194] CLK REF OUT, instrument reference clock output, used for clock synchronization when multiple instruments are cascaded. Fig. 9 shown.

[0195] Figure 4 It is a distributed clock system, including a mainboard clock unit and multiple sub-card clock units, the mainboard clock unit is a main card clock unit or an onboard clock unit arranged on a backplane, and the mainboard clock unit and the multiple sub-card clock units are interconnected through signal links.

[0196] Figure 4 , 8 The main architecture of the motherboard clock unit. The source clock input of the motherboard clock unit can be the clock input of any daughter card A, the onboard clock source input, or the external reference clock source (CLK REF IN). It is switched through the Switch and processed by the motherboard clock unit before being distributed to each daughter card as the system clock. At the same time, the motherboard clock unit has the function of outputting the reference clock.

[0197] Fig. 9 When multiple instruments are cascaded and there is a need for clock homology, the reference clock output by instrument 1 can be used as the reference clock input of instrument 2 to make the clocks of multiple instruments homology. For example, when oscilloscopes, signal sources, spectrum analyzers, etc. are used in collaboration, this architecture can use the clock source with the highest specification on the daughter card / main card of the instrument as the source clock of the entire system, ensuring the optimal clock characteristics of the entire system.

[0198] With the distributed clock solution, the system source clock can be provided by the clock unit of the mainboard or by the daughter card. For daughter cards with high-quality clock requirements, the daughter card onboard clock unit can provide the clock to the mainboard, and then distribute it to each daughter card through the mainboard clock unit, which not only ensures the clock quality, but also makes the clock of the entire system the same source.

[0199] It should be understood that the above embodiments are exemplary and are not intended to include all possible implementations included in the claims. Various modifications and changes may be made on the basis of the above embodiments without departing from the scope of the present disclosure. Similarly, the various technical features of the above embodiments may be arbitrarily combined to form other embodiments of the utility model that may not be explicitly described. Therefore, the above embodiments only express several implementations of the utility model and do not limit the scope of protection of the utility model patent.

Claims

1. A motherboard, characterized in that: The mainboard includes a first mainboard, and the first mainboard is used to connect at least one daughter card; The first mainboard includes: a selection switch, a phase-locked loop and at least one first clock buffer, wherein: The output end of the selection switch is connected to the input end of the phase-locked loop, and the selection switch is used to select one of the multiple input ends of the selection switch and the output end of the selection switch, wherein the multiple input ends of the selection switch are used to input a first clock source signal and a second clock source signal respectively, wherein the first clock source signal is generated by the clock source of the first mainboard, and the second clock source signal is generated by the clock source of the daughter card; The output end of the phase-locked loop is connected to the input end of the first clock buffer, and the phase-locked loop is used to output a first output clock signal to the first clock buffer; The first clock buffer is used to buffer the first output clock signal and output a second output clock signal to the daughter card, wherein one first clock buffer corresponds to one daughter card.

2. The mainboard according to claim 1, characterized in that: One of the multiple input terminals of the selection switch is also used to input a third clock source signal, wherein the third clock source signal is generated by a clock source of the second mainboard.

3. The mainboard according to claim 1, characterized in that: The first mainboard further includes: at least one first frequency divider disposed between the first clock buffer and the daughter card, wherein one first frequency divider corresponds to one first clock buffer; The first frequency divider is used to perform M-frequency division on the first output clock signal buffered by the first clock buffer, and output a second output clock signal obtained after the M-frequency division to the daughter card for use.

4. The mainboard according to any one of claims 1 to 3, characterized in that: The phase-locked loop comprises: a second frequency divider; The second frequency divider is used to divide the first output clock signal by N to obtain a third output clock signal, wherein the third output clock signal is used to be output to a third mainboard, and N is an integer greater than or equal to 1.

5. The mainboard according to claim 4, characterized in that: The third output clock signal is input into the phase detector of the phase locked loop as a frequency feedback signal of the phase locked loop.

6. The mainboard according to claim 4, characterized in that: The first mainboard further includes at least one of the following: a second clock buffer, for buffering the third output clock signal output to the third mainboard; A filter is used to filter the third output clock signal output to the third mainboard.

7. A daughter card, characterized in that: The daughter card is used to connect to the first mainboard; The daughter card includes a clock source for generating a second clock source signal, and the second clock source signal is output to the first mainboard; The daughter card is used to receive the second output clock signal output by the first mainboard, wherein the second output clock signal is obtained by buffering the first output clock signal output by the phase-locked loop of the first mainboard through the first clock buffer of the first mainboard; wherein the input end of the phase-locked loop is connected to the output end of the selection switch of the first mainboard, and the output end of the selection switch is connected to one of the selected multiple input ends selected by the selection switch, wherein the multiple input ends of the selection switch are respectively used to input the first clock source signal and the second clock source signal, wherein the first clock source signal is generated by the clock source of the first mainboard.

8. The daughter card according to claim 7, characterized in that: One of the multiple input terminals of the selection switch is also used to input a third clock source signal, wherein the third clock source signal is generated by a clock source of the second mainboard.

9. The daughter card according to claim 7, characterized in that: The second output clock signal is obtained by buffering the first output clock signal output by the phase-locked loop through the first clock buffer of the first mainboard and dividing it by M through the first divider on the first mainboard, where M is an integer greater than or equal to 1.

10. An electronic device, characterized in that: The electronic device comprises at least one of the following: The mainboard according to any one of claims 1 to 6; The daughter card according to any one of claims 7 to 9.

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