Multilayer circuit board and manufacturing method thereof

Abstract

The invention discloses a multi-layer circuit board and a manufacturing method thereof. The manufacturing method comprises the steps of manufacturing and forming N sub-boards; a second prepreg is attached to the surface of one second inner conductive layer in the N-1 adjacent conductive groups through the first pin holes; a PET film is attached to the surface of the second prepreg, so that the PET film covers the second pin hole, and the first pin hole is exposed; pre-pressing a second prepreg and a PET film, then processing the PET film and the second prepreg by using laser, forming a blind hole in the second prepreg, and exposing a first conductive structure of a second inner conductive layer below the second prepreg; copper paste hole plugging and pre-curing are carried out on the blind hole, and then the PET film is removed; and through the second pin holes, all the daughter boards are stacked, pressed and molded to obtain the multi-layer circuit board. By adopting the technical scheme, the problems of poor reliability and low yield of the current manufacturing method can be solved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of circuit board manufacturing, and in particular to a multilayer circuit board and a manufacturing method thereof. BACKGROUND

[0002] An artificial intelligence (AI) backboard is a core hardware basis for constructing a large-scale AI computing system, mainly solving the high-speed interconnection problem between a high-performance graphics processing unit (GPU) cluster, and can realize a bandwidth of 900 GB / s, a delay 20 times lower than a peripheral component interconnect express (PCIe), and transmission of three 4K movies per second. The application scene training Conners' Continuous Performance Test 3rd Edition (CPT-3) in the past needs months, and now only takes a few weeks after realizing cluster interconnection using the AI backboard. The main functions of the AI backboard include eliminating communication bottlenecks, creating aggregated computing power, virtualizing super-large memory, accelerating distributed training, and constructing a scalable foundation.

[0003] The AI backboard is mainly a multilayer board composed of multiple sub-boards, forming a Z-axis interconnection core AI backboard. After the sub-boards are pressed into a mother board, the thickness of the mother board can reach 15 mm. According to the conventional process, the mother board needs to be drilled to form through holes for connecting different conductive layers, and the mother board needs to be processed. However, due to the thickness of the mother board, many processes cannot be realized. At present, the industry mainly fills the holes in the multiple sub-boards that need to realize all conductive layer conduction with resin, and then fills the holes with copper paste after electroplating. In this way, the sub-boards are pressed together to form a structure in which all conductive layers are in conduction. However, this implementation method is not mature in the industry, has poor reliability, and has a low yield. SUMMARY

[0004] The present application provides a multilayer circuit board and a manufacturing method thereof to solve the problem of poor reliability and low yield of the current manufacturing method.

[0005] According to an aspect of the present application, a manufacturing method of a multilayer circuit board is provided, comprising:

[0006] manufacturing and forming N sub-boards, wherein N is an integer greater than 1; the sub-boards include multiple core boards and first prepregs located between the core boards; the sub-boards further include multiple first pin holes and multiple second pin holes; of 2N first outer conductive layers of the N sub-boards, two are second outer conductive layers, and 2N-2 are second inner conductive layers; the 2N-2 second inner conductive layers constitute N-1 adjacent conductive groups;

[0007] Through the first pin hole, a second prepreg is attached to the surface of the second inner conductive layer in one of N-1 adjacent conductive groups; the second prepreg also includes a plurality of the first pin holes and a plurality of the second pin holes;

[0008] A PET film is laminated onto the surface of the second semi-cured sheet so that the PET film covers the second pin hole and exposes the first pin hole;

[0009] The second prepreg and the PET film are pre-pressed, and then the PET film and the second prepreg are processed by laser to form blind holes in the second prepreg to expose the first conductive structure of the second inner conductive layer located below the second prepreg;

[0010] The blind vias are plugged with copper paste, pre-cured, and then the PET film is removed.

[0011] All the sub-boards are stacked and pressed together through the second pin hole to obtain the multilayer circuit board.

[0012] Optionally, for the same sub-board, the distance from the first pin hole to the edge of the sub-board is less than the distance from the second pin hole to the edge of the sub-board.

[0013] Optionally, removing the PET film includes:

[0014] Position the PET film on the side of the second semi-cured sheet closest to the ground, and then peel off the PET film;

[0015] And / or, make the plane of the second semi-cured sheet intersect the plane of the ground, and peel the PET film away from the edge of the PET film away from the ground.

[0016] Optionally, N=3, the sub-board includes a first sub-board, a second sub-board and a third sub-board; of the two first outer conductive layers of the first sub-board, one is the second outer conductive layer and the other is the second inner conductive layer; of the two first outer conductive layers of the second sub-board, both are the second inner conductive layers; of the two first outer conductive layers of the third sub-board, one is the second outer conductive layer and the other is the second inner conductive layer.

[0017] To create and form N sub-boards, including:

[0018] Provide multiple core boards and multiple first prepreg sheets, fabricate and form the first inner layer circuitry of each of the sub-boards, fabricate and form multiple first pin holes, and then brown the first inner layer circuitry;

[0019] The core board and the first prepreg are stacked and pressed together through the first pin hole to obtain each of the sub-boards, and then a first outer layer circuit is formed on the first outer conductive layer of each of the sub-boards.

[0020] After the first outer layer circuit is formed, a plurality of second pin holes are made and formed. Then, the first outer layer circuit of the first sub-board and the third sub-board is browned, and the first outer layer circuit located on the second outer conductive layer is solder resisted.

[0021] Through the first pin hole, a second prepreg is attached to the surface of the second inner conductive layer in one of N-1 adjacent conductive groups, including:

[0022] The second prepreg is attached to the second inner conductive layer of the first sub-board and the second inner conductive layer of the third sub-board through the first pin hole.

[0023] Before stacking all the sub-boards through the second pin hole, the process further includes:

[0024] The first outer layer circuit of the second sub-board is browned.

[0025] Optionally, laser processing is used to process the PET film and the second prepreg to form blind holes in the second prepreg to expose the first conductive structure of the second inner conductive layer located beneath the second prepreg, including:

[0026] First, a carbon dioxide laser is used to process the PET film and the second prepreg, at least removing the PET film above the first conductive structure; then, an ultraviolet laser or a green laser is used to process the second prepreg, removing the second prepreg above the first conductive structure to form a blind hole.

[0027] Optionally, a PET film is laminated onto the surface of the second prepreg to cover the second pin hole and expose the first pin hole, including:

[0028] A full layer of PET film is laminated onto the surface of the second semi-cured sheet, and the PET film is cut using a frame cutter so that the PET film covers the second pin hole and exposes the first pin hole.

[0029] Optionally, before laminating all the sub-plates, the process further includes:

[0030] Dummy boards are placed above and / or below the stacked sub-boards.

[0031] Optionally, the multilayer circuit board is obtained by lamination and molding, including:

[0032] Using a drill bit, holes are drilled in the pressed motherboard to form pre-drilled holes;

[0033] Using a milling cutter, starting from the pre-drilled hole, the motherboard is milled to obtain the multilayer circuit board.

[0034] Optionally, a milling cutter is used to perform milling on the mother plate, starting from the pre-drilled hole, including:

[0035] Using the milling cutter, a first milling cut is performed starting from the pre-drilled hole, wherein the depth of the first milling cut is less than the thickness of the motherboard; then, using the milling cutter, a second milling cut is performed starting from the pre-drilled hole along the same path on the same side of the motherboard to form the multilayer circuit board.

[0036] According to another aspect of the present invention, a multilayer circuit board is provided, which is manufactured using the multilayer circuit board manufacturing method described in any of the above embodiments.

[0037] The technical solution of this invention facilitates alignment between multiple core boards within the sub-board by providing a first pin hole, and further facilitates alignment between multiple sub-boards by providing a second pin hole, ensuring the alignment accuracy of each conductive layer, improving product yield and reliability. By pre-pressing a second prepreg and PET film onto the surface of a portion of the second inner conductive layer to form blind vias, and then plugging these vias with copper paste, Z-axis interconnection between different sub-boards can be achieved. Furthermore, removing the PET film after copper paste pre-curing removes copper slag caused by copper paste plugging, eliminating the need for a water-filled horizontal line. Removing copper slag improves the reliability of the circuit board and prevents delamination during motherboard lamination. Simultaneously, the PET film adhered to the surface of the second prepreg covers the second pin hole, exposing the first pin hole. This protects the second pin hole from contamination, preventing copper paste from clogging it during subsequent filling and affecting alignment accuracy during motherboard lamination. It also ensures a smooth PET film 200 adhesion, preventing uneven adhesion and warping after lamination. Uneven adhesion could cause copper paste to be imprinted on the delamination / warping areas, resulting in short circuits, or insufficient filling of the holes during filling, leading to open circuits.

[0038] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0039] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0040] Figure 1 This is a flowchart illustrating a method for manufacturing a multilayer circuit board according to an embodiment of the present invention;

[0041] Figure 2 This is a structural schematic diagram of the fabrication process of a multilayer circuit board provided in an embodiment of the present invention;

[0042] Figure 3 This is a top view schematic diagram of a sub-board after bonding a second prepreg and a PET film according to an embodiment of the present invention;

[0043] Figure 4 This is a schematic diagram of a PET film removal process provided in an embodiment of the present invention;

[0044] Figure 5 This is a schematic diagram illustrating a process for removing a PET film according to an embodiment of the present invention.

[0045] Figure 6 This is a flowchart illustrating another method for manufacturing a multilayer circuit board according to an embodiment of the present invention.

[0046] Figure 7 This is a schematic diagram of the fabrication process of another multilayer circuit board provided in an embodiment of the present invention;

[0047] Figure 8 This is a schematic diagram of the structure of a frame-type cutting tool provided in an embodiment of the present invention;

[0048] Figure 9 This is a schematic diagram of a multilayer circuit board provided in an embodiment of the present invention. Detailed Implementation

[0049] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0050] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0051] Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without inventive effort are within the scope of protection of the present invention. The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings.

[0052] Figure 1 This is a flowchart illustrating a method for fabricating a multilayer circuit board according to an embodiment of the present invention. (Refer to...) Figure 1 The manufacturing methods for multilayer circuit boards include:

[0053] S110. Fabricate and form N sub-boards, where N is an integer greater than 1; the sub-board includes multiple core boards and a first prepreg located between the core boards; the sub-board also includes multiple first pin holes and multiple second pin holes; of the 2N first outer conductive layers of the N sub-boards, two are second outer conductive layers and 2N-2 are second inner conductive layers; the 2N-2 second inner conductive layers constitute N-1 adjacent conductive groups.

[0054] in, Figure 2 This is a structural schematic diagram of the fabrication process of a multilayer circuit board provided in an embodiment of the present invention, for reference. Figure 2 The sub-board 010 includes multiple core boards 110 and a first prepreg 121 located between the core boards 110; the sub-board 010 also includes multiple first pin holes PIH1 and multiple second pin holes PIH2. The first pin holes PIH1 are used to precisely position and mechanically fix the multiple core boards 110 and the first prepreg 121 before the sub-board 010 is pressed together, and are also used to precisely position and mechanically fix the sub-board 010 during the processing of the sub-board 010; the first pin holes PIH1 are used to precisely position and mechanically fix the multiple sub-boards 010 before the sub-board 010 is pressed together to form the motherboard, and are also used to precisely position and mechanically fix the motherboard during the processing of the motherboard.

[0055] Specifically, the sub-board 010 can be formed by laminating multiple core boards 110. Each core board 110 includes a substrate layer 111 and conductive layers 112 located on one side or opposite sides of the substrate layer 111. In one embodiment, the conductive layers 112 are copper layers. The conductive layer 112 located on the outer side of the sub-board 010 is a first outer conductive layer S1; the conductive layer 112 located on the inner side of the sub-board 010 is a first inner conductive layer S2. After all the sub-boards 010 are laminated into a mother board, the first outer conductive layer S1 located on the outer side of the mother board becomes a second outer conductive layer S3, and the first outer conductive layer S1 located inside the mother board becomes a second inner conductive layer S4. Adjacent conductive groups refer to two adjacent second inner conductive layers S4 after all the sub-boards 010 are laminated into a mother board. After lamination to form the mother board, a prepreg can be provided between two adjacent second inner conductive layers S4. In one embodiment, the sub-board 010 also includes conductive vias TH. For example, the conductive via TH can be made using a plated over filled via (POFV) process, and the aperture can be 0.175 mm.

[0056] S120. Through the first pin hole, a second prepreg is attached to the surface of a second inner conductive layer in one of N-1 adjacent conductive groups; the second prepreg also includes multiple first pin holes and multiple second pin holes.

[0057] For example, a complete multilayer circuit board includes seventy-eight conductive layers (LC1, ..., LC78) and three sub-boards 010, each including twenty-six conductive layers. From top to bottom, the first sub-board 011 may include the first to the twenty-sixth conductive layers (LC1, ..., LC26), the second sub-board 012 may include the twenty-seventh to the fifty-second conductive layers (LC27, ..., LC52), and the third sub-board 013 may include the fifty-third to the seventy-eighth conductive layers (LC53, ..., LC78). The first, twenty-sixth, twenty-seventh, fifty-twoth, fifty-threeth, and seventy-eighth conductive layers (LC1, LC26, LC27, LC52, LC53, and LC78) are all first outer conductive layers S1, and the remaining conductive layers are all first inner conductive layers S2; the first and seventy-eighth conductive layers (LC1 and LC78) are also second outer conductive layers S3, and the twenty-sixth, twenty-seventh, fifty-twoth, and fifty-threeth conductive layers (LC26, LC27, LC52, and LC53) are also second inner conductive layers S4; the twenty-sixth and twenty-seventh conductive layers (LC26 and LC27) form adjacent conductive groups, and the fifty-second and fifty-third conductive layers (LC52 and LC53) form adjacent conductive groups.

[0058] In an optional embodiment, a second prepreg 122 may be bonded to the surfaces of the 27th conductive layer LC27 (the second inner conductive layer S4 located above in the second sub-board 012) and the 53rd conductive layer LC53 (the second inner conductive layer S4 located above in the third sub-board 013).Figure 2 The image only shows, by way of example, the third sub-board 013 after the second prepreg 122 has been bonded together. Reference Figure 2 During the bonding process of the second prepreg 122, in order to achieve precise positioning and mechanical fixation, the third sub-board 013 can be placed on the pin base 420, so that the first pin 410 on the pin base 420 passes through the first pin hole PIH1 of the third sub-board 013 and the first pin hole PIH1 of the second prepreg 122. The second prepreg 122 is positioned differently from the first prepreg 121; the materials of the second prepreg 122 and the first prepreg 121 can be the same or different, and this embodiment of the invention does not limit this.

[0059] S130. PET film is laminated onto the surface of the second semi-cured sheet so that the PET film covers the second pin hole and exposes the first pin hole.

[0060] For example, continue to refer to Figure 2 In order to achieve precise positioning and mechanical fixation when bonding the PET film 200, the third sub-board 013 and the second semi-cured sheet 122 can be fixed using the pin base 420 and the first pin 410 during the bonding process. The PET film 200 is bonded to the surface of the second semi-cured sheet 122. The size of the PET film 200 is smaller than the size of the second semi-cured sheet 122. After bonding, the PET film 200 covers the second pin hole PIH2 and exposes the first pin hole PIH1.

[0061] By covering the second pin hole PIH2 with the PET film and exposing the first pin hole PIH1, the second pin hole PIH2 is protected from contamination, preventing copper paste from clogging it during subsequent hole plugging and affecting the alignment accuracy when the daughter board 010 is laminated to form the mother board. On the other hand, the PET film 200 is able to adhere smoothly, preventing uneven adhesion and warping after lamination, which could cause copper paste to be printed on the warped area, resulting in a short circuit, or the hole not being fully filled when plugging with copper paste, resulting in an open circuit.

[0062] S140, pre-press the second prepreg and the PET film, and then use laser processing on the PET film and the second prepreg to form blind holes in the second prepreg to expose the first conductive structure of the second inner conductive layer located below the second prepreg.

[0063] For example, a vacuum press or a pressure press can be used, with a set temperature of 130°C and a pressing time of 20 minutes, to pre-press the second semi-cured sheet 122 and the PET film 200 bonded to the second inner conductive layer S4 of the sub-board 010. During pre-pressing, aluminum sheets 310 can be placed above and below the sub-board 010. The aluminum sheets 310 can serve to equalize pressure, transfer heat, isolate, and protect. In addition, a PET film or silicone-free release film 320 larger than the sub-board 010 can be placed above the PET film 200 and between the aluminum sheets. The lamination structure during pre-pressing is as follows: Figure 2 As shown. The silicone-free release film 320 can prevent the aluminum sheet 310 from contacting the second prepreg 122 not covered by the PET film 200, which would cause difficulties in disassembly or forcibly disassemble the board and tear the second prepreg 122 into layers, rendering it unusable. Moreover, using a larger PET film or a silicone-free release film 320 can prevent silicone oil residue on the second prepreg 122 from causing delamination during the pressing of the motherboard when separating it from the second prepreg 122 not covered by the PET film 200.

[0064] After pre-pressing the second prepreg 122 and PET film 200 of the second inner conductive layer S4 bonded to the sub-board 010, holes can be drilled at preset positions using laser drilling to form blind holes BH in the second prepreg 122, exposing the first conductive structure of the second inner conductive layer S4 located below the second prepreg 122. The first conductive structure exposed by the blind hole BH can be a conductive line located in the second inner conductive layer S4, or it can be an electroplated cap of a conductive through-hole TH; this embodiment of the invention does not limit this.

[0065] S150. Fill the blind holes with copper paste, pre-cur them, and then remove the PET film.

[0066] For example, a screen printing process can be used to screen print copper paste 500 at the blind via BH location, thus plugging the blind via BH with copper paste and pre-curing the copper paste 500 in the blind via BH, and then removing the PET film 200. Removing the PET film after the copper paste 500 has pre-cured removes copper slag outside the blind via BH area, avoiding copper slag residue outside the blind via BH that could cause short circuits. Moreover, removing copper slag by removing the PET film eliminates the need to cross any water-containing horizontal lines, preventing delamination during motherboard lamination and improving the reliability of the finished product.

[0067] In an optional embodiment, after the copper paste 500 in the blind via BH is pre-cured, an automated optical inspection (AOI) device can be used to scan the copper paste 500 and the second prepreg 122 on the surface of the sub-board 010 to detect whether the copper paste 500 is full and whether there is copper slag remaining on the surface of the second prepreg 122.

[0068] S160. Through the second pin hole, all sub-boards are stacked, pressed, and shaped to obtain a multi-layer circuit board.

[0069] For example, all sub-boards 010 can be placed in the pin base in a preset order. Figure 2 (Not shown in the image) The second pin on the pin base passes through the second pin hole PIH2 of each sub-board 010 to achieve precise alignment of the sub-board 010. Then, all sub-boards 010 are pressed together to form a motherboard. During pressing, the second inner conductive layer S4 with the second prepreg 122 attached can be bonded to another second inner conductive layer S4 in the same adjacent conductive group through the second prepreg 122. This allows the first conductive structure of the second inner conductive layer S4 located below the second prepreg 122 to be electrically connected to the second conductive structure of the second inner conductive layer S4 in the same adjacent conductive group through the copper paste of the blind via BH, thereby achieving Z-axis interconnection between different sub-boards 010.

[0070] In an optional embodiment, before laminating all the sub-boards 010, a dummy board 340 is placed above and / or below the stacked sub-boards 010. In one embodiment, the dummy board 340 includes a prepreg and copper foil disposed on one or opposite sides of the prepreg; in another embodiment, the dummy board 340 includes a core board, which may include a substrate layer and copper foil disposed on one or opposite sides of the substrate layer. Placing the dummy board 340 during lamination to form the mother board helps to reduce the heating rate during lamination, reduce thermal stress, avoid board warping and deformation, and also helps to improve the covering effect, resulting in sufficient connection between the sub-boards 010.

[0071] In addition, during the pressing process to form the master plate, aluminum sheets 310, release film 320', steel plate 330, and kraft paper 350 (25-30 sheets) can be placed above and / or below the stacked sub-plates 010, as well as a press pad 361 at the bottom and a press cover plate 362 at the top of the stacked sub-plates 010. The stacking structure during pressing is as follows: Figure 2 As shown. Among them, the release film 320' can be a high-temperature release film.

[0072] After the motherboard is laminated, it can be milled according to the positioning holes of the daughterboard to remove the useless material on the motherboard, and finally obtain the multilayer circuit board provided in the embodiment of the present invention. In one embodiment, after the motherboard is laminated, before milling the motherboard, the conductive lines on the surface of the motherboard can be subjected to electroless gold treatment to improve reliability and solderability.

[0073] In an optional embodiment, among the plurality of sub-boards 010 provided in S110, the first inner conductive layer S2 located inside the sub-board 010 has been fabricated and formed with conductive lines, the second inner conductive layer S4 (the first outer conductive layer S1 located inside the motherboard) has been fabricated and formed with conductive lines, and the second outer conductive layer S3 (the first outer conductive layer S1 located outside the motherboard) has not yet been fabricated and formed with conductive lines, in order to avoid short circuits or open circuits in the conductive lines of the second outer conductive layer S3 during the processing of the sub-board 010. Conductive lines can be fabricated and formed in the second outer conductive layer S3 after S160.

[0074] In another optional embodiment, among the multiple sub-boards 010 provided in S110, all the first outer conductive layers S1 and the first inner conductive layers S2 of the sub-board 010 have been fabricated and formed into conductive lines, that is, the second inner conductive layer S4 (the first outer conductive layer S1 located inside the motherboard) and the second outer conductive layer S3 (the first outer conductive layer S1 located outside the motherboard) have been fabricated and formed into conductive lines. At the same time, the conductive lines of the second outer conductive layer S3 have been surface-processed to protect the conductive lines of the second outer conductive layer S3 from damage.

[0075] In this embodiment of the invention, by providing first pin holes on the sub-board, alignment between multiple core boards within the sub-board is facilitated; by providing second pin holes on the sub-board, alignment between multiple sub-boards is further facilitated, ensuring the alignment accuracy of each conductive layer and improving product yield and reliability. By pre-pressing a second prepreg and PET film onto the surface of a portion of the second inner conductive layer to form blind vias, and then plugging these vias with copper paste, Z-axis interconnection between different sub-boards can be achieved. Furthermore, by removing the PET film after copper paste pre-curing, copper slag caused by copper paste plugging can be removed, eliminating the need for a water-filled horizontal line. Removing copper slag helps improve the reliability of the circuit board and avoids delamination during motherboard lamination. At the same time, the PET film adhered to the surface of the second prepreg covers the second pin hole, exposing the first pin hole. This protects the second pin hole from contamination and prevents copper paste from clogging it during subsequent filling, which would affect the alignment accuracy when the motherboard is formed. It also ensures that the PET film 200 is applied smoothly, preventing uneven application and warping after lamination. This would cause copper paste to be printed on the delamination and warping areas, resulting in short circuits, or the copper paste filling the holes would be incomplete, causing open circuits.

[0076] Optional, Figure 3 This is a top view schematic diagram of a sub-board after bonding the second prepreg and the PET film according to an embodiment of the present invention, for reference. Figure 3 For the same sub-board 010, the distance L1 between the first pin hole PIH1 and the edge of the sub-board 010 is less than the distance L2 between the second pin hole PIH2 and the edge of the sub-board 010.

[0077] For example, the size of the second prepreg 122 is the same as the size of the sub-board 010, and the plurality of first pin holes PIH1 of the second prepreg 122 are correspondingly set with the plurality of first pin holes PIH1 of the sub-board 010, and the plurality of second pin holes PIH2 of the second prepreg 122 are correspondingly set with the plurality of second pin holes PIH2 of the sub-board 010. At this time, the edge of the second prepreg 122 is the edge of the sub-board 010, the position of the first pin hole PIH1 of the second prepreg 122 is the position of the first pin hole PIH1 of the sub-board 010, and the position of the second pin hole PIH2 of the second prepreg 122 is the position of the second pin hole PIH2 of the sub-board 010.

[0078] The distance L1 between the first pin hole PIH1 and the edge of the sub-plate 010 is less than the distance L3 between the PET film 200 and the edge of the sub-plate 010, and the distance L3 between the PET film 200 and the edge of the sub-plate 010 is less than the distance L2 between the second pin hole PIH2 and the edge of the sub-plate 010. This allows the PET film 200 to cover the second pin hole PIH2, exposing the first pin hole PIH1. In one embodiment, the distance between the second pin hole PIH2 and the edge of the sub-plate 010 is within 0.1-0.5 inches, and the distance between the PET film 200 and the edge of the sub-plate 010 is within 0.05-0.45 inches.

[0079] Optionally, the thickness of the PET film 200 is 20-50 micrometers (μm), which allows the copper paste 500 in the blind via BH to be 20-50 μm higher than the second prepreg 122 after the PET film 200 is subsequently removed. This ensures reliable connection of the upper and lower conductive lines of the second prepreg 122, preventing the PET film 200 from being too thin, which would result in the copper paste 500 in the blind via BH being too little higher than the second prepreg 122 after the PET film 200 is removed, causing the copper paste 500 in the blind via BH to fail to weld to the second conductive junction during motherboard lamination. It also prevents the PET film 200 from being too thick, which would result in the copper paste 500 in the blind via BH being too much higher than the second prepreg 122, making delamination easy during lamination.

[0080] Optional, Figure 4 This is a schematic diagram of a PET film removal process provided in an embodiment of the present invention. Figure 5 This is a schematic diagram illustrating a practical procedure for removing a PET film according to an embodiment of the present invention. (Refer to...) Figure 4 and Figure 5 Removing the PET film includes: positioning the PET film 200 on the side of the second precured sheet 122 closest to the ground, and tearing the PET film 200 away; and / or, positioning the plane of the second precured sheet 122 intersecting the plane of the ground, and tearing the PET film 200 away from the edge of the PET film 200 away from the ground.

[0081] For example, when removing the PET film 200, the second semi-cured sheet 122 to which the sub-board 010 is attached can be tilted downwards, and the PET film 200 can be peeled off starting from the higher edge of the PET film 200 on the side away from the ground. In this way, copper dross from the screen printing copper paste 500 can be removed by peeling off the PET film 200, and copper dross can be prevented from falling onto the second semi-cured sheet 122 and causing a short circuit.

[0082] Optionally, N=3, and sub-board 010 includes a first sub-board 011, a second sub-board 012, and a third sub-board 013; of the two first outer conductive layers S1 of the first sub-board 011, one is a second outer conductive layer S3 and the other is a second inner conductive layer S4; of the two first outer conductive layers S1 of the second sub-board 012, both are second inner conductive layers S4; of the two first outer conductive layers S1 of the third sub-board 013, one is a second outer conductive layer S3 and the other is a second inner conductive layer S4. Figure 6 This is a flowchart illustrating another method for fabricating a multilayer circuit board according to an embodiment of the present invention. (Refer to...) Figure 6 The manufacturing methods for multilayer circuit boards include:

[0083] S210: Provide multiple core boards and multiple first prepregs, fabricate and form the first inner layer circuitry of each sub-board, fabricate and form multiple first pin holes, and then brown the first inner layer circuitry.

[0084] Specifically, the first inner conductive layer S2 of the core board 110 (the conductive layer 112 located inside the sub-board 010 after lamination) is patterned to form the first inner layer circuit. In this step, the first outer conductive layer S1 of the core board 110 (the conductive layer 112 located outside the sub-board 010 after lamination) has not yet been fabricated and formed into conductive circuit.

[0085] S220. The core board and the first prepreg are stacked and pressed together through the first pin hole to obtain each sub-board. Then, the first outer layer circuit is formed on the first outer conductive layer of each sub-board.

[0086] For example, when the core board 110 and the first prepreg 121 are stacked, the first pins can be passed through the first pin holes PIH1 of each core board 110 to align the core boards 110 and press them together to obtain the first sub-board 011, the second sub-board 012 and the third sub-board 013. Then, the first outer conductive layer S1 of the first sub-board 011, the second sub-board 012 and the third sub-board 013 is used to make and form conductive lines, which are the first outer layer lines.

[0087] Figure 7 This is a structural schematic diagram of another multilayer circuit board fabrication process provided by an embodiment of the present invention, as shown below. Figure 7As shown, this step involves processing all the first outer conductive layers S1 to form the first outer layer circuitry, that is, fabricating and forming conductive circuitry on the second outer conductive layer S3 and the second inner conductive layer S4. Taking a complete multilayer circuit board including seventy-eight conductive layers (LC1, ..., LC78), and each sub-board 010 including twenty-six conductive layers as an example, this step involves fabricating and forming conductive circuitry on the first, twenty-sixth, twenty-seventh, fifty-twoth, fifty-threeth, and seventy-eighth conductive layers (LC1, LC26, LC27, LC52, LC53, LC78).

[0088] In an alternative implementation, prior to forming the first outer layer circuitry, a POFV process can be employed: drilling, copper plating, electroplating, resin plugging, and electroplating to form conductive vias (TH).

[0089] S230. After forming the first outer layer circuit, multiple second pin holes are made and formed. Then, the first outer layer circuit of the first sub-board and the third sub-board is browned, and the first outer layer circuit located on the second outer conductive layer is solder resisted.

[0090] For example, continuing with a complete multilayer circuit board including seventy-eight conductive layers (LC1, ..., LC78), and each sub-board 010 including twenty-six conductive layers, in this step, only the first, twenty-sixth, fifty-third, and seventy-eighth conductive layers (LC1, LC26, LC53, LC78) are browned, and then only the first and seventy-eighth conductive layers (LC1, LC78) are solder resisted. The solder resist treatment can protect the first conductive layer LC1 and the seventy-eighth conductive layer LC78 from damage during the motherboard lamination process.

[0091] S240. Through the first pin hole, the second semi-cured sheet is attached to the second inner conductive layer of the first sub-board and the second inner conductive layer of the third sub-board respectively.

[0092] For example, continuing with a complete multilayer circuit board including seventy-eight conductive layers (LC1, ..., LC78), and each sub-board 010 including twenty-six conductive layers, in this step, the second prepreg 122 is attached to the twenty-sixth conductive layer LC26 and the fifty-third conductive layer LC78 respectively, which can protect the browning of the twenty-sixth conductive layer LC26 and the fifty-third conductive layer LC78 and avoid browning timeout.

[0093] S250, PET film is laminated onto the surface of the second semi-cured sheet so that the PET film covers the second pin hole and exposes the first pin hole.

[0094] S260, pre-press the second prepreg and the PET film, and then use laser processing on the PET film and the second prepreg to form blind holes in the second prepreg to expose the first conductive structure of the second inner conductive layer located below the second prepreg.

[0095] S270. Fill the blind holes with copper paste, pre-cur them, and then remove the PET film.

[0096] S280. The first outer layer circuit of the second sub-board is browned. All sub-boards are stacked and pressed together through the second pin hole to obtain a multilayer circuit board.

[0097] For example, continuing with a complete multilayer circuit board including seventy-eight conductive layers (LC1, ..., LC78), and each sub-board 010 including twenty-six conductive layers, in the step, before stacking all the sub-boards 010, the twenty-seventh conductive layer LC27 and the fifty-second conductive layer LC52 need to be browned. Browning the first outer layer circuit of the second sub-board 012 after processing the second prepreg 122 and PET film 200 can ensure the timeliness of browning and avoid the browning of the second sub-board 012 from exceeding the time limit.

[0098] In this embodiment of the invention, the first outer layer circuitry is formed after lamination to form the sub-board. This avoids damage to the first outer layer circuitry during the sub-board lamination process and also prevents the first outer layer circuitry from undergoing multiple laminations. After the first outer layer circuitry is formed, the first outer layer circuitry on the first and third sub-boards is browned, and solder resist treatment is applied to the first outer layer circuitry located on the second outer conductive layer. A second prepreg is then attached to the surface of the first outer layer circuitry located on the second inner conductive layer. Finally, the first outer layer circuitry on the second sub-board is browned again before the motherboard lamination. This ensures the timeliness of the browning process, avoids excessive exposure time after browning of the first outer layer circuitry, which would affect the browning effect, and also protects the first outer layer circuitry on the second outer conductive layer, preventing damage during the motherboard lamination process.

[0099] Optionally, laser processing is used to process the PET film 200 and the second prepreg 122 to form a blind hole BH in the second prepreg 122 to expose the first conductive structure of the second inner conductive layer S4 located below the second prepreg 122. This includes: firstly processing the PET film 200 and the second prepreg 122 with a carbon dioxide laser to remove at least the PET film 200 above the first conductive structure; then processing the second prepreg 122 with an ultraviolet laser or a green laser to remove the second prepreg 122 above the first conductive structure and form the blind hole BH.

[0100] For example, after pre-pressing the PET film 200 and the second prepreg 122, laser lithography can be performed on the second prepreg 122 and the PET film 200 above the conductive via TH. For example, since the PET film 200 has a low melting point, a 10000nm CO2 laser can be used to lithography the PET film 200, which is less likely to produce char residue. The CO2 laser can also remove part of the second prepreg 122. When approaching the first conductive structure below the second prepreg 122, a 10-400nm ultraviolet laser or a 500nm green laser can be used to remove the remaining second prepreg 122 at that location for adhesive removal. This can also remove 0.5-1.5μm of the first conductive structure, ensuring that there is no adhesive residue at the bottom of the blind via BH.

[0101] By first using a long-wavelength laser and then a short-wavelength laser, the PET film 200 can be ablated. This prevents debris from the PET film 20 from affecting copper paste pouring and causing poor electrical performance. It also prevents residual adhesive at the bottom of the blind via (BH) from causing laser-induced coupling damage (ICD). Moreover, the blind via (BH) formed by this method is free of debris and residual adhesive. It does not require passing through any water level or plasma, effectively avoiding functional defects such as delamination and board bursting that may occur after laser plating.

[0102] Optional, Figure 8 This is a schematic diagram of the structure of a frame-type cutting tool provided in an embodiment of the present invention, for reference. Figure 8 The process of laminating a PET film 200 onto the surface of the second prepreg 122 to cover the second pin hole PIH2 and expose the first pin hole PIH1 includes: laminating a full layer of PET film 200 onto the surface of the second prepreg 122, and cutting the PET film 200 using a frame cutter 600 to cover the second pin hole PIH2 and expose the first pin hole PIH1.

[0103] The frame-type cutter 600 includes multiple blades 610 that can form a frame structure, allowing for a single cut of the PET film 200 without the need for multiple cuts. In one embodiment, the frame-type cutter 600 also includes a handle 620 connected to the blades 610.

[0104] For example, a full layer of PET film 200 can be first bonded to the surface of the second prepreg 122. At this time, the PET film 200 can cover the first pin hole PIH1 and the entire second prepreg 122, making the bonding of the PET film 200 convenient, effective, safe and quick, and without contaminating the PET film 200. Then, a special, precision frame cutter 600 can be used to cut away the part covering the first pin hole PIH1 in one go, which can prevent the PET film 200 from lifting, affecting the copper paste pouring quality, and causing poor electrical performance.

[0105] Optionally, the pressing and forming process to obtain a multilayer circuit board includes: using a drill bit to drill holes in the pressed motherboard to form pre-drilled holes; and using a milling cutter to perform milling on the motherboard starting from the pre-drilled holes to obtain a multilayer circuit board.

[0106] For example, the entry point of the milling cutter can be determined first. A pre-drilled hole with a diameter of 3.2 mm can be drilled using a drill bit, and the drill chips can be removed. Then, a special milling cutter with a cutting edge length greater than the thickness of the motherboard and a diameter less than 3.2 mm, such as 3.175 mm, can be used to perform milling on the motherboard from the pre-drilled hole along a preset path to remove useless material from the motherboard, ultimately obtaining the multilayer circuit board provided in this embodiment of the invention. This prevents the milling cutter from breaking.

[0107] In an alternative implementation, the cutting edge of the drill bit is greater than or equal to half the thickness of the mother plate, which can remove some of the waste chips before the milling cutter cuts, thus preventing the milling cutter from breaking.

[0108] Based on the above embodiments, a milling cutter is used to perform milling on the motherboard, starting from the pre-drilled hole. This includes: using a milling cutter to perform a first milling cut starting from the pre-drilled hole, wherein the depth of the first milling cut is less than the thickness of the motherboard; and then using a milling cutter to perform a second milling cut along the same path on the same side of the motherboard, starting from the pre-drilled hole, to form a multilayer circuit board.

[0109] Specifically, two milling cuts are performed from the same side of the motherboard along the same path. In one embodiment, the depth of the first milling cut is less than the thickness of the motherboard and greater than or equal to half the thickness of the motherboard.

[0110] For example, a depth-controlled milling cutter can be used. The first cut is half the thickness of the motherboard. The cutter is then moved horizontally along a preset path until it returns to the starting point. Then, without moving or flipping the motherboard, the cutter is used again to mill through the motherboard a second time, moving horizontally along the preset path until it returns to the starting point. This removes the unusable material from the motherboard, resulting in the multilayer circuit board provided in this embodiment of the invention. This avoids the spindle jamming caused by the depth-controlled milling cutter cutting too deeply in one go.

[0111] Based on the same inventive concept, embodiments of the present invention also provide a multilayer circuit board. Figure 9 This is a schematic diagram of a multilayer circuit board provided in an embodiment of the present invention, such as... Figure 9 As shown, different sub-boards 010 can be bonded together by the second prepreg 122, and the conductive structure between different sub-boards 010 can be welded by copper paste 500.

[0112] The multilayer circuit board provided in the embodiments of the present invention can be manufactured using the manufacturing method of the multilayer circuit board provided in any embodiment of the present invention. It has the functional modules and beneficial effects of the manufacturing method of the multilayer circuit board provided in the embodiments of the present invention. For contents not described in detail in the embodiments of the multilayer circuit board, please refer to the description of the manufacturing method of the multilayer circuit board above, and will not be repeated here. Similarly, the manufacturing method of the multilayer circuit board provided in the embodiments of the present invention can be used to manufacture the multilayer circuit board provided in any embodiment of the present invention. It has the corresponding technical features and beneficial effects of the multilayer circuit board. For contents not described in detail in the embodiments of the manufacturing method of the multilayer circuit board, please refer to the description of the multilayer circuit board above, and will not be repeated here.

[0113] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, the scope of which is determined by the scope of the appended claims.

Claims

1. A method for manufacturing a multilayer circuit board, characterized in that, include: N sub-boards are fabricated and formed, where N is an integer greater than 1; each sub-board includes multiple core boards and a first prepreg located between the core boards; each sub-board also includes multiple first pin holes and multiple second pin holes; of the 2N first outer conductive layers of the N sub-boards, two are second outer conductive layers and 2N-2 are second inner conductive layers; the 2N-2 second inner conductive layers constitute N-1 adjacent conductive groups; Through the first pin hole, a second prepreg is attached to the surface of the second inner conductive layer in one of N-1 adjacent conductive groups; the second prepreg also includes a plurality of the first pin holes and a plurality of the second pin holes; A PET film is laminated onto the surface of the second semi-cured sheet so that the PET film covers the second pin hole and exposes the first pin hole; The second prepreg and the PET film are pre-pressed, and then the PET film and the second prepreg are processed by laser to form blind holes in the second prepreg to expose the first conductive structure of the second inner conductive layer located below the second prepreg; The blind vias are plugged with copper paste, pre-cured, and then the PET film is removed. All the sub-boards are stacked and pressed together through the second pin hole to obtain the multilayer circuit board.

2. The method for manufacturing a multilayer circuit board according to claim 1, characterized in that, For the same sub-board, the distance from the first pin hole to the edge of the sub-board is less than the distance from the second pin hole to the edge of the sub-board.

3. The method for manufacturing a multilayer circuit board according to claim 1, characterized in that, Removing the PET film includes: Position the PET film on the side of the second semi-cured sheet closest to the ground, and then peel off the PET film; And / or, make the plane of the second semi-cured sheet intersect the plane of the ground, and peel the PET film away from the edge of the PET film away from the ground.

4. The method for manufacturing a multilayer circuit board according to claim 1, characterized in that, N=3, the sub-board includes a first sub-board, a second sub-board and a third sub-board; of the two first outer conductive layers of the first sub-board, one is the second outer conductive layer and the other is the second inner conductive layer; of the two first outer conductive layers of the second sub-board, both are the second inner conductive layers; of the two first outer conductive layers of the third sub-board, one is the second outer conductive layer and the other is the second inner conductive layer. The process involves creating and forming N sub-boards, including: Provide multiple core boards and multiple first prepreg sheets, fabricate and form the first inner layer circuitry of each of the sub-boards, fabricate and form multiple first pin holes, and then brown the first inner layer circuitry; The core board and the first prepreg are stacked and pressed together through the first pin hole to obtain each of the sub-boards, and then a first outer layer circuit is formed on the first outer conductive layer of each of the sub-boards. After the first outer layer circuit is formed, a plurality of second pin holes are made and formed. Then, the first outer layer circuit of the first sub-board and the third sub-board is browned, and the first outer layer circuit located on the second outer conductive layer is solder resisted. Through the first pin hole, a second prepreg is attached to the surface of the second inner conductive layer in one of N-1 adjacent conductive groups, including: The second prepreg is attached to the second inner conductive layer of the first sub-board and the second inner conductive layer of the third sub-board through the first pin hole. Before stacking all the sub-boards through the second pin hole, the process further includes: The first outer layer circuit of the second sub-board is browned.

5. The method for manufacturing a multilayer circuit board according to claim 1, characterized in that, Laser processing is used to process the PET film and the second prepreg, forming blind holes in the second prepreg to expose a first conductive structure of the second inner conductive layer located beneath the second prepreg, including: First, a carbon dioxide laser is used to process the PET film and the second prepreg, at least removing the PET film above the first conductive structure; then, an ultraviolet laser or a green laser is used to process the second prepreg, removing the second prepreg above the first conductive structure to form a blind hole.

6. The method for manufacturing a multilayer circuit board according to claim 1, characterized in that, A PET film is laminated onto the surface of the second prepreg to cover the second pin hole and expose the first pin hole, including: A full layer of PET film is laminated onto the surface of the second semi-cured sheet, and the PET film is cut using a frame cutter so that the PET film covers the second pin hole and exposes the first pin hole.

7. The method for manufacturing a multilayer circuit board according to claim 1, characterized in that, Before all the sub-plates are pressed together, the following is also included: Dummy boards are placed above and / or below the stacked sub-boards.

8. The method for manufacturing a multilayer circuit board according to claim 1, characterized in that, The multilayer circuit board is obtained by lamination and molding, including: Using a drill bit, holes are drilled in the pressed motherboard to form pre-drilled holes; Using a milling cutter, starting from the pre-drilled hole, the motherboard is milled to obtain the multilayer circuit board.

9. The method for manufacturing a multilayer circuit board according to claim 8, characterized in that, Using a milling cutter, the motherboard is milled starting from the pre-drilled hole, including: Using the milling cutter, a first milling cut is performed starting from the pre-drilled hole, wherein the depth of the first milling cut is less than the thickness of the motherboard; then, using the milling cutter, a second milling cut is performed starting from the pre-drilled hole along the same path on the same side of the motherboard to form the multilayer circuit board.

10. A multilayer circuit board, characterized in that, The multilayer circuit board is manufactured using the method described in any one of claims 1-9.

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