DPRAM multiplexing circuit based on EMIF bus

Abstract

The utility model discloses a DPRAM multiplexing circuit based on an EMIF bus, comprising a main control chip, the main control chip is connected with a plurality of DPRAM chips, and each DPRAM chip is connected with an inverter chip; an address line pin of each DPRAM chip is connected with an EMIF address bus pin of the main control chip, and an I / O data line pin of each DPRAM chip is connected with a data bus pin of the main control chip; a read enable receiving pin, a write enable receiving pin, a high enable receiving pin and a low enable receiving pin of each DPRAM chip are respectively connected to a read enable control pin, a write enable control pin, a high enable control pin and a low enable control pin of the main control chip; the second chip selection enabling receiving pin of each DPRAM chip is connected to the output pin of the corresponding inverter chip, and the first chip selection enabling receiving pin of each DPRAM chip and the input pin of the corresponding inverter chip are connected to the correspondingly distributed chip selection enabling control pin in the main control chip. According to the utility model, the purpose of multiplexing a plurality of DPRAMs on one bus can be achieved.

Description

Technical Field

[0001] The utility model relates to the field of circuit design, and more specifically to a DPRAM multiplexing circuit based on an EMIF bus. Background Art

[0002] With the rapid development of computer technology, high-speed and stable data transmission has become a key part of information products. Dual-Port RAM (DPRAM) has two independent interfaces and can read and write from two different address spaces. This makes DPRAM very suitable for application scenarios that require high-speed data transmission and processing. With the development of communication technology, a main control chip (DSP / CPU) often needs to mount multiple DPRAMs, but due to the limited chip pin resources, the number of DPRAMs that can be mounted is limited, which cannot meet the demand for mounting multiple DPRAMs. Utility Model Content

[0003] In order to overcome the deficiencies in the prior art, the utility model proposes a hardware circuit, namely, a DPRAM multiplexing circuit based on an EMIF bus, which can achieve the purpose of multiplexing multiple DPRAMs on one bus.

[0004] The purpose of the utility model is achieved through the following technical solutions.

[0005] The utility model is a DPRAM multiplexing circuit based on an EMIF bus, comprising a main control chip, wherein the main control chip is connected to a plurality of DPRAM chips, and each of the DPRAM chips is connected to an inverter chip;

[0006] The address line pins of each DPRAM chip are connected to the EMIF address bus pins of the main control chip, the I / O data line pins of each DPRAM chip are connected to the data bus pins of the main control chip, the read enable receiving pin, write enable receiving pin, high enable receiving pin, and low enable receiving pin of each DPRAM chip are respectively connected to the read enable control pin, write enable control pin, high enable control pin, and low enable control pin of the main control chip, and the SEMR enable pin of each DPRAM chip is connected to a 3.3V power supply;

[0007] The second chip select enable receiving pin of each DPRAM chip is connected to the output pin of the corresponding inverter chip, and the first chip select enable receiving pin of each DPRAM chip and the input pin of the corresponding inverter chip are connected to the chip select enable control pin correspondingly allocated to each DPRAM chip in the master chip.

[0008] Furthermore, the main control chip adopts a DSP chip.

[0009] Furthermore, the number of DPRAM chips connected to the main control chip is equal to the number of chip select enable control pins of the main control chip, and each DPRAM chip corresponds to an inverter chip.

[0010] Furthermore, the low enable control pin, high enable control pin, write enable control pin, and read enable control pin of the master control chip are respectively connected to the low enable receiving pin, high enable receiving pin, write enable receiving pin, and read enable receiving pin of each DPRAM chip through a resistor, and all chip select enable control pins of the master control chip are respectively connected to the first chip select enable receiving pin of each corresponding DPRAM chip through a resistor.

[0011] Furthermore, the ground pin of each inverter chip is grounded, and the power pin is connected to a 3.3V power supply.

[0012] Furthermore, the SEMR enable pin of each of the DPRAM chips is connected to a 3.3V power supply via a 10K resistor.

[0013] Compared with the prior art, the beneficial effects brought about by the technical solution of the utility model are:

[0014] (1) In the present invention, the address line pins of multiple DPRAM chips are connected to the EMIF address bus pins of the master chip, and the I / O data line pins of multiple DPRAM chips are connected to the data bus pins of the master chip U6B. This connection method reuses the data bus and address bus of multiple DPRAM chips, saving the pin resources of the master chip. The master chip can control the DPRAM enable based on the chip select signal, so that the read and write operations of multiple DPRAMs do not conflict when in use, achieving the purpose of multiplexing multiple DPRAM chips by one master chip.

[0015] (2) The EMIF bus selected in the utility model has corresponding resources for most main control chips (CPU / DSP) on the market, with a wide range of application scenarios and few restrictions on use. The digital signal processor (DSP) reuses multiple dual-port storage memories (DPRAM), which has many advantages and good effects in the field of data communication. By using multiple DPRAMs, multiple data can be processed in parallel, speeding up the reading and writing of data and improving computing efficiency.

[0016] (3) The redundant design of the present invention in multiple DPRAM designs can improve system stability. When a DPRAM fails, other DPRAMs can take over the work, ensuring continuous and stable operation of the system and enhancing the overall reliability of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1It is the schematic diagram of the dual DPRAM multiplexing circuit design.

[0018] Figure 2 It is a schematic diagram of the design principle of multiple DPRAM multiplexing circuit. DETAILED DESCRIPTION

[0019] The utility model is further described below in conjunction with the accompanying drawings.

[0020] The utility model is based on the EMIF bus DPRAM multiplexing circuit, mainly including a main control chip U6B, a DPRAM chip, an inverter chip, etc. The main control chip U6B is connected to multiple DPRAM chips, and each of the DPRAM chips is connected to an inverter chip. Preferably, each DPRAM chip corresponds to an inverter chip, and the number of DPRAM chips connected to the main control chip U6B can be at most equal to the number of chip select enable control pins of the main control chip, for example Figure 1 As shown, the control chip U6B has five chip select enable control pins EMA_CS[1], EMA_CS[2], EMA_CS[3], EMA_CS[4], and EMA_CS[5]. At this time, up to five DPRAM chips can be connected. Only two DPRAM chips (U7B and U9B) and two inverter chips (U8 and U10) are shown in the figure, and the same applies.

[0021] The main control chip U6B can be a DSP chip for controlling the reading and writing of DPRAM for high-speed data transmission. The DSP chip model can be TMS320C6748BZWT4, etc., with an operating frequency of 275MHz and 456Mhz, a core voltage of 1.3V, and an I / O voltage of 1.8V or 3.3V.

[0022] The DPRAM chip, i.e., dual-port random access memory register (Dual-Port RAM), is a special memory, and its key feature is its "ping-pong" function, i.e., each port has its own data bus and control signal, and independently accesses the data in the memory without interfering with each other. The DPRAM chip model can be 70V28LA5PFG, and the selected DPRAM chip has a chip select control signal, which is used for the main control chip U6B to control access to different DPRAM chips.

[0023] The inverter chip model can be SN74LVC1G14DCKR, which is a single inverter with Schmitt trigger input, an operating voltage of 1.65-5.5V, an input accepting voltage of up to 5.5V, a maximum propagation delay time of 4.6ns at 3.3V, low power consumption, a maximum ICC of 10μm, and provides ±24M output drive at 3.3V.

[0024] The address line pins of each DPRAM chip are connected to the EMIF address bus pins of the main control chip, the I / O data line pins of each DPRAM chip are connected to the data bus pins of the main control chip U6B, the read enable receiving pin 59, write enable receiving pin 60, high enable receiving pin 65, and low enable receiving pin 66 of each DPRAM chip are respectively connected to the read enable control pin B15, write enable control pin B9, high enable control pin A5, and low enable control pin C8 of the main control chip U6B, and the SEMR enable pin 62 of each DPRAM chip is connected to the 10K resistor (such as Figure 1 R15, R16) are connected to the 3.3V power supply VCC.

[0025] The second chip select enable receiving pin 63 of each DPRAM chip is connected to the output pin 4 of the corresponding inverter chip, for example Figure 1 The second chip select enable receiving pin 63 of the DPRAM chip U7B is connected to the output pin 4 of the inverter chip U8, and the second chip select enable receiving pin 63 of the DPRAM chip U9B is connected to the output pin 4 of the inverter chip U10. The first chip select enable receiving pin 64 of each DPRAM chip and the input pin 2 of the corresponding inverter chip are connected to the chip select enable control pin corresponding to each DPRAM chip in the master chip U6B. For example Figure 1 The first chip select enable receiving pin 64 of the DPRAM chip U7B and the input pin 2 of the inverter chip U8 are both connected to the chip select enable control pin EMA_CS[1] of the main control chip U6B, the first chip select enable receiving pin 64 of the DPRAM chip U9B and the input pin 2 of the inverter chip U10 are both connected to the chip select enable control pin EMA_CS[2] of the main control chip U6B, and the chip select enable control pins EMA_CS[3], EMA_CS[4], and EMA_CS[5] of the main control chip U6B can be connected to other DPRAM chips and inverter chips in the same way. In addition, the ground pin 3 of each inverter chip is grounded GND, and the power pin 5 is connected to the 3.3V power supply VCC. The inverted signal output by each inverter chip works simultaneously with the chip select signal of the main control chip U6B to meet the enable signal timing logic of the corresponding DPRAM chip.

[0026] In the above circuit, preferably, the low enable control pin C8, high enable control pin A5, write enable control pin B9, and read enable control pin B15 of the main control chip U6B are respectively connected to the low enable receiving pin 66, high enable receiving pin 65, write enable receiving pin 60, and read enable receiving pin 59 of each DPRAM chip through a resistor (such as R1, R2, R13, R14). All chip select enable control pins (such as EMA_CS[1], EMA_CS[2], EMA_CS[3], EMA_CS[4], EMA_CS[5]) of the main control chip U6B are respectively connected to the first chip select enable receiving pin 64 of each corresponding DPRAM chip through a resistor (such as R8, R7, R6, R5, R4). All unused pins of the main control chip U6B, except the EMS_RAS pin "A16" and the EMS_WAIT[0] pin "B18", are connected to resistors (such as R3, R9, R10, R11, R12). Except for the resistor R11 connected to the clock pin, the other resistors R1~R10 and resistors R12~R14 are connected to the I / O pins of the DSP chip and then connected to the DPRAM chip. The DSP chip and the DPRAM chip are not directly connected. This is to avoid reflections generated by the circuit during high-speed signal transmission, thereby ensuring signal integrity, improving transmission efficiency, and reducing transmission bit error rate.

[0027] Due to the limited pin resources of the main control chip such as DSP, the address line pins (A0R~A15R) of DPRAM chip U7B and DPRAM chip U9B are connected to the EMIF address bus pins (EMA_A[0]~EMA_A

[15] ) of the main control chip U6B, and the I / O data line pins (I / O0R~I / O15R) of DPRAM chip U7B and DPRAM chip U9B are connected to the data bus pins (EMA_D[0]~EMA_D

[15] ) of the main control chip U6B. Figure 1 As shown, this connection method allows the data bus and address bus of the two DPRAM chips to be multiplexed, saving DSP pin resources.

[0028] This utility model is passed Figure 1 According to the circuit design principle, the DSP can control the enabling of the DPRAM based on the chip select signal, so that the read and write operations of two or more DPRAMs do not conflict when in use, thereby achieving the purpose of multiplexing two or more DPRAM chips by one DSP.

[0029] The utility model design is not limited to Figure 1 The two DPRAMs are multiplexed as shown. Figure 1 The connection method can be expanded to realize the design of multiple DPRAM multiplexing, such as Figure 2Multiple DPRAM multiplexing circuit design principle frame Figure 2 shown.

[0030] like Figure 2 Shown in Figure 1 The circuit principle is that multiple DPRAM chips share a set of data buses (EMA_D) and EMIF address buses (EMA_A) connected to the main control chip (such as DSP chip). The DSP chip controls the operation of each DPRAM chip through the chip select enable CS. In theory, the only factor that limits the number of DPRAM chips reused is the chip select I / O pin resources of the main control chip (DSP) (such as the number of EMA_CS[1]~EMA_CS[n]). If the chip select I / O pin resources are sufficient, the number of reused DPRAM chips can be continuously increased. The design of multiplexing multiple DPRAMs based on the EMIF bus is completed.

[0031] Although the functions and working processes of the utility model are described above in conjunction with the accompanying drawings, the utility model is not limited to the above-mentioned specific functions and working processes, and the above-mentioned specific implementation methods are merely illustrative rather than restrictive. Under the enlightenment of the utility model, ordinary technicians in this field can also make many forms without departing from the scope of protection of the purpose of the utility model and the claims, which are all within the protection of the utility model.

Claims

1. A DPRAM multiplexing circuit based on EMIF bus, including a main control chip U6B, characterized in that: The main control chip (U6B) is connected to a plurality of DPRAM chips, and each of the DPRAM chips is connected to an inverter chip; The address line pins of each DPRAM chip are connected to the EMIF address bus pins of the main control chip, the I / O data line pins of each DPRAM chip are connected to the data bus pins of the main control chip (U6B), the read enable receiving pin (59), the write enable receiving pin (60), the high enable receiving pin (65), and the low enable receiving pin (66) of each DPRAM chip are respectively connected to the read enable control pin (B15), the write enable control pin (B9), the high enable control pin (A5), and the low enable control pin (C8) of the main control chip (U6B), and the SEMR enable pin (62) of each DPRAM chip is connected to a 3.3V power supply (VCC); The second chip select enable receiving pin (63) of each DPRAM chip is connected to the output pin (4) of the corresponding inverter chip, and the first chip select enable receiving pin (64) of each DPRAM chip and the input pin (2) of the corresponding inverter chip are connected to the chip select enable control pin correspondingly allocated to each DPRAM chip in the main control chip (U6B).

2. The DPRAM multiplexing circuit based on the EMIF bus according to claim 1, characterized in that: The main control chip (U6B) adopts a DSP chip.

3. The DPRAM multiplexing circuit based on EMIF bus according to claim 1, characterized in that: The number of DPRAM chips connected to the main control chip (U6B) is equal to the number of chip selection enable control pins of the main control chip, and each DPRAM chip corresponds to an inverter chip.

4. The DPRAM multiplexing circuit based on the EMIF bus according to claim 1, characterized in that: The low enable control pin (C8), high enable control pin (A5), write enable control pin (B9), and read enable control pin (B15) of the master control chip (U6B) are respectively connected to the low enable receiving pin (66), high enable receiving pin (65), write enable receiving pin (60), and read enable receiving pin (59) of each DPRAM chip through a resistor, and all chip select enable control pins of the master control chip (U6B) are respectively connected to the first chip select enable receiving pin (64) of each corresponding DPRAM chip through a resistor.

5. The DPRAM multiplexing circuit based on EMIF bus according to claim 1, characterized in that: The ground pin (3) of each inverter chip is grounded (GND), and the power pin (5) is connected to a 3.3V power supply (VCC).

6. The DPRAM multiplexing circuit based on EMIF bus according to claim 1, characterized in that: The SEMR enable pin (62) of each DPRAM chip is connected to a 3.3V power supply (VCC) via a 10K resistor.

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