Silicon gate CMOS analog switch chip

Abstract

The utility model provides a silicon gate CMOS analog switch chip comprising a port layout area which is arranged around the edge of the chip and is provided with a first data input / output port, a second data input / output port and a control signal input port, and the first data input / output port and the second data input / output port are located on the two sides of the chip respectively; the input control circuit layout area is adjacent to the port layout area and is used for shaping a control signal from the control signal input port; the one or more driving circuit layout areas are adjacent to the input control circuit layout area and can generate driving signals based on the shaped control signals; and the transmission channel layout areas are the same as the driving circuit layout areas in number, adjacent to the driving circuit layout areas in a one-to-one correspondence manner and adjacent to the port layout areas, transmission channel circuits are arranged, and the transmission channel circuits are connected with the first data input / output ports and the second data input / output ports and can be turned on / off based on driving signals.

Description

Technical Field

[0001] The present disclosure relates to the technical field of analog switches, and in particular to a silicon-gate CMOS analog switch chip. Background Art

[0002] Analog switches are mainly used to connect or disconnect signals in electronic devices. Analog switches are widely used in automatic control systems and computers because of their low power consumption, high speed, no mechanical contacts, small size and long service life.

[0003] Currently, the ports of commercialized analog switches for connecting external circuits are mostly evenly distributed on the periphery of the chip, but there is no clear area division for ports with different functions. If the ports are not properly positioned, it will lead to waste of layout space during internal layout design and excessive crossing and overlapping of metal lines, causing chip performance defects. During testing and application, if the ports are connected incorrectly, it will often cause chip damage. Utility Model Content

[0004] In order to solve the above problems existing in the prior art, the present disclosure provides a silicon gate CMOS analog switch chip, the layout structure of which includes:

[0005] The port layout area is arranged around the edge of the chip, in which a first data input / output port, a second data input / output port and a control signal input port are arranged, and the first data input / output port and the second data input / output port are respectively located on both sides of the chip; and one of the first data input / output port and the second data input / output port is used for inputting data, and the other is used for outputting data.

[0006] An input control circuit layout area, adjacent to the port layout area and used to shape the control signal from the control signal input port;

[0007] One or more drive circuit layout areas are adjacent to the input control circuit layout area and can generate drive signals based on the shaped control signal;

[0008] The transmission channel layout area is adjacent to the driving circuit layout area in the same number and one-to-one correspondence, and is adjacent to the port layout area, in which a transmission channel circuit is set, which is respectively connected to the first data input / output port and the second data input / output port, and can be turned on / off based on the driving signal.

[0009] In the above scheme,

[0010] Optionally, the port layout area includes:

[0011] The first port layout area and the second port layout area are arranged at two ends of the chip opposite to each other;

[0012] The third port layout area and the fourth port layout area are arranged opposite to each other and are both located between the first port layout area and the second port layout area;

[0013] in,

[0014] A first data input / output port is arranged in the first port layout area, a second data input / output port is arranged in the second port layout area, and an electrostatic protection structure is arranged in both the first port layout area and the second port layout area;

[0015] The third port layout area and the fourth port layout area are both provided with control signal input ports, and are respectively provided with power input ports, ground wire ports and electrostatic protection structures.

[0016] In the above scheme, the data input / output ports are divided into two groups and distributed on both sides of the chip, which are used for input and output respectively, which is convenient for subsequent testing and application, and can also avoid chip damage caused by port connection errors.

[0017] Optionally, both ends of the first port layout area and the second port layout area extend toward each other and are in a "U" shape. The above features can minimize the occurrence of excessively long metal wires (such as aluminum wires) during input and output wiring, which may affect the circuit delay time, and facilitate pressure welding connection with the tube shell to avoid pressure welding errors.

[0018] Optionally, the spacing between adjacent parts in the port layout area is 6μm to 10μm. The purpose of this spacing setting is to avoid unnecessary space waste in the chip area, and to avoid the isolation protection grooves around the MOS tube from intersecting or overlapping during the manufacturing process, thereby causing abnormal chip electrical parameters or even functional failure. And / or, the spacing between the input control circuit layout area and the third port layout area or the fourth port layout area is 190μm to 200μm. The purpose of this spacing is to avoid unnecessary space waste in the chip area, facilitate the spatial distribution of power lines and ground lines in the chip, and reduce the erroneous connection between the ports in the third port layout area and the fourth port layout area and the irrelevant metal lines in the input control circuit layout area during the process flow. And / or, the distance between the drive circuit layout area and the input control circuit layout area is 6μm to 10μm.

[0019] Optionally, the input control circuit layout area is rectangular, adjacent to the first port layout area or the second port layout area, and adjacent to the third port layout area and the fourth port layout area;

[0020] A multi-stage inverter circuit is arranged in the input control circuit layout area, and the multi-stage inverter circuit is connected to the control signal input port;

[0021] Optionally, a multi-stage inverter circuit is provided in the driving circuit layout area, which is electrically connected to the circuit in the input control circuit layout area and is configured to increase the driving capability of the received signal and improve the delay time.

[0022] Optionally, the transmission channel layout area includes:

[0023] a main body portion, adjacent to one of the first port layout area and the second port layout area;

[0024] An extension portion, one end of which is connected to the main body portion, and the other end of which extends toward the other of the first port layout area and the second port layout area;

[0025] in,

[0026] In a direction perpendicular to the extension direction, the width of the extension portion is smaller than that of the main body portion;

[0027] The transmission channel layout area and the corresponding driving circuit layout area are combined to form a rectangle.

[0028] In this optional solution, the design of the main part and the extension part of the transmission channel layout area can shorten the length of the metal wire from the driving circuit layout area to the transmission channel layout area to the greatest extent, realize faster transmission of electrical signals, and efficiently utilize the chip area; in addition, the driving circuit layout area and the transmission channel layout area are combined to form a new rectangle, which also makes the internal layout of the chip more regular and neat, which is conducive to the compact arrangement of each layout area and is conducive to the miniaturization of the chip.

[0029] Optionally, the distance between the transmission channel layout area and the adjacent port layout area is 190 μm to 200 μm.

[0030] Optionally, a symmetrical transmission channel circuit and a substrate bias structure of the transmission channel are arranged in the transmission channel layout area;

[0031] The transmission channel circuit is electrically connected to the first data input / output port and the second data input / output port in the first port layout area and the second port layout area respectively;

[0032] The transmission channel circuit is electrically connected to the multi-stage inverter circuit in the driving circuit layout area, and the transmission channel circuit is used for transmitting level signals on both sides of the transmission channel.

[0033] Optionally, the silicon gate CMOS analog switch chip has multiple channels, and the number of the driving circuit layout area and the number of the transmission channel layout area are the same as the number of the channels;

[0034] Among them, the adjacent driving circuit layout areas and transmission channel layout areas are symmetrically arranged.

[0035] In summary, the chip layout structure provided in the embodiment of the present disclosure can be used to avoid the waste of redundant layout space and excessive crossing and overlapping of multi-layer metal wires, thereby avoiding chip performance defects caused by unreasonable layout; and during chip testing and application, each port can be effectively identified, thereby improving test efficiency and application security, and avoiding chip damage caused by port misconnection. On the other hand, the utilization efficiency of the internal layout area of ​​the chip is high, and the overall structure of the chip is compact, which is conducive to the miniaturization of the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the background technology, the drawings required for use in the embodiments of the present disclosure or the background technology will be described below.

[0037] Figure 1 is a schematic diagram of the layout structure of an embodiment of the present disclosure;

[0038] Figure 2 is a schematic diagram of a layout structure of an embodiment of the present disclosure, which shows four port layout areas arranged around a chip;

[0039] Figure 3 It is a schematic diagram of the layout structure of an embodiment of a two-way single-pole single-throw analog switch chip disclosed in the present invention;

[0040] Figure 4 is a schematic diagram of the layout structure of an embodiment of a three-way single-pole single-throw analog switch chip disclosed in the present invention;

[0041] Figure 5 It is a schematic diagram of the layout structure of an embodiment of a 15-way single-pole single-throw analog switch chip disclosed in the present invention;

[0042] Figure 6 The device logic diagram of the 15-way single-pole single-throw analog switch chip involved in the present disclosure;

[0043] Figure 7 A logic schematic diagram of a 15-way single-pole single-throw analog switch chip involved in the present disclosure;

[0044] Figure 8 A schematic diagram of device pin distribution of a 15-way single-pole single-throw analog switch chip involved in the present disclosure;

[0045] Note in the figure:

[0046] 100-port layout area, 200-input control circuit layout area, 300-drive circuit layout area, 400-transmission channel layout area;

[0047] 101 - first port layout area, 102 - second port layout area, 103 - third port layout area, 104 - fourth port layout area;

[0048] 30n and 3mn are the driving circuit layout areas corresponding to the nth channel or the mnth channel of the switch chip respectively;

[0049] 40n and 4mn are transmission channel layout areas corresponding to the nth channel or the mnth channel of the switch chip respectively. DETAILED DESCRIPTION

[0050] Some embodiments of the present disclosure will now be described more fully below with reference to the accompanying drawings, however, the present disclosure can be implemented in many different ways and should not be construed as being limited to the embodiments set forth herein. On the contrary, providing these embodiments herein will make the present disclosure more detailed and complete, and fully convey the scope of the present disclosure to those skilled in the art. The same reference numerals throughout the text represent the same objects.

[0051] In order to solve or improve the problems existing in the aforementioned prior art, the embodiments of the present disclosure are intended to provide a single-pole single-throw (SPST) analog switch, more specifically, a silicon-gate CMOS analog switch chip.

[0052] The disclosed embodiment optimizes the layout of the chip and carefully classifies and divides all ports on the chip: the data input / output ports (I / O ports, input / output ports with input functions as the main function) of all channels are distributed on one side of the chip, and the data output / input ports (O / I ports, input / output ports with output functions as the main function) of all channels are distributed on the other side of the chip opposite thereto, so as to facilitate subsequent testing and application and avoid chip damage caused by port connection errors. In addition, based on the distribution of the above ports, a reasonable layout is adopted to minimize the chip area and reduce the chip manufacturing cost while achieving high performance and high reliability.

[0053] In addition, there are isolation protection grooves around the MOS tubes in the layout area to effectively avoid interference between different transistors and improve the device's anti-latch capability.

[0054] In the embodiments of the present disclosure, the concepts of "channel" and "way" are the same, and these two descriptions can be replaced. For example, "three-channel single-pole single-throw analog switch" can also be described as "three-way single-pole single-throw analog switch". In the embodiments of the present disclosure, the description of "channel" is mainly used.

[0055] The silicon gate CMOS analog switch chip provided in the embodiments of the present disclosure is as follows: Figure 1 As shown, it has a layout structure with the following characteristics:

[0056] The port layout area 100 is arranged around the edge of the chip, in which the first data input / output port, the second data input / output port and the control signal input port are arranged. The first data input / output port and the second data input / output port are respectively located on both sides of the chip.

[0057] For example, the port layout area 100 includes ports mainly used for output, which can be called data output / input ports (O / I ports) and their corresponding electrostatic protection structures, which are arranged in Figure 1 Also includes a port mainly used for input, which can be called a data input / output port (I / O port) and its corresponding electrostatic protection structure, arranged in such Figure 1 The right end of the middle port layout area 100.

[0058] It should be understood that the data input / output ports placed at both ends of the port layout area 100 in the embodiment are distinguished based on their actual functions in the chip, for example, the input data port (electrically connected to the input pin) and the output data port (electrically connected to the output pin) are placed at both ends of the chip. Therefore, the chip input pins S1-S15 and output pins D1-D15 are located at both ends of the chip, or Figure 8 As shown, under the premise that most of the pins are located at the two ends, some of the pins are extended to the edges adjacent to the two ends.

[0059] The input control circuit layout area 200 is adjacent to the port layout area 100 and is used to shape the control signal from the control signal input port; for example, the input control circuit layout area 200 can be as follows Figure 1 As shown, it is arranged on the right side of the chip, adjacent to the right side portion, and the upper and lower portions of the port layout area 100. Under this arrangement, the control signal input port can be arranged in the aforementioned three portions of the port layout area 100 adjacent to the input control circuit layout area 200 to provide the input control circuit layout area 200 with the control signal to be shaped.

[0060] One or more drive circuit layout areas 300 are adjacent to the input control circuit layout area 200 and can generate a drive signal based on the shaped control signal; wherein the number of the drive circuit layout areas 300 is the same as the number of channels of the chip, for example Figure 1 The single-channel chip shown in FIG. 1 includes a driving circuit layout area 300 .

[0061] The transmission channel layout area 400 is adjacent to the driving circuit layout area 300 in the same number and one-to-one correspondence, and is adjacent to the port layout area 100, for example Figure 1The single-channel chip shown in the figure includes a transmission channel layout area 400. A transmission channel circuit is provided in the transmission channel layout area 400. The transmission channel circuit is respectively connected to the first and second data input / output ports and can be turned on / off based on a driving signal. For example, the data input from the first data input / output port can be output from the second data input / output port via the turned-on transmission channel circuit, or the data input from the second data input / output port can be output from the first data input / output port via the turned-on transmission channel circuit.

[0062] According to an embodiment of the present disclosure, in a preferred embodiment, as Figure 2 shown, the port layout area 100 specifically includes the first to fourth port layout areas, where: the first port layout area 101 and the second port layout area 102 are relatively arranged at both ends of the chip; the third port layout area 103 and the fourth port layout area 104 are relatively arranged and are both located between the first port layout area 101 and the second port layout area 102. A first data input / output port is provided in the first port layout area 101, a second data input / output port is provided in the second port layout area 102, and an electrostatic protection structure is provided in both port layout areas. One of the first data input / output port and the second data input / output port is selected as the data input end, and the other is used as the data output end. A control signal input port, a power input port, and a ground wire port are provided in both the third port layout area 103 and the fourth port layout area 104. In addition, an electrostatic protection structure can also be provided.

[0063] According to an embodiment of the present disclosure, in a preferred embodiment, there are isolation protection grooves around the MOS transistors in each of the foregoing layout areas, effectively avoiding interference between different transistors and improving the device's anti-latch-up ability.

[0064] According to an embodiment of the present disclosure, in a preferred embodiment, as Figures 2 to 4 shown, both ends of the first port layout area 101 and the second port layout area 102 extend towards the middle of the chip and are in a "U" shape or a "匚" shape. Correspondingly, as Figure 8 shown, the S pins and D pins also partially extend and are arranged on the upper and lower sides of the chip shown in the figure. For example, S1 to S3, D1 to D3 extending on the upper side of the chip layout, and S14, S15 and D14, D15 extending on the lower side of the chip layout.

[0065] According to an embodiment of the present disclosure, in a preferred embodiment, the distance between adjacent parts in the port layout area 100, that is, the minimum distance between adjacent parts, is 6 μm to 10 μm.

[0066] As Figure 2As shown, the input control circuit layout area 200 is rectangular, adjacent to the second port layout area 102, and also adjacent to the third port layout area 103 and the fourth port layout area 104 respectively.

[0067] A multi-stage inverter circuit is arranged in the input control circuit layout area 200 , and an input end of the multi-stage inverter circuit is connected to a control signal input port.

[0068] Although not shown in the figure, in the embodiment of the present disclosure, the input control circuit layout area 200 can also be set on the left side of the figure, that is, adjacent to the first port layout area 101, and adjacent to the third port layout area 103 and the fourth port layout area 104.

[0069] In a preferred embodiment, the spacing between the input control circuit layout area 200 and the third port layout area 103 or the fourth port layout area 104, that is, the minimum distance between adjacent parts, is 190 μm to 200 μm.

[0070] In a preferred embodiment, a multi-stage inverter circuit is provided in the driving circuit layout area 300, which is electrically connected to the circuit in the input control circuit layout area 200 and is configured to increase the driving capability of the received signal and improve the delay time.

[0071] In a preferred embodiment, the distance between the driving circuit layout area 300 and the input control circuit layout area 200, that is, the minimum distance between adjacent parts, is 6 μm to 10 μm.

[0072] It should be understood that the specific circuit structures of the circuit in the input control circuit layout area 200 and the multi-stage inverter circuit in the drive circuit layout area 300 are no different from the prior art, and those skilled in the art can design them as appropriate based on the product usage scenarios. Therefore, due to space limitations, the aforementioned circuit structures will not be repeated in this disclosure.

[0073] like Figure 2 As shown, in a typical embodiment of the present disclosure, the transmission channel layout area 400 includes:

[0074] A main body portion, adjacent to the first port layout area 101;

[0075] An extension portion, one end of which is connected to the main body portion, and the other end of which extends in a direction toward the second port layout area 102;

[0076] In the direction perpendicular to the extension direction (vertical direction in the figure), the width (size) of the extension portion is smaller than that of the main body portion, and the entire transmission channel layout area 400 forms an "L" shape, or a "L-shape".

[0077] The input control circuit layout area 200 is set as follows Figure 2In the embodiment on the left side, that is, adjacent to the first port layout area 101, correspondingly, the main body is adjacent to the second port layout area 102, and the extension portion extends toward the direction of the first port layout area 101.

[0078] In other words, in the embodiment of the present disclosure, the main body is adjacent to one of the first port layout area and the second port layout area; one end of the extension portion is connected to the main body, and the other end extends toward the other of the first port layout area and the second port layout area (not adjacent to the main body, or adjacent to the input control circuit layout area 200).

[0079] And if Figure 2 As shown, the transmission channel layout area 400 and the corresponding driving circuit layout area 300 are combined to form a rectangle.

[0080] In a preferred embodiment, the distance between the transmission channel layout area 400 and the port layout area 100, that is, the minimum distance between adjacent parts, is 190 μm to 200 μm.

[0081] In a preferred embodiment, a symmetrical transmission channel circuit and a substrate bias structure of the transmission channel are arranged in the transmission channel layout area 400 .

[0082] It should be understood that the specific circuit structure of the circuit in the transmission channel layout area 400 is the same as the prior art, and those skilled in the art can design it as appropriate according to the product usage scenario. Therefore, the aforementioned circuit structure is not repeated in this disclosure.

[0083] Two ends of the transmission channel circuit are electrically connected to the first data input / output port and the second data input / output port in the first port layout area 101 and the second port layout area 102 respectively;

[0084] The transmission channel circuit is electrically connected to the multi-stage inverter circuit in the driving circuit layout area 300, or other circuits that play the same role.

[0085] In a preferred embodiment, the provided silicon gate CMOS analog switch chip has multiple channels, and the number of the driving circuit layout area 300 and the transmission channel layout area 400 is the same as the number of channels; wherein the adjacent driving circuit layout areas 300 and the transmission channel layout areas 400 are symmetrically arranged. Figure 3 , Figure 4 , Figure 5 The chip layouts of 2 channels, 3 channels and 15 channels are shown as examples.

[0086] Several representative embodiments are provided below to more clearly describe the technical solutions defined in the present disclosure.

[0087] Example 1: Single-channel SPST analog switch

[0088] like Figure 2 As shown, the chip in the embodiment is a single-channel single-pole single-throw analog switch, and its chip layout includes a port layout area 100, an input control circuit layout area 200, a drive circuit layout area 300 and a transmission channel layout area 400. Each layout area is Figure 2 Marked with wireframe.

[0089] The port layout area 100 is connected to the input control circuit layout area 200 and the transmission channel layout area 400 respectively; the input control circuit layout area 200 is connected to the drive circuit layout area 300; and the drive circuit layout area 300 is connected to the transmission channel layout area 400.

[0090] The port layout area 100 is provided with input / output ports distributed around the chip, and specifically includes four parts, wherein the first port layout area 101 is arranged opposite to the second port layout area 102, and the third port layout area 103 is arranged opposite to the fourth port layout area 104.

[0091] The first port layout area 101 is provided with a data output / input port (O / I port) and its corresponding electrostatic protection structure; the second port layout area 102 is provided with a data input / output port (I / O port) and its corresponding electrostatic protection structure.

[0092] The third port layout area 103 and the fourth port layout area 104 are provided with a control signal input port, a power input interface, a ground port and an electrostatic protection structure corresponding to each port. The input control signal enters from the third port layout area 103 and the fourth port layout area 104 where the control signal input port is located, and after being processed by the entire complete circuit, the final data output signal is output from the data output / input port (O / I port) of the first port layout area 101.

[0093] In order to minimize the occurrence of metal wires (such as aluminum wires) that are too long during input and output wiring, which may affect the circuit delay time, and to ensure convenient pressure welding connection with the tube shell to avoid pressure welding errors, the port layout area 100 is set on the board Figure 4 The first port layout area 101 and the second port layout area 102 are respectively located on one side of the chip and both ends thereof extend to occupy partial areas of the adjacent two sides.

[0094] A preset distance 1 is set between the four parts of the port layout area 100, which is 6μm to 10μm. If the preset distance 1 is greater than 10μm, unnecessary space waste may occur in the chip area; if the preset distance 1 is less than 6μm, the isolation protection grooves around the MOS tube may intersect or overlap during the manufacturing process, thereby causing abnormal chip electrical parameters or even functional failure.

[0095] The input control circuit layout area 200 includes a group of multi-stage inverters. This group of multi-stage inverters is used to shape the input control signal. The input control circuit layout area 200 is rectangular and is located in the right area of ​​the chip and on the left side of the second port layout area 102 in the port layout area 100.

[0096] The input control circuit layout area 200 is connected to the third port layout area 103 and the fourth port layout area 104 in the port layout area 100 to ensure efficient processing of the input control signal.

[0097] A preset distance 2 is set between the input control circuit layout area 200 and the third port layout area 103 and the fourth port layout area 104 in the port layout area 100, and the preset distance 2 is 190μm to 200μm. If the preset distance is greater than 200μm, unnecessary space waste may occur in the chip area; if the preset distance is less than 190μm, there is not enough chip space to distribute the power line and the ground line during the layout, and during the process tape-out, the ports in the third port layout area 103 and the fourth port layout area 104 may be incorrectly connected to the irrelevant metal lines in the input control circuit layout area 200.

[0098] The driving circuit layout area 300 includes a group of multi-stage inverters, which are controlled by an input control circuit. This group of multi-stage inverters has the function of increasing the driving capability and improving the delay time. In order to facilitate receiving the signal processed by the input control circuit, the driving circuit layout area 300 is connected to the input control circuit layout area 200 and is arranged adjacent to each other. The driving circuit layout area 300 and the input control circuit layout area 200 are provided with a preset distance three, and the preset distance three can specifically be 6μm to 10μm.

[0099] The transmission channel layout area 400 includes a group of symmetrical transmission channel circuits and a substrate bias structure of the transmission channel. The transmission channel circuit is used to transmit level signals on both sides of the transmission channel.

[0100] The transmission channel layout area 400 is L-shaped, that is, the transmission channel layout area 400 is generally L-shaped, including a main body and an extension part, wherein the main body is arranged close to the first port layout area 101 of the port layout area 100, one side of the extension part is connected to the main body, and the other side extends toward the second port layout area 102 of the port layout area 100, and the width of the extension part (that is, the dimension perpendicular to the extension direction) is smaller than the dimension of the main body, thereby forming a space, and the driving circuit layout area 300 is located in this space, and the driving circuit layout area 300 and the transmission channel layout area 400 are combined into a rectangular shape as a whole.

[0101] Specifically, the electrical parameters of the PMOS tube and the NMOS tube used in the transmission channel are difficult to be strictly consistent, and there are more or less differences. When designing the circuit, the dimensions of the PMOS tube and the NMOS tube calculated according to the chip electrical parameter requirements are different, resulting in differences in the layout area used by the PMOS tube and the NMOS tube during layout. Compared with combining the PMOS tube layout area and the NMOS tube layout area into a rectangular shape, the transmission channel layout area 400 adopts a special L-shaped shape, which can shorten the length of the metal wire from the drive circuit layout area 300 to the transmission channel layout area 400 to the greatest extent, realize faster transmission of electrical signals, and improve the efficiency of chip area use.

[0102] In addition, the driving circuit layout area 300 and the transmission channel layout area 400 are combined to form a new rectangle, which also makes the internal layout of the chip more regular and neat, which is conducive to the compact arrangement of each layout area and realizes the miniaturization of the chip.

[0103] The transmission channel layout area 400 is connected to both the port layout area 100 and the driving circuit layout area 300. There is a preset distance 4 between the transmission channel layout area 400 and the port layout area 100. The preset distance 4 may be 190 μm to 200 μm.

[0104] Example 2: Two-way SPST analog switch

[0105] like Figure 3 As shown, if the chip is a two-way single-pole single-throw analog switch, the number of the transmission channel layout area 400 and the number of the drive circuit layout area 300 are two each. The two transmission channel layout areas 400 are symmetrically arranged, and the two drive circuit layout areas 300 are adjacent to each other. The drive circuit / transmission channel layout areas of adjacent channels adopt a symmetrical layout, which can distribute MOS tubes with the same potential on the same side, reduce the layout area occupied by metal lines, and improve chip space utilization.

[0106] In this embodiment, the input control circuit of the input control circuit layout area can be a group of multi-stage inverters or two groups of multi-stage inverters: if it is a group of multi-stage inverters, then the group of multi-stage inverters can control the opening or closing of two transmission channels at the same time; if it is two groups of multi-stage inverters, then each group of inverters can control the opening or closing of one transmission channel respectively. The area of ​​the input control circuit layout area 200 varies with the number of multi-stage inverters in the input control circuit.

[0107] Example 3: Three-way SPST analog switch

[0108] like Figure 4 As shown, if the chip is a three-way single-pole single-throw analog switch, the number of the driving circuit layout area 300 and the number of the transmission channel layout area 400 are both three, wherein two adjacent transmission channel layout areas 400 are symmetrically arranged.

[0109] The input control circuit of the input control circuit layout area 200 can be a group of multi-stage inverters or three groups of multi-stage inverters: if it is a group of multi-stage inverters, then a group of multi-stage inverters can control the opening or closing of three transmission channels at the same time; if it is three groups of multi-stage inverters, then each group of multi-stage inverters can control the opening or closing of one transmission channel. The area of ​​the input control circuit layout area 200 varies with the number of multi-stage inverters in the input control circuit.

[0110] Example 4: 15-way SPST analog switch

[0111] Figure 5 The layout structure shown is a schematic diagram of the layout structure of a 15-way single-pole single-throw analog switch. In the figure, the driving circuit layout area and the transmission channel layout area are both 15 parts, and each part of the driving circuit layout area and the transmission channel layout area corresponds to one channel. Specifically, the following driving circuit layout areas in the figure: 301, 302, 303, 304, 305, 306, 307, 308, 309, 310, 311, 312, 313, 314, 315, and the following transmission channel layout areas corresponding thereto and capable of being assembled into a rectangle: 401, 402, 403, 404, 405, 406, 407, 408, 409, 410, 411, 412, 413, 414, 415, respectively correspond to 1 to 15 channels (roads) of the chip. For example, the driving circuit layout area 301 and the transmission channel layout area 401 correspond to the first channel of the switch chip; the driving circuit layout area 315 and the transmission channel layout area 415 correspond to the fifteenth channel of the switch chip.

[0112] The input control circuit of the input control circuit layout area can be one group of multi-stage inverters, three groups of multi-stage inverters, five groups of multi-stage inverters or fifteen groups of multi-stage inverters: if it is one group of multi-stage inverters, then one group of multi-stage inverters can control the opening or closing of fifteen transmission channels at the same time; if it is three groups of multi-stage inverters, then each group of multi-stage inverters can control the opening or closing of five transmission channels at the same time; if it is five groups of multi-stage inverters, then each group of multi-stage inverters can control the opening or closing of three transmission channels at the same time; if it is fifteen groups of multi-stage inverters, then each group of multi-stage inverters can control the opening or closing of one transmission channel.

[0113] like Figure 5 As shown, the drive circuit layout area and the transmission channel layout area are arranged crosswise in the vertical direction to more efficiently utilize the internal area of ​​the chip. The symmetrical layout of adjacent channels as shown in the figure can distribute MOS tubes with the same potential on the same side, reducing the layout area of ​​the metal wires and improving the chip space utilization.

[0114] The 15-way single-pole single-throw analog switch described in the aforementioned embodiment 4 includes five identical logic circuits, each of which is a group of multi-stage inverters in the input control circuit to control the opening and closing of three transmission channels. Exemplarily, the input control terminal symbol of the device is IN. When IN is at a low level, the three channels controlled by the input control terminal are turned off; when IN is at a high level, the three channels controlled by the input control terminal are turned on. The truth table is shown in Table 1:

[0115] Table 1 Truth table

[0116]

[0117]

[0118] The device logic diagram, logic schematic diagram, pin distribution diagram and pin definition involved in the embodiment are as follows: Figures 6 to 8 And as shown in Table 2.

[0119] Table 2 Pin Definition

[0120]

[0121] The above embodiments provide several layouts of single-pole single-throw analog switches. In other analog switches, the number of drive circuit layout areas and transmission channel layout areas and the area of ​​the input control circuit layout area can be adjusted according to specific requirements (such as one input control circuit controlling one transmission channel or multiple transmission channels) and the number of channels.

[0122] It should also be noted that, in order to facilitate a clear description of the layout structure and positional relationship, the above embodiments are all described in terms of orientation based on the drawings of this application. Therefore, if the rotation angle of the image is adjusted, the corresponding position will also change adaptively.

[0123] In summary, in view of the actual situation that most single-pole single-throw analog switches have a large number of ports, the disclosed embodiment sets the input and output port layout area in the chip layout into four parts, and carefully classifies and divides all ports to set different types of ports in different parts. In this way, when laying out the layout, it can help avoid the waste of redundant layout space and excessive crossing and overlapping of multi-layer metal wires, thereby avoiding chip performance defects caused by unreasonable layout layout; and when testing and applying the chip, each port can be effectively identified, thereby improving test efficiency and application security, and avoiding chip damage caused by port misconnection.

[0124] On this basis, by reasonably setting the shape and layout of the input control circuit layout area and the driving circuit layout area, such as the cross-distribution of the driving circuit layout area and the transmission channel layout area, the internal area of ​​the chip can be utilized more efficiently, thereby achieving a compact overall chip structure and facilitating the miniaturization of the chip.

[0125] In addition, an isolation protection groove is designed around each MOS tube in the layout area. During layout, the isolation protection groove can separate MOS tubes with different potentials by a certain distance, so that there is enough distance between wells with different potentials, thereby enhancing the device's anti-latch capability and improving product reliability.

[0126] The preset distance between the driving circuit layout area and the transmission channel layout area is to avoid the intersection or overlap between the grooves caused by the process errors generated during the manufacturing process of the isolation protection grooves around each MOS tube in the layout area, and at the same time reserve the wiring space connecting different layout areas.

[0127] The layout design concept disclosed in the present invention has strong applicability, and is applicable to both single-channel and multi-channel single-pole single-throw analog switches; it is also applicable whether the internal circuit wants to realize a group of multi-stage inverters in the input control circuit to control the opening or closing of a transmission channel, or a group of multi-stage inverters to control the opening or closing of multiple transmission channels.

[0128] The above description is only part of the specific implementation methods of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any changes or substitutions that can be easily thought of by any technician familiar with the technical field within the technical scope disclosed in the embodiments of the present disclosure should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A silicon gate CMOS analog switch chip, characterized in that: The layout structure includes the following: A port layout area (100) is arranged around the edge of the chip, wherein a first data input / output port, a second data input / output port and a control signal input port are arranged, wherein the first data input / output port and the second data input / output port are respectively located at two sides of the chip; and one of the first data input / output port and the second data input / output port is used for inputting data, and the other is used for outputting data; An input control circuit layout area (200), adjacent to the port layout area (100), for shaping the control signal from the control signal input port; One or more drive circuit layout areas (300), adjacent to the input control circuit layout area (200), capable of generating a drive signal based on the shaped control signal; The transmission channel layout area (400) is adjacent to the driving circuit layout area (300) in the same number and one-to-one correspondence, and is adjacent to the port layout area (100), wherein a transmission channel circuit is arranged, the transmission channel circuit is respectively connected to the first data input / output port and the second data input / output port, and can be turned on / off based on the driving signal.

2. The silicon-gate CMOS analog switch chip according to claim 1, characterized in that: The port layout area (100) includes: A first port layout area (101) and a second port layout area (102) are arranged at two ends of the chip opposite to each other; The third port layout area (103) and the fourth port layout area (104) are arranged opposite to each other and are both located between the first port layout area (101) and the second port layout area (102); in, The first data input / output port is arranged in the first port layout area (101), the second data input / output port is arranged in the second port layout area (102), and an electrostatic protection structure is arranged in both the first port layout area (101) and the second port layout area (102); The third port layout area (103) and the fourth port layout area (104) are both provided with the control signal input port, and are respectively provided with a power input port, a ground line port and an electrostatic protection structure.

3. The silicon gate CMOS analog switch chip according to claim 2, characterized in that: Both ends of the first port layout area (101) and the second port layout area (102) extend towards each other and are in a "U" shape.

4. The silicon gate CMOS analog switch chip according to claim 2, characterized in that: The distance between adjacent parts in the port layout area (100) is 6 μm to 10 μm; And / or, the distance between the input control circuit layout area (200) and the third port layout area (103) or the fourth port layout area (104) is 190 μm to 200 μm; And / or, the distance between the driving circuit layout area (300) and the input control circuit layout area (200) is 6 μm to 10 μm.

5. The silicon-gate CMOS analog switch chip according to claim 2, characterized in that: The input control circuit layout area (200) is rectangular, adjacent to the first port layout area (101) or the second port layout area (102), and adjacent to the third port layout area (103) and the fourth port layout area (104); A multi-stage inverter circuit is arranged in the input control circuit layout area (200), and the multi-stage inverter circuit is connected to the control signal input port.

6. The silicon-gate CMOS analog switch chip according to claim 1, characterized in that: A multi-stage inverter circuit is arranged in the driving circuit layout area (300), which is electrically connected to the circuit in the input control circuit layout area (200) and is configured to increase the driving capability of the received signal and improve the delay time.

7. The silicon-gate CMOS analog switch chip according to claim 2, characterized in that: The transmission channel layout area (400) includes: A main body portion, adjacent to one of the first port layout area (101) and the second port layout area (102); An extension portion, one end of which is connected to the main body portion, and the other end of which extends toward the other of the first port layout area (101) and the second port layout area (102); in, In a direction perpendicular to the extension direction, the width of the extension portion is smaller than that of the main body portion; The transmission channel layout area (400) and the corresponding driving circuit layout area (300) are combined to form a rectangle.

8. The silicon-gate CMOS analog switch chip according to claim 7, characterized in that: The distance between the transmission channel layout area (400) and the adjacent port layout area (100) is 190 μm to 200 μm.

9. The silicon-gate CMOS analog switch chip according to claim 7, characterized in that: A symmetrical transmission channel circuit and a substrate bias structure of the transmission channel are arranged in the transmission channel layout area (400); The transmission channel circuit is electrically connected to the first data input / output port and the second data input / output port respectively; The transmission channel circuit is electrically connected to the multi-stage inverter circuit in the driving circuit layout area (300).

10. The silicon gate CMOS analog switch chip according to any one of claims 1 to 9, characterized in that: The silicon-gate CMOS analog switch chip has a plurality of channels, and the number of the driving circuit layout area (300) and the number of the transmission channel layout area (400) are both the same as the number of channels; Wherein, the adjacent driving circuit layout area (300) and transmission channel layout area (400) are symmetrically arranged.

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