Slot based on Feiteng D3000 platform
By designing a PCIe X16 slot with identity pins and level conversion chips on the motherboard of the Feiteng D3000 platform, the problem of inflexible configuration of PCIe resources on the platform is solved, flexible allocation of PCIe resources and the satisfaction of multiple configuration requirements are achieved, and R&D and manufacturing costs are reduced.
Patent Information
- Application Number
- CN202421647774.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-07-11
- Publication Date
- 2025-05-02
- Estimated Expiration
- 2034-07-11
AI Technical Summary
The PCIe resource configuration of Feiteng D3000 platform is inflexible and cannot meet the user's multiple configuration needs, resulting in increased design and manufacturing costs.
Design a slot based on the Feiteng D3000 platform, and automatically split the PCIe X8 signal by setting the PCIe X16 slot and level conversion chip on the motherboard.
It realizes flexible allocation of PCIe resources of D3000 processor without the need for new development motherboards, greatly improving design flexibility and reducing R&D and manufacturing costs.
Smart Images
Figure CN222825899U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of computer mainboard design, in particular to a slot based on a Feiteng D3000 platform. Background Art
[0002] The Feiteng D3000 processor uses 8 high-performance server cores, supports DDR5 and PCIe5.0, and can meet the office and entertainment needs of more users.
[0003] In the related technology, the Feiteng D3000 platform implements the configuration of PCIe resources by fixing the pull-up and pull-down resistors, but the pull-up and pull-down resistors can only realize fixed PCIe splitting, which is not flexible and cannot meet the user's flexibility requirements for multiple configurations. If multiple requirements are to be met, a new motherboard needs to be developed to meet them, which increases the design and manufacturing costs as well as the maintenance costs. Utility Model Content
[0004] In view of this, the utility model provides a slot based on the Feiteng D3000 platform to solve the problem that the PCIe resources of the D3000 platform cannot be flexibly split and utilized.
[0005] In a first aspect, the utility model provides a slot based on the Feiteng D3000 platform, the slot comprising:
[0006] A PCIe X16 slot is provided on the mainboard and is connected to the D3000 processor and is used to connect to a PCIe X8 signal of an X8PCIe controller of the D3000 processor. The PCIe X16 slot is provided with a first identification pin and a second identification pin;
[0007] A level conversion chip is connected to the PCIe X16 slot and is used to transfer the first identity identification signal of the first identity identification pin to the first configuration pin of the D3000 processor, and transfer the second identity identification signal of the second identity identification pin to the second configuration pin of the D3000 processor, so that the D3000 processor splits the PCIe X8 signal transmitted to the PCIe X16 slot based on the level state of the configuration pin.
[0008] In the utility model, by setting an identity pin for the PCIe X16 slot arranged on the motherboard, the identity signal of the identity pin is transferred to the configuration pin of the D3000 processor, and the D3000 processor realizes the automatic splitting design of X8 PCIe resources according to different level state combinations of the configuration pins, thereby realizing the flexible allocation of PCIe resources of the D3000 processor without the need to develop a new motherboard, greatly improving the flexibility of the design, meeting the needs of different configurations, and effectively reducing the R&D and manufacturing costs.
[0009] In an optional implementation, the first identity identification signal of the first identity identification pin is grounded through a first resistor, and the second identity identification signal of the second identity identification pin is grounded through a second resistor.
[0010] In this manner, the first identification signal of the first identification pin is grounded through a first resistor, and the second identification signal of the second identification pin is grounded through a second resistor, so that the PCIe X8 signal can be split according to the level state of the configuration pin.
[0011] In an optional implementation, the level conversion chip is connected to the P1V8CPU, and the P1V8CPU is used to provide a 1.8V level for the IO pins of the D3000 processor and to provide a 1.8V level for the level conversion chip.
[0012] In this way, since the D3000 processor IO only supports 1.8V level, connecting one end of the level conversion chip to the P1V8CPU can effectively prevent the external voltage from leaking to the processor and causing abnormalities.
[0013] In an optional implementation, the level conversion chip is connected to P3V3VSB, and P3V3VSB is used to provide a 3.3V level standby power supply for the motherboard of the D3000 processor and to provide a 3.3V level standby power supply for the level conversion chip.
[0014] In this way, since the D3000 processor IO only supports 1.8V level, connecting one end of the level conversion chip to P3V3VSB can effectively prevent the external voltage from leaking to the processor and causing abnormalities.
[0015] In an optional embodiment, the slot also includes a dual M.2 SSD adapter card, which is provided with a first M.2 SSD slot, a second M.2 SSD slot, a first adapter card pin corresponding to the first identity identification pin, and a second adapter card pin corresponding to the second identity identification.
[0016] In this method, a PCIe dual M.2 SSD adapter card is designed, and combined with adapter card identity recognition, the host's need for multiple SSDs can be met.
[0017] In an optional implementation, the first pin signal of the first adapter card pin is pulled up to P3V3VSB through a third resistor, and the first pin signal corresponds to the first identity signal;
[0018] The second pin signal of the second adapter card pin is pulled up to P3V3VSB through the fourth resistor, and the second pin signal corresponds to the second identity recognition signal.
[0019] In this manner, the first pin signal of the first adapter card pin corresponds to the first identity recognition signal, and the second pin signal of the second adapter card pin corresponds to the second identity recognition signal, which facilitates the corresponding PCIe X8 signal splitting when the dual M.2 SSD adapter card is inserted.
[0020] In an optional embodiment, when the dual M.2 SSD adapter card is not inserted into the PCIe X16 slot, when the motherboard starts, the level states of the first configuration pin and the second configuration pin are both in a low level state, and the PCIe X8 signal transmitted to the PCIe X16 slot is not split.
[0021] In this mode, the PCIe X16 slot can support graphics cards, PCIe dual M.2SSD adapter cards, etc., which is flexible and expandable. Since there is no identification pin signal on the standard graphics card, the level state corresponding to the identification pin of the PCIe X16 slot is low. When the motherboard starts, the level state of the configuration pin of the D3000 processor is low. At this time, the configuration mode of the X8 PCIe controller is not to split and transmit the complete PCIe X8 signal.
[0022] In an optional embodiment, when a dual M.2 SSD adapter card is inserted into a PCIe X16 slot, when the motherboard starts, the first pin signal corresponds to the first identification signal, the second pin signal corresponds to the second identification signal, the level states of the first configuration pin and the second configuration pin are both high level states, and the PCIe X8 signal transmitted to the PCIe X16 slot is split into a first PCIe X4 signal and a second PCIe X4 signal.
[0023] In this way, the pin signal of the dual M.2 SSD adapter card and the identification signal of the PCIe X16 slot are both in a high-level state during power-on detection. The PCIe X8 signal on the D3000 processor realizes X4+X4 signal splitting, and the dual SSDs work normally, meeting the host's requirement for multiple SSDs.
[0024] In an optional implementation, the first resistor and the third resistor are in a voltage-dividing relationship, and the second resistor and the fourth resistor are in a voltage-dividing relationship.
[0025] In this manner, by forming a voltage-dividing relationship between the first resistor and the third resistor and a voltage-dividing relationship between the second resistor and the fourth resistor, the first identity identification pin and the second identity identification pin are both at a high level, thereby making the level signals of the first configuration pin and the second configuration pin high.
[0026] In an optional implementation, the first M.2 SSD slot corresponds to the first PCIe X4 signal, and the second M.2 SSD slot corresponds to the second PCIe X4 signal.
[0027] In this method, the PCIe X8 signal is split into X4+X4 signals, so that the dual SSDs can work normally, thereby meeting the host's need for multiple SSDs. BRIEF DESCRIPTION OF THE DRAWINGS
[0028] In order to more clearly illustrate the specific implementation methods of the utility model or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the utility model. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.
[0029] Figure 1 It is a structural schematic diagram of a slot based on the Feiteng D3000 platform according to an embodiment of the utility model.
[0030] Figure 2 It is a structural schematic diagram of a dual M.2 SSD adapter card according to an embodiment of the utility model. DETAILED DESCRIPTION
[0031] In order to make the purpose, technical solution and advantages of the embodiment of the utility model clearer, the technical solution in the embodiment of the utility model will be clearly and completely described below in conjunction with the drawings in the embodiment of the utility model. Obviously, the described embodiment is a part of the embodiment of the utility model, not all the embodiments. Based on the embodiment of the utility model, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the utility model.
[0032] In the related technology, the Feiteng D3000 platform implements the configuration of PCIe resources by fixing the pull-up and pull-down resistors, but the pull-up and pull-down resistors can only realize fixed PCIe splitting, which is not flexible and cannot meet the user's flexibility requirements for multiple configurations. If multiple requirements are to be met, a new motherboard needs to be developed to meet them, which increases the design and manufacturing costs as well as the maintenance costs.
[0033] In order to solve the above problems, a slot based on the Feiteng D3000 platform is provided in the embodiment of the utility model, which is suitable for the use scenario of the motherboard design using the Feiteng D3000 platform. The utility model provides a slot based on the Feiteng D3000 platform, and by setting an identity pin for the PCIe X16 slot set on the motherboard, the identity signal of the identity pin is transferred to the configuration pin of the D3000 processor, and the D3000 processor realizes the automatic splitting design of the X8 PCIe resources according to the level state combination of different configuration pins, and realizes the flexible allocation of the PCIe resources of the D3000 processor, without the need to develop a new motherboard, greatly improving the flexibility of the design, meeting the needs of different configurations, and effectively reducing the R&D and manufacturing costs.
[0034] According to an embodiment of the utility model, a slot embodiment based on the Feiteng D3000 platform is provided. In this embodiment, a slot based on the Feiteng D3000 platform is provided. Figure 1 Schematic diagram of the structure of the slot based on the Feiteng D3000 platform according to the embodiment of the utility model, such as Figure 1 As shown, the slots include:
[0035] A PCIe X16 slot is provided on the mainboard and is connected to the D3000 processor and is used to connect to a PCIe X8 signal of an X8PCIe controller of the D3000 processor. The PCIe X16 slot is provided with a first identification pin and a second identification pin;
[0036] A level conversion chip is connected to the PCIe X16 slot and is used to transfer the first identity identification signal of the first identity identification pin to the first configuration pin of the D3000 processor, and transfer the second identity identification signal of the second identity identification pin to the second configuration pin of the D3000 processor, so that the D3000 processor splits the PCIe X8 signal transmitted to the PCIe X16 slot based on the level state of the configuration pin.
[0037] In an optional implementation, the first identity identification signal of the first identity identification pin is grounded through a first resistor, and the second identity identification signal of the second identity identification pin is grounded through a second resistor.
[0038] In this manner, the first identification signal of the first identification pin is grounded through a first resistor, and the second identification signal of the second identification pin is grounded through a second resistor, so that the PCIe X8 signal can be split according to the level state of the configuration pin.
[0039] In an optional implementation, the level conversion chip is connected to the P1V8CPU, and the P1V8CPU is used to provide a 1.8V level for the IO pins of the D3000 processor and to provide a 1.8V level for the level conversion chip.
[0040] In this way, since the D3000 processor IO only supports 1.8V level, connecting one end of the level conversion chip to the P1V8CPU can effectively prevent the external voltage from leaking to the processor and causing abnormalities.
[0041] In an optional implementation, the level conversion chip is connected to P3V3VSB, and P3V3VSB is used to provide a 3.3V level standby power supply for the motherboard of the D3000 processor and to provide a 3.3V level standby power supply for the level conversion chip.
[0042] In this way, since the D3000 processor IO only supports 1.8V level, connecting one end of the level conversion chip to P3V3VSB can effectively prevent the external voltage from leaking to the processor and causing abnormalities.
[0043] In one example, if Figure 1 As shown, the PCIe X8 signal of the D3000 processor is connected to the PCIe X16 slot, and the ID0 and ID1 identification pins are designed on this slot. Then, these two ID signals are connected to the configuration pin CFG of the CPU through the level conversion chip. When the CPU starts up, different X8 PCIe split modes are implemented according to the high and low states of SE_CFG1 and SE_CFG2 detected. ID0 and ID1 are connected to the D3000 processor through the level conversion chip, and the D3000 implements the automatic split design of X8 PCIe resources according to different SE_CFG combinations. ID0 and ID1 are the identity recognition signals of the board, which are fed back to SE_CFG1 and SE_CFG2 on the D3000 CPU through the level conversion chip, thereby realizing the resource splitting of the PCIe controller when the computer is turned on.
[0044] Specifically, 1) the PCIe signals of the X8 PCIe controller of the Feiteng D3000 CPU on the motherboard are all connected to the PCIe X16 slot, which can be used to insert a graphics card, a network card, a PCIe dual M.2 SSD adapter card, etc.; 2) ID0 and ID1 identification pins are designed on this PCIe X16 slot, which are connected to GND through pull-down resistors R0 and R1 respectively. At the same time, these two signals are connected to SE_CFG1 and SE_CFG2 on the D3000 processor through a level conversion chip. The two sides of the level conversion chip use P3V3VSB and P1V8CPU pull-ups respectively. The level conversion chip is used mainly because the D3000 processor IO only supports 1.8V level and effectively prevents external voltage from leaking to the processor and causing abnormalities.
[0045] Figure 2 is a schematic diagram of the structure of a dual M.2 SSD adapter card according to an embodiment of the utility model, such as Figure 2 As shown, in an optional embodiment, the slot also includes a dual M.2 SSD adapter card, and the dual M.2 SSD adapter card is provided with a first M.2 SSD slot, a second M.2 SSD slot, a first adapter card pin corresponding to the first identity identification pin, and a second adapter card pin corresponding to the second identity identification.
[0046] In this method, a PCIe dual M.2 SSD adapter card is designed, and combined with adapter card identity recognition, the host's need for multiple SSDs can be met.
[0047] In an optional implementation, the first pin signal of the first adapter card pin is pulled up to P3V3VSB through a third resistor, and the first pin signal corresponds to the first identity signal;
[0048] The second pin signal of the second adapter card pin is pulled up to P3V3VSB through the fourth resistor, and the second pin signal corresponds to the second identity recognition signal.
[0049] In this manner, the first pin signal of the first adapter card pin corresponds to the first identity recognition signal, and the second pin signal of the second adapter card pin corresponds to the second identity recognition signal, which facilitates the corresponding PCIe X8 signal splitting when the dual M.2 SSD adapter card is inserted.
[0050] In an optional embodiment, when the dual M.2 SSD adapter card is not inserted into the PCIe X16 slot, when the motherboard starts, the level states of the first configuration pin and the second configuration pin are both in a low level state, and the PCIe X8 signal transmitted to the PCIe X16 slot is not split.
[0051] In this mode, the PCIe X16 slot can support graphics cards, PCIe dual M.2SSD adapter cards, etc., which is flexible and expandable. Since there is no identification pin signal on the standard graphics card, the level state corresponding to the identification pin of the PCIe X16 slot is low. When the motherboard starts, the level state of the configuration pin of the D3000 processor is low. At this time, the configuration mode of the X8 PCIe controller is not to split and transmit the complete PCIe X8 signal.
[0052] In an optional embodiment, when a dual M.2 SSD adapter card is inserted into a PCIe X16 slot, when the motherboard starts, the first pin signal corresponds to the first identification signal, the second pin signal corresponds to the second identification signal, the level states of the first configuration pin and the second configuration pin are both high level states, and the PCIe X8 signal transmitted to the PCIe X16 slot is split into a first PCIe X4 signal and a second PCIe X4 signal.
[0053] In this way, the pin signal of the dual M.2 SSD adapter card and the identification signal of the PCIe X16 slot are both in a high-level state during power-on detection. The PCIe X8 signal on the D3000 processor realizes X4+X4 signal splitting, and the dual SSDs work normally, meeting the host's requirement for multiple SSDs.
[0054] In an optional implementation, the first resistor and the third resistor are in a voltage-dividing relationship, and the second resistor and the fourth resistor are in a voltage-dividing relationship.
[0055] In this manner, by forming a voltage-dividing relationship between the first resistor and the third resistor and a voltage-dividing relationship between the second resistor and the fourth resistor, the first identity identification pin and the second identity identification pin are both at a high level, thereby making the level signals of the first configuration pin and the second configuration pin high.
[0056] In an optional implementation, the first M.2 SSD slot corresponds to the first PCIe X4 signal, and the second M.2 SSD slot corresponds to the second PCIe X4 signal.
[0057] In this method, the PCIe X8 signal is split into X4+X4 signals, so that the dual SSDs can work normally, thereby meeting the host's need for multiple SSDs.
[0058] In one example, if Figure 2 As shown in the figure, a PCIe dual M.2SSD adapter card is designed, which has 2 M.2SSD slots and 2 pin IDs corresponding to the PCIe X16 slots on the motherboard. On this adapter card, the two pin signals are pulled up to P3V3VSB through R2 and R3 resistors; among them, R0 and R2 are a group of voltage division, and R1 and R3 are a group of voltage division. As long as the voltage is high after voltage division, it is fine. For example: 3.3V×R2 / (R0+R2)=3.3V×1 / (10+1)=3V, which is still a high level.
[0059] When there is no need for dual M.2 SSDs, the PCIe X16 slot on the motherboard can be inserted into devices such as graphics cards. Since there are no ID0 and ID1 pin signals on standard graphics cards, the ID0 and ID1 on the motherboard are low level 00. When the motherboard starts, the SE_CFG1 and CFG2 of the D3000 processor detect 00. Referring to the manual of the D3000 processor, it can be seen that the configuration method of the X8 PCIe controller at this time is not to split the complete X8 signal.
[0060] When dual M.2 SSDs are required, the PCIe X16 slot on the motherboard can be inserted into a PCIe dual M.2 SSD adapter card. In order for the X8 PCIe controller of the D3000 processor to implement the X4+X4 signal split mode, its SE_CFG1 and SE_CFG2 must be detected as 11 during power-on detection. To this end, the R0 and R1 resistors on the motherboard can be set to 10KΩ, and the R2 and R3 on the dual M.2 SSD adapter card can be set to 1KΩ. In this way, when the dual M.2 SSD adapter card is inserted into the motherboard, the R0 and R2 resistor voltage divider and the R1 and R3 resistor voltage divider can achieve ID0 and ID1 are both high level 11. At this time, the X8 PCIe on the D3000 processor can achieve X4+X4 signal splitting, and the dual SSD can work normally.
[0061] The slot based on the Feiteng D3000 platform provided in this embodiment sets an identity identification pin for the PCIe X16 slot set on the motherboard, transfers the identity identification signal of the identity identification pin to the configuration pin of the D3000 processor, and the D3000 processor implements the automatic splitting design of X8 PCIe resources according to different level state combinations of the configuration pins, thereby realizing flexible allocation of PCIe resources of the D3000 processor without the need to develop a new motherboard, greatly improving the flexibility of the design, meeting the needs of different configurations, and effectively reducing R&D and manufacturing costs.
[0062] Although the embodiments of the present invention are described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present invention, and such modifications and variations are all within the scope defined by the appended claims.
Claims
1. A slot based on the Feiteng D3000 platform, characterized in that: The slot comprises: A PCIe X16 slot is provided on the mainboard and is connected to the D3000 processor, and is used to connect to a PCIe X8 signal of an X8PCIe controller of the D3000 processor, wherein the PCIe X16 slot is provided with a first identification pin and a second identification pin; A level conversion chip is connected to the PCIe X16 slot, and is used to transfer the first identity identification signal of the first identity identification pin to the first configuration pin of the D3000 processor, and transfer the second identity identification signal of the second identity identification pin to the second configuration pin of the D3000 processor, so that the D3000 processor splits the PCIe X8 signal transmitted to the PCIe X16 slot based on the level state of the configuration pin.
2. The slot according to claim 1, characterized in that: The first identification signal of the first identification pin is grounded through a first resistor, and the second identification signal of the second identification pin is grounded through a second resistor.
3. The slot according to claim 1, characterized in that: The level conversion chip is connected to the P1V8CPU, and the P1V8CPU is used to provide a 1.8V level for the IO pins of the D3000 processor and to provide a 1.8V level for the level conversion chip.
4. The slot according to claim 1, characterized in that: The level conversion chip is connected to P3V3VSB, and the P3V3VSB is used to provide a 3.3V level standby power supply for the mainboard of the D3000 processor and to provide a 3.3V level standby power supply for the level conversion chip.
5. The slot according to claim 2, characterized in that: The slot also includes a dual M.2 SSD adapter card, which is provided with a first M.2 SSD slot, a second M.2 SSD slot, a first adapter card pin corresponding to the first identity identification pin, and a second adapter card pin corresponding to the second identity identification pin.
6. The slot according to claim 5, characterized in that: The first pin signal of the first adapter card pin is pulled up to P3V3VSB through a third resistor, and the first pin signal corresponds to the first identity signal; The second pin signal of the second adapter card pin is pulled up to P3V3VSB through a fourth resistor, and the second pin signal corresponds to the second identity recognition signal.
7. The slot according to claim 5, characterized in that: When the dual M.2 SSD adapter card is not inserted into the PCIe X16 slot, when the mainboard is started, the level states of the first configuration pin and the second configuration pin are both in a low level state, and the PCIe X8 signal transmitted to the PCIe X16 slot is not split.
8. The slot according to claim 6, characterized in that: When the dual M.2 SSD adapter card is inserted into the PCIe X16 slot, when the mainboard is started, the first pin signal corresponds to the first identity identification signal, the second pin signal corresponds to the second identity identification signal, the level states of the first configuration pin and the second configuration pin are both high level states, and the PCIe X8 signal transmitted to the PCIe X16 slot is split into a first PCIe X4 signal and a second PCIe X4 signal.
9. The slot according to claim 8, characterized in that: The first resistor and the third resistor are in a voltage-dividing relationship, and the second resistor and the fourth resistor are in a voltage-dividing relationship.
10. The slot according to claim 8, characterized in that The first M.2 SSD slot corresponds to the first PCIe X4 signal, and the second M.2 SSD slot corresponds to the second PCIe X4 signal.