High density capacitor

Abstract

The high-density capacitor provided by the embodiment of the utility model comprises a bottom electrode with a plurality of non-concentric cylindrical parts, a top electrode comprising a plurality of vertical parts and surrounding parts, and a dielectric layer for separating the top electrode from the bottom electrode. Each of the plurality of non-concentric cylindrical portions includes an inner housing and an outer housing, and each of the plurality of vertical portions is vertically surrounded by the inner housing of the respective cylindrical portion of the bottom electrode. The surrounding portion of the top electrode vertically surrounds each of the plurality of non-concentric cylindrical portions of the bottom electrode, respectively, such that adjacent non-concentric cylindrical portions of the bottom electrode are separated from each other by the surrounding portion of the top electrode. At least some of the plurality of non-concentric cylindrical portions of the bottom electrode include a spatial distribution having a hexagonal symmetry.

Description

Technical Field

[0001] The embodiment of the utility model relates to a high-density capacitor. Background Art

[0002] The semiconductor industry has also grown due to the ever-increasing integration density of various electronic components (e.g., transistors, diodes, resistors, inductors, capacitors, etc.). To a large extent, these increases in integration density have come from the continued reduction in minimum feature size, which has enabled more components to be integrated into a given area. In this regard, individual transistors, interconnects, and related structures have become increasingly smaller, and there is a continuing need to develop new materials, processes, and designs for semiconductor devices and interconnects to enable further advances.

[0003] Since transistors made of oxide semiconductors can be processed at low temperatures and thus fabrication of such devices can be done without causing damage to previously fabricated devices, such transistors are attractive options for back-end-of-line (BEOL) integration. For example, fabrication conditions and fabrication techniques of such transistors using oxide semiconductors can be done without causing damage to previously fabricated front-end-of-line (FEOL) and middle end-of-line (MEOL) devices. Circuits based on oxide semiconductor-based transistor devices can further include other components that can be fabricated in BEOL processes, such as capacitors, inductors, resistors, and integrated passive devices. Utility Model Content

[0004] According to one embodiment of the utility model, a high-density capacitor includes: a bottom electrode having a first cylindrical structure, wherein the first cylindrical structure includes a first inner shell and a first outer shell concentric with the first inner shell; a top electrode including a first vertical portion and a surrounding portion; a dielectric layer separating the top electrode from the bottom electrode; and a barrier layer separating the first inner shell of the bottom electrode from the first outer shell of the bottom electrode. The first vertical portion of the top electrode can be surrounded by the first inner shell of the bottom electrode in the vertical direction, and the surrounding portion surrounds the first outer shell of the bottom electrode in the vertical direction.

[0005] According to one embodiment of the utility model, a high-density capacitor may include a bottom electrode having a plurality of non-concentric cylindrical portions, a top electrode including a plurality of vertical portions and a surrounding portion, and a dielectric layer separating the top electrode from the bottom electrode. Each of the plurality of non-concentric cylindrical portions includes an inner shell and an outer shell, and each of the plurality of vertical portions is surrounded in the vertical direction by the inner shell of the corresponding cylindrical portion of the plurality of non-concentric cylindrical portions of the bottom electrode. The surrounding portion of the top electrode surrounds each of the plurality of non-concentric cylindrical portions of the bottom electrode in the vertical direction, respectively, so that adjacent non-concentric cylindrical portions of the plurality of non-concentric cylindrical portions of the bottom electrode are separated from each other by the surrounding portion of the top electrode. At least some of the plurality of non-concentric cylindrical portions of the bottom electrode include a spatial distribution having hexagonal symmetry. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The aspects of the present disclosure will be best understood when the following detailed description is read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the sizes of various features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 is a vertical cross-sectional view of a first structure after forming a complementary metal oxide semiconductor (CMOS) transistor, a first metal interconnect structure formed in a lower level dielectric material layer, and an isolation dielectric layer according to various embodiments.

[0008] Figure 2A is a horizontal cross-sectional view of a high density capacitor that can be formed in a BEOL process according to various embodiments.

[0009] Figure 2B According to various embodiments Figure 2A A vertical cross-sectional view of a high-density capacitor is shown.

[0010] Figure 3A is a top view of an intermediate structure that may be used in forming a high density capacitor according to various embodiments.

[0011] Figure 3B According to various embodiments Figure 3A A vertical cross-sectional view of the intermediate structure shown.

[0012] Figure 4A is a top view of yet another intermediate structure that may be used in forming a high density capacitor according to various embodiments.

[0013] Figure 4B According to various embodiments Figure 4A A vertical cross-sectional view of the intermediate structure shown.

[0014] Figure 5A is a top view of yet another intermediate structure that may be used in forming a high density capacitor according to various embodiments.

[0015] Figure 5B According to various embodiments Figure 5A A vertical cross-sectional view of the intermediate structure shown.

[0016] Fig. 6A is a horizontal cross-sectional view of yet another intermediate structure that may be used in forming a high density capacitor according to various embodiments.

[0017] Figure 6B According to various embodiments Fig. 6A A vertical cross-sectional view of the intermediate structure shown.

[0018] Fig. 7A is a horizontal cross-sectional view of yet another intermediate structure that may be used in forming a high density capacitor according to various embodiments.

[0019] Figure 7B According to various embodiments Fig. 7A A vertical cross-sectional view of the intermediate structure shown.

[0020] Fig. 8A is a horizontal cross-sectional view of yet another intermediate structure that may be used in forming a high density capacitor according to various embodiments.

[0021] Figure 8B According to various embodiments Fig. 8A A vertical cross-sectional view of the intermediate structure shown.

[0022] Fig. 9A is a horizontal cross-sectional view of yet another intermediate structure that may be used in forming a high density capacitor according to various embodiments.

[0023] Fig. 9B According to various embodiments Fig. 9A A vertical cross-sectional view of the intermediate structure shown.

[0024] Fig. 10A is a horizontal cross-sectional view of yet another intermediate structure that may be used in forming a high density capacitor according to various embodiments.

[0025] Fig. 10B According to various embodiments Fig. 10A A vertical cross-sectional view of the intermediate structure shown.

[0026] Fig.11A is a horizontal cross-sectional view of yet another intermediate structure that may be used in forming a high density capacitor according to various embodiments.

[0027] Fig. 11B According to various embodiments Fig.11A A vertical cross-sectional view of the intermediate structure shown.

[0028] Fig. 12A is a horizontal cross-sectional view of yet another intermediate structure that may be used in forming a high density capacitor according to various embodiments.

[0029] Fig. 12B According to various embodiments Fig. 12A A vertical cross-sectional view of the intermediate structure shown.

[0030] Fig.13A is a horizontal cross-sectional view of yet another intermediate structure that may be used in forming a high density capacitor according to various embodiments.

[0031] Fig. 13B According to various embodiments Fig.13A A vertical cross-sectional view of the intermediate structure shown.

[0032] Fig.14A is a horizontal cross-sectional view of yet another intermediate structure that may be used in forming a high density capacitor according to various embodiments.

[0033] Fig. 14B According to various embodiments Fig.14A A vertical cross-sectional view of the intermediate structure shown.

[0034] Fig.15A is a top view of yet another intermediate structure that may be used in forming a high density capacitor according to various embodiments.

[0035] Fig. 15B According to various embodiments Fig.15A A vertical cross-sectional view of the intermediate structure shown.

[0036] Fig.16A is a top view of yet another intermediate structure that may be used in forming a high density capacitor according to various embodiments.

[0037] Fig. 16B According to various embodiments Fig.16A A vertical cross-sectional view of the intermediate structure shown.

[0038] Fig.17A is a top view of yet another intermediate structure that may be used in forming a high density capacitor according to various embodiments.

[0039] Fig. 17B According to various embodiments Fig.17A A vertical cross-sectional view of the intermediate structure shown.

[0040] Fig.18A is a top view of yet another intermediate structure that may be used in forming a high density capacitor according to various embodiments.

[0041] Fig.18B According to various embodiments Fig.18A A vertical cross-sectional view of the intermediate structure shown.

[0042] Fig.19A is a top view of yet another intermediate structure that may be used in forming a high density capacitor according to various embodiments.

[0043] Fig.19B According to various embodiments Fig.19A A vertical cross-sectional view of the intermediate structure shown.

[0044] Fig. 20A is a top view of yet another intermediate structure that may be used in forming a high density capacitor according to various embodiments.

[0045] Fig. 20B According to various embodiments Fig. 20A A vertical cross-sectional view of the intermediate structure shown.

[0046] Fig.21A According to various embodiments Figure 2A and Figure 2B A top view of the high-density capacitor shown.

[0047] Fig.21B According to various embodiments Figure 2A , Figure 2B and Fig.21A A vertical cross-sectional view of a high-density capacitor is shown.

[0048] Fig.22A is a top view of yet another high density capacitor that can be formed in a BEOL process according to various embodiments.

[0049] Fig. 22B According to various embodiments Fig.22A A vertical cross-sectional view of a high-density capacitor is shown.

[0050] Fig.23A According to various embodiments, Fig.22A and Fig. 22B A vertical cross-sectional view of an intermediate structure that may be used when a high density capacitor is shown.

[0051] Fig. 23B According to various embodiments, Fig.22A and Fig. 22B A vertical cross-sectional view of yet another intermediate structure that may be used as a high density capacitor is shown.

[0052] Fig.24 is a flow chart illustrating the operations of a method of forming a high density capacitor in accordance with various embodiments. DETAILED DESCRIPTION

[0053] The following disclosure provides many different embodiments or examples for implementing the different features of the utility model. The specific examples of components and configurations described below are for simplifying the disclosure. Of course, these components and configurations are only examples and are not intended to be restrictive. For example, in the following description, forming a first feature above or on a second feature may include an embodiment in which the first feature and the second feature are directly contacted, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be directly in contact. In addition, the disclosure may repeat the figure numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0054] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," and the like may be used herein to describe the relationship of one component or feature to another component or feature as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of a component in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.

[0055] Various embodiments of the present disclosure provide high-density capacitors and methods of forming the same, which can be advantageous in terms of manufacturing flexibility, size reduction, and providing increased capacitance. In this regard, the high-density capacitors can be formed in a BEOL process and can be incorporated with other BEOL circuit components (e.g., thin-film transistor (TFT) devices). As such, various embodiments of high-density capacitors can include materials that can be processed at low temperatures. Therefore, making such capacitors can cause no damage to previously made devices (e.g., FEOL devices and MEOL devices). Embodiments of the high-density capacitor include a bottom electrode and a top electrode, the bottom electrode having a plurality of non-concentric cylindrical portions, each of the plurality of non-concentric cylindrical portions having a diameter less than or equal to 0.1 microns, and the top electrode having a vertical portion surrounded in a vertical direction by the non-concentric cylindrical portions of the bottom electrode. In addition, the vertical portions are separated from each other by a separation distance that is also less than or equal to 0.2 microns. In some embodiments, the plurality of non-concentric cylindrical portions may have a spatial distribution with hexagonal symmetry, which enables the cylindrical portions to be tightly packed. As such, the bottom electrode and the top electrode form a densely packed capacitor structure that is compatible with other circuit components formed in BEOL processing operations.

[0056] An embodiment of a high-density capacitor includes: a bottom electrode having a first cylindrical structure, the first cylindrical structure including a first inner shell and a first outer shell concentric with the first inner shell; a top electrode including a first vertical portion and a surrounding portion; a dielectric layer separating the top electrode from the bottom electrode; and a barrier layer separating the first inner shell of the bottom electrode from the first outer shell of the bottom electrode. The first vertical portion of the top electrode may be surrounded by the first inner shell of the bottom electrode in a vertical direction, and the surrounding portion surrounds the first outer shell of the bottom electrode in a vertical direction. According to an embodiment, the bottom electrode may include a second cylindrical structure that is not concentric with the first cylindrical structure, the second cylindrical structure includes a second inner shell and a second outer shell concentric with the second inner shell, and the top electrode includes a second vertical portion surrounded by the second inner shell of the bottom electrode in a vertical direction, and the surrounding portion surrounds the second outer shell of the bottom electrode in a vertical direction. The first vertical portion of the top electrode and the second vertical portion of the top electrode are separated from each other by a separation distance less than or equal to 0.2 microns.

[0057] In yet another embodiment, a high-density capacitor may include a bottom electrode having a plurality of non-concentric cylindrical portions, a top electrode including a plurality of vertical portions and a surrounding portion, and a dielectric layer separating the top electrode from the bottom electrode. Each of the plurality of non-concentric cylindrical portions includes an inner shell and an outer shell, and each of the plurality of vertical portions is surrounded in a vertical direction by the inner shell of the corresponding cylindrical portion of the bottom electrode. The surrounding portion of the top electrode surrounds each of the plurality of non-concentric cylindrical portions of the bottom electrode in a vertical direction, respectively, so that adjacent non-concentric cylindrical portions of the bottom electrode are separated from each other by the surrounding portion of the top electrode. At least some of the plurality of non-concentric cylindrical portions of the bottom electrode include a spatial distribution having hexagonal symmetry.

[0058] In another embodiment, a method of forming a high-density capacitor may include: etching an interlayer dielectric layer to produce a plurality of pillar structures; depositing a first conductive material on the plurality of pillar structures and surrounding areas to produce a plurality of outer shells of a bottom electrode; etching the plurality of pillar structures to form a plurality of cavities in the plurality of pillar structures; depositing a second conductive material in the plurality of cavities to produce a plurality of inner shells of a bottom electrode; depositing a dielectric layer on the bottom electrode; and depositing a third conductive material on the dielectric layer to produce a plurality of vertical portions and surrounding portions of a top electrode. The embodiment method may further include: forming a barrier layer on the plurality of pillar structures and surrounding areas before depositing the first conductive material on the plurality of pillar structures and surrounding areas; electrically connecting the bottom electrode to a first interconnect structure formed below the high-density capacitor; and electrically connecting the top electrode to a second interconnect structure formed above the high-density capacitor.

[0059] Figure 1 A semiconductor structure 100 according to various embodiments is shown. The semiconductor structure 100 includes a substrate 102, which may be a semiconductor substrate (e.g., a commercially available silicon substrate). The substrate 102 may include a semiconductor material layer 104 or include a semiconductor material layer 104 at least at an upper portion of the substrate 102. The semiconductor material layer 104 may be a surface portion of a bulk semiconductor substrate or may be a top semiconductor layer of a semiconductor-on-insulator (SOI) substrate. In one embodiment, the semiconductor material layer 104 may include a single crystalline semiconductor material (e.g., single crystalline silicon). In one embodiment, the substrate 102 may include a single crystalline silicon substrate including a single crystalline silicon material.

[0060] A shallow trench isolation structure 106 including a dielectric material (e.g., silicon oxide) may be formed in an upper portion of the semiconductor material layer 104. A properly doped semiconductor well (e.g., a p-type well and an n-type well) may be formed in each region laterally enclosed by a portion of the shallow trench isolation structure 106. A field effect transistor 108 may be formed over the top surface of the semiconductor material layer 104. For example, each of the field effect transistors 108 may include a source electrode 110, a drain electrode 112, a semiconductor channel 114 including a surface portion of the substrate 102 extending between the source electrode 110 and the drain electrode 112, and a gate structure 116. The semiconductor channel 114 may include a single crystalline semiconductor material.

[0061] Each gate structure 116 may include a gate dielectric layer 118, a gate electrode 120, a gate cap dielectric 122, and a dielectric gate spacer 124. A source-side metal-semiconductor alloy region 126 may be formed on each source electrode 110, and a drain-side metal-semiconductor alloy region 128 may be formed on each drain electrode 112. The devices formed on the top surface of the semiconductor material layer 104 may include complementary metal-oxide-semiconductor (CMOS) transistors and optional additional semiconductor devices (e.g., resistors, diodes, capacitors, etc.) and are collectively referred to as CMOS circuitry 134.

[0062] Figure 1 The semiconductor structure 100 shown may include a memory array region 130, and a memory cell array may be subsequently formed in the memory array region 130. The first exemplary structure may further include a peripheral region 132 in which metal wiring for the memory device array is disposed. Generally speaking, the field effect transistor 108 in the CMOS circuit system 134 may be electrically connected to the electrode of the corresponding memory cell through a corresponding set of metal interconnect structures.

[0063] The devices in the peripheral region 132 (e.g., field effect transistors 108) can provide functions for operating a memory cell array to be formed later. Specifically, the devices in the peripheral region can be configured to control programming operations, erasing operations, and sensing (reading) operations of the memory cell array. For example, the devices in the peripheral region 132 can include sensing circuit systems and / or programming circuit systems.

[0064] One or more of the field effect transistors 108 in the CMOS circuit system 134 may include a semiconductor channel 114 containing a portion of the semiconductor material layer 104 located in the substrate 102. In an embodiment in which the semiconductor material layer 104 includes a single crystalline semiconductor material (e.g., single crystalline silicon), the semiconductor channel 114 of each of the field effect transistors 108 in the CMOS circuit system 134 may include a single crystalline semiconductor channel (e.g., a single crystalline silicon channel). In one embodiment, a plurality of field effect transistors 108 in the CMOS circuit system 134 may include a corresponding node, which is then electrically connected to a node of a corresponding memory cell to be formed subsequently. For example, a plurality of field effect transistors 108 in the CMOS circuit system 134 may include a corresponding source electrode 110 or a corresponding drain electrode 112, which is then electrically connected to a node of a corresponding memory cell to be formed subsequently.

[0065] In one embodiment, the CMOS circuit system 134 may include a programming control circuit configured to control the gate voltage of a group of field effect transistors 108 and control the gate voltage of transistors (e.g., thin film transistors) to be formed subsequently. The group of field effect transistors 108 may be used to program corresponding memory cells (e.g., ferroelectric memory cells). In this embodiment, the programming control circuit may be configured to provide a first programming pulse, the first programming pulse programs the corresponding ferroelectric dielectric material layer in the selected ferroelectric memory cell to a first polarization state, in which the electrical polarization in the ferroelectric dielectric material layer is directed toward the first electrode of the selected ferroelectric memory cell, and the programming control circuit may be configured to provide a second programming pulse, the second programming pulse programs the ferroelectric dielectric material layer in the selected ferroelectric memory cell to a second polarization state, in which the electrical polarization in the ferroelectric dielectric material layer is directed toward the second electrode of the selected ferroelectric memory cell.

[0066] In one embodiment, the substrate 102 may include a single crystal silicon substrate, and the field effect transistor 108 may include a corresponding portion of the single crystal silicon substrate as a semiconducting channel. As used herein, a "semiconducting" device refers to a device with a conductivity ranging from 1.0×10 -6 Siemens / cm (S / cm) to 1.0×105 Siemens / cm. As used herein, "semiconductor material" refers to a semiconductor material having an electrical conductivity ranging from 1.0×10 -6 Siemens / cm to 1.0×10 5 Siemens / cm range, and when appropriately doped with electrical dopants, can produce conductivity ranging from 1.0 Siemens / cm to 1.0×10 5 Siemens / cm range for doped materials.

[0067] According to an embodiment, the field effect transistor 108 may then be electrically connected to a drain electrode and a gate electrode of an access transistor, the access transistor comprising a semiconductive metal oxide plate to be formed above the field effect transistor 108. In one embodiment, a subset of the field effect transistors 108 may then be electrically connected to at least one of the drain electrode and the gate electrode. For example, the field effect transistor 108 may include a first word line driver configured to apply a first gate voltage to a first word line via a first subset of a lower level metal interconnect structure to be formed later, and a second word line driver configured to apply a second gate voltage to a second word line via a second subset of a lower level metal interconnect structure to be formed later. In addition, the field effect transistor 108 may include a bit line driver configured to apply a bit line bias voltage to a bit line to be formed later, and a sense amplifier configured to detect a current flowing through the bit line during a read operation.

[0068] Various metal interconnect structures formed in the dielectric material layer may then be formed over the substrate 102 and the semiconductor device (e.g., field effect transistor 108) located on the substrate 102. In an exemplary embodiment, the dielectric material layer may include, for example, a first dielectric material layer 136, a first interconnect level dielectric material layer 138, and a second interconnect level dielectric material layer 140. The first dielectric material layer 136 may be a layer that surrounds the contact structure connected to the source and the drain in a vertical direction (sometimes referred to as a contact level dielectric material layer). The metal interconnect structure may include a device contact via structure (e.g., metal interconnect structure 142) formed in the first dielectric material layer 136 and contacting corresponding components of the CMOS circuit system 134, a first metal line structure (e.g., metal interconnect structure 144) formed in the first interconnect level dielectric material layer 138, a first metal via structure (e.g., metal interconnect structure 146) formed in the lower portion of the second interconnect level dielectric material layer 140, and a second metal line structure (e.g., metal interconnect structure 148) formed in the upper portion of the second interconnect level dielectric material layer 140.

[0069] Each of the dielectric material layers (e.g., dielectric material layers 136, 138, 140) may include a dielectric material such as undoped silicate glass, doped silicate glass, organosilicate glass, amorphous fluorinated carbon, porous variants thereof, or combinations thereof. Each of the metal interconnect structures (e.g., metal interconnect structures 142, 144, 146, 148) may include at least one conductive material, which may be a combination of a metal liner (e.g., a metal nitride or a metal carbide) and a metal fill material. Each metal liner may include TiN, TaN, WN, TiC, TaC, and WC, and each metal fill material portion may include W, Cu, Al, Co, Ru, Mo, Ta, Ti, TiN, alloys thereof, and / or combinations thereof.

[0070] Other suitable metal liner and metal fill materials may also be used within the contemplated scope of the present disclosure. In one embodiment, the first metal via structure (e.g., metal interconnect structure 146) and the second metal line structure (e.g., metal interconnect structure 148) may be formed as an integrated line and via structure by a dual damascene process. The dielectric material layer (e.g., dielectric material layers 136, 138, 140) is referred to herein as a lower level dielectric material layer. The metal interconnect structure (e.g., metal interconnect structures 142, 144, 146, 148) formed in the lower level dielectric material layer is referred to herein as a lower level metal interconnect structure.

[0071] Although the present disclosure is described using embodiments in which a memory cell array may be formed above the second line and via level dielectric material layer 140, embodiments in which a memory cell array may be formed at a different metal interconnect level are expressly contemplated herein.

[0072] A thin film transistor array and a ferroelectric memory cell (or other type of memory cell) array may be subsequently deposited on the dielectric material layer (e.g., dielectric material layers 136, 138, 140) in which the metal interconnect structures (e.g., metal interconnect structures 142, 144, 146, 148) have been formed. The collection of all dielectric material layers formed before forming the thin film transistor array or the ferroelectric memory cell array is collectively referred to as the lower level dielectric material layer (e.g., dielectric material layers 136, 138, 140). The collection of all metal interconnect structures formed in the lower level dielectric material layer (e.g., dielectric material layers 136, 138, 140) is referred to herein as the first metal interconnect structure (e.g., metal interconnect structures 142, 144, 146, 148). Generally, first metal interconnect structures (eg, metal interconnect structures 142 , 144 , 146 , 148 ) formed in at least one lower level dielectric material layer (eg, dielectric material layers 136 , 138 , 140 ) may be formed above semiconductor material layer 104 in substrate 102 .

[0073] According to an embodiment, a thin film transistor may then be formed in a metal interconnect level overlying the metal interconnect level containing the lower level dielectric material layer (e.g., dielectric material layers 136, 138, 140) and the first metal interconnect structure (e.g., metal interconnect structures 142, 144, 146, 148). In one embodiment, a planar dielectric material layer having a uniform thickness may be formed over the lower level dielectric material layer (e.g., dielectric material layers 136, 138, 140). The planar dielectric material layer is referred to herein as an insulating matrix layer 150. The insulating matrix layer 150 may include a dielectric material, such as undoped silicate glass, doped silicate glass, organosilicate glass, or a porous dielectric material, and the insulating matrix layer 150 may be deposited by chemical vapor deposition. The thickness of the insulating matrix layer 150 may range from 20 nanometers (ie, 200 angstroms) to 300 nanometers (ie, 3000 angstroms), although lesser thicknesses and greater thicknesses may also be used.

[0074] Generally, an interconnect level dielectric layer (e.g., a lower level dielectric material layer (e.g., dielectric material layers 136, 138, 140)) containing a metal interconnect structure (e.g., a first metal interconnect structure (e.g., metal interconnect structures 142, 144, 146, 148)) may be formed over the semiconductor device. An insulating matrix layer 150 may be formed over the interconnect level dielectric layer. Other passive devices may be formed in the BEOL process. For example, various capacitors, inductors, resistors, and integrated passive devices may be utilized with other BEOL devices.

[0075] Figure 2A is a horizontal cross-sectional view of a high density capacitor 200 that may be formed in a BEOL process according to various embodiments, and Figure 2B According to various embodiments Figure 2A A vertical cross-sectional view of a high-density capacitor 200 is shown. Figure 2A The plane bounded by the horizontal section view shown is Figure 2B The cross section A-A' in the figure indicates that Figure 2B The plane bounded by the vertical section view shown is Figure 2A The high-density capacitor 200 may be formed on one or more interconnect-level dielectric layers (e.g., lower-level dielectric material layers (e.g., dielectric material layers 136, 138, 140)) containing metal interconnect structures (e.g., first metal interconnect structures (e.g., metal interconnect structures 142, 144, 146, 148)). For example, the high-density capacitor 200 may be formed on an insulating matrix layer 150 (e.g., see Figure 1) or formed on one or more additional interconnect layers formed on the insulating matrix layer 150, as described in more detail below.

[0076] like Figure 2A and Figure 2B As shown in , the high-density capacitor 200 may include a bottom electrode (e.g., bottom electrodes 204a, 204b) having a plurality of non-concentric cylindrical portions 202 that are not concentric with each other. Each of the plurality of non-concentric cylindrical portions 202 may include an inner shell 204a and an outer shell 204b that is concentric with the inner shell 204a. In various embodiments, the inner shell 204a and the outer shell 204b may each include a conductive material having a thickness less than or equal to 10 nanometers. The high-density capacitor 200 may also include a top electrode having a plurality of vertical portions 206a and a surrounding portion 206b. According to various embodiments, the bottom electrode (including the inner shell 204a and the inner shell 204a) and the top electrode (having a plurality of vertical portions 206a and a surrounding portion 206b) each include a conductive material, such as one or more of TiN, TaN, WN, TiC, TaC, and WC. Other embodiments may include various other conductive materials (conducting material).

[0077] like Figure 2A and Figure 2B As shown in , each of the plurality of vertical portions 206a of the top electrode (having a plurality of vertical portions 206a and surrounding portions 206b) may be surrounded by the inner shell 204a of the corresponding cylindrical portion 202 of the bottom electrode (including the inner shell 204a and the inner shell 204a) in the vertical direction, and the surrounding portions 206b of the top electrode (having a plurality of vertical portions 206a and surrounding portions 206b) respectively surround each of the plurality of non-concentric cylindrical portions 202 of the bottom electrode (including the inner shell 204a and the inner shell 204a) in the vertical direction. In this regard, adjacent non-concentric cylindrical portions 202 of the bottom electrode (including the inner shell 204a and the inner shell 204a) may be separated from each other by the surrounding portions 206b of the top electrode (having a plurality of vertical portions 206a and surrounding portions 206b). In various embodiments, adjacent vertical portions 206 a of the plurality of vertical portions 206 a may be separated from one another by a separation distance 212 that may be less than or equal to 0.2 microns.

[0078] A dielectric layer (eg, first concentric portion 210a, second concentric portion 210b) may separate the top electrode (having a plurality of vertical portions 206a and surrounding portions 206b) from the bottom electrode (including inner shell 204a and inner shell 204a). In this regard, the dielectric layer (e.g., first concentric portion 210a, second concentric portion 210b) may include first concentric portion 210a and second concentric portion 210b, the first concentric portion 210a separating each of the plurality of vertical portions 206a of the top electrode (having a plurality of vertical portions 206a and surrounding portions 206b) from the inner shell 204a of the bottom electrode (including the inner shell 204a and the inner shell 204a), and the second concentric portion 210b separating the outer shell 204b of the bottom electrode (including the inner shell 204a and the inner shell 204a) from the surrounding portion 206b of the top electrode (having a plurality of vertical portions 206a and the surrounding portion 206b). In various embodiments, the diameter 214 of the second concentric portion 210b may be less than or equal to 0.2 microns. In various embodiments, the dielectric layer (e.g., the first concentric portion 210a, the second concentric portion 210b) may include a high-k dielectric material including one or more of hafnium oxide, hafnium silicon oxide, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, zirconium oxide, titanium oxide, aluminum oxide, and hafnium dioxide-aluminum oxide. Figure 2A As shown in , at least some of the plurality of non-concentric cylindrical portions 202 of the bottom electrode (including the inner shell 204a and the inner shell 204a) may include a spatial distribution having hexagonal symmetry. In various other embodiments, the plurality of non-concentric cylindrical portions 202 may be arranged to have a spatial distribution having various other symmetries or no particular symmetry. Figure 2A and Figure 2B As shown in FIG. 1 , in some embodiments, when a plurality of non-concentric cylindrical portions 202 having a first symmetry (e.g., hexagonal) are placed in a region having a second symmetry (e.g., rectangular), one or more dielectric spacer regions 215 may be formed, as described below with reference to FIG. Fig.14A and Fig. 14B Elaborate in more detail.

[0079] like Figure 2A and Figure 2B As shown in , the high-density capacitor 200 may further include a barrier layer 216, which separates the inner shell 204a of the bottom electrode (including the inner shell 204a and the inner shell 204a) from the outer shell 204b of the bottom electrode (including the inner shell 204a and the inner shell 204a). The barrier layer 216 may include a conductive material, such as Ta and / or TaN. In this way, the barrier layer 216 can form a conductive connection with the bottom electrode (including the inner shell 204a and the inner shell 204a). In addition, as Figure 2B As shown in , the barrier layer 216 can form a conductive connection with the first interconnect structure 218a. In this way, the bottom electrode (including the inner shell 204a and the inner shell 204a) can be electrically connected to the first interconnect structure 218a that can be disposed below the high-density capacitor 200. In this way, the high-density capacitor 200 can be disposed on the interlayer dielectric layer 220 including the interconnect structure 218a. Similarly, the top electrode (having a plurality of vertical portions 206a and a surrounding portion 206b) can be electrically connected to the second interconnect structure 218b formed above the high-density capacitor 200.

[0080] The non-concentric cylindrical portion 202 is Figure 2A and Figure 2B The specific arrangement in the high-density capacitor 200 shown is provided only as an exemplary embodiment. Various other embodiments may include a bottom electrode (including the inner shell 204a and the inner shell 204a) containing more or fewer non-concentric cylindrical portions 202, and the non-concentric cylindrical portions 202 may have different spatial configurations. For example, the embodiment high-density capacitor 200 includes a plurality of non-concentric cylindrical portions 202 including fifteen non-concentric cylindrical portions 202. In addition, the plurality of non-concentric cylindrical portions 202 may be arranged so that at least some of the plurality of non-concentric cylindrical portions 202 of the bottom electrode (including the inner shell 204a and the inner shell 204a) have a spatial distribution with hexagonal symmetry, for example Figure 2A as shown in .

[0081] Other embodiments may include other numbers of non-concentric cylindrical portions 202 arranged in various ways with or without a particular symmetry (e.g., square, rectangular, etc.). For example, some embodiments may include a bottom electrode (including an inner shell 204a and an outer shell 204a) that includes a single cylindrical portion 202, two non-concentric cylindrical portions 202, three non-concentric cylindrical portions 202, etc. Each such embodiment may include a top electrode (having a plurality of vertical portions 206a and surrounding portions 206b) having a corresponding number of vertical portions 206a (e.g., one vertical portion 206a, two vertical portions 206a, three vertical portions 206a, etc.) and surrounding portions 206b. In addition, other embodiments may include non-concentric cylindrical portions 202 having different configurations. For example, although each of the above-described embodiments includes a non-concentric cylindrical portion 202 having an inner shell 204a and an outer shell 204b, other embodiments may not be so limited. For example, other embodiments may include a non-concentric cylindrical portion 202 having an inner shell 204a, an outer shell 204b, and one or more additional shells (not shown) formed between the inner shell 204a and the outer shell 204b. For example, the non-concentric cylindrical portion 202 may include three shells, four shells, etc.

[0082] These additional embodiments may further include one or more dielectric layers 210 separating the bottom electrode (including the inner shell 204a and the inner shell 204a) from the top electrode (having multiple vertical portions 206a and surrounding portions 206b) and one or more barrier layers 216 separating one or more of the bottom electrode (including the inner shell 204a and the inner shell 204a) and the top electrode (having multiple vertical portions 206a and surrounding portions 206b) from one or more interconnect structures (e.g., interconnect structures 218a, 218b) formed respectively below or above the high-density capacitor 200. In still other embodiments, both the bottom electrode (including the inner shell 204a and the inner shell 204a) and the top electrode (having a plurality of vertical portions 206a and a surrounding portion 206b) can be electrically connected to the interconnect structure 218a formed below the high-density capacitor 200, or both the bottom electrode (including the inner shell 204a and the inner shell 204a) and the top electrode (having a plurality of vertical portions 206a and a surrounding portion 206b) can be electrically connected to the interconnect structure 218b formed above the high-density capacitor 200. The following references can be used. FIG. 3A to FIG. 23B The operations described in greater detail are used to form the above-described embodiments including high density capacitor 200 and variations including different numbers and configurations of cylindrical portions.

[0083] Figure 3Ais a top view of an intermediate structure 300 that may be used in forming a high-density capacitor (eg, high-density capacitors 200, 2200) according to various embodiments, and Figure 3B According to various embodiments Figure 3A A vertical cross-sectional view of the intermediate structure 300 is shown. Figure 3B The plane bounded by the vertical section view shown is Figure 3A The cross section BB' in FIG. Figure 3A The area of ​​the intermediate structure 300 shown in the top view is composed of Figure 3B The intermediate structure 300 may include the interlayer dielectric layer 220, the first boundary layer 302a, the first dielectric layer 304a, the second boundary layer 302b, the second dielectric layer 304b, the third boundary layer 302c and the third dielectric layer 304c. The intermediate structure 300 may further include a hard mask layer 306L and a patterned photoresist 308.

[0084] The interlayer dielectric layer 220, the first boundary layer 302a, the first dielectric layer 304a, the second boundary layer 302b, the second dielectric layer 304b, the third boundary layer 302c, the third dielectric layer 304c, and the hard mask layer 306L can each be formed as a flat blanket (i.e., unpatterned) layer having a corresponding flat top surface and a corresponding flat bottom surface. The intermediate structure 300 can be formed in a BEOL process. In this way, the interlayer dielectric layer 220 can be a dielectric layer (e.g., a dielectric layer) in which one or more interconnect structures 218a can be embedded. Figure 1 The one or more interconnect structures 218a may be electrically connected to various interconnect structures (e.g., Figure 1 The one or more interconnect structures 218a may include at least one conductive material, which may be a combination of a metal liner (e.g., a metal nitride or a metal carbide) and a metal filler material. Each metal liner may include TiN, TaN, WN, TiC, TaC, and WC, and each metal filler material portion may include W, Cu, Al, Co, Ru, Mo, Ta, Ti, alloys thereof, and / or combinations thereof. Other suitable materials within the contemplated scope of the present disclosure may also be used.

[0085] Each of the interlayer dielectric layer 220, the first dielectric layer 304a, the second dielectric layer 304b, and the third dielectric layer 304c may include, for example, undoped silicate glass, doped silicate glass (e.g., deposited by decomposing tetraethylorthosilicate (TEOS)), organic silicate glass, silicon oxynitride, or silicon carbonitride. Other dielectric materials are also within the contemplated scope of the present disclosure. The dielectric material of the interlayer dielectric layer 220, the dielectric material of the first dielectric layer 304a, the dielectric material of the second dielectric layer 304b, and the dielectric material of the third dielectric layer 304c may be deposited by a conformal deposition process (e.g., a chemical vapor deposition process) or a self-planarizing deposition process (e.g., spin coating). The thickness of the interlayer dielectric layer 220, the thickness of the first dielectric layer 304a, the thickness of the second dielectric layer 304b, and the thickness of the third dielectric layer 304c may each range from approximately 15 nanometers to approximately 60 nanometers (e.g., from approximately 20 nanometers to approximately 40 nanometers), but smaller thicknesses and larger thicknesses may also be used.

[0086] Each of the first boundary layer 302a, the second boundary layer 302b, and the third boundary layer 302c may include an etch stop material such as silicon nitride, silicon carbide, silicon carbonitride, or a dielectric metal oxide such as aluminum oxide, titanium oxide, tantalum oxide, etc. In an exemplary embodiment, the first boundary layer 302a and the third boundary layer 302c may include silicon carbide, and the second boundary layer 302b may include silicon nitride. The first boundary layer 302a, the second boundary layer 302b, and the third boundary layer 302c may be deposited by a conformal deposition process or a non-conformal deposition process. In one embodiment, the first boundary layer 302a, the second boundary layer 302b, and the third boundary layer 302c may be deposited by chemical vapor deposition, atomic layer deposition, or physical vapor deposition. The thickness of the first boundary layer 302a, the thickness of the second boundary layer 302b, and the thickness of the third boundary layer 302c may each range from approximately 2 nanometers to approximately 20 nanometers, such as from approximately 3 nanometers to approximately 12 nanometers, although smaller thicknesses and larger thicknesses may also be used.

[0087] The hard mask layer 306L may include a conductive material such as TiN. Alternatively, the hard mask layer 306L may include any suitable material, such as amorphous carbon, amorphous hydrogenated carbon, an organosiloxane-based material, SiN, SiON, or a combination thereof. The hard mask layer 306L may be formed as a flat blanket (i.e., unpatterned) layer having a flat top surface and a flat bottom surface, and the hard mask layer 306L may be formed using chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any other suitable process. The patterned photoresist 308 may be formed by depositing a blanket layer of photoresist material (not shown), which may then be patterned using photolithography techniques. The patterned photoresist 308 may then be used as a mask while patterning the hard mask layer 306L to form a patterned hard mask 306, as described below with reference to Figure 4A and Figure 4B Further details. Figure 3A As shown in , for example, the patterned photoresist 308 may expose a rectangular portion of the hard mask layer 306L while covering a plurality of circular regions of the hard mask layer 306L. As shown, at least some of the circular regions may have a spatial distribution with hexagonal symmetry.

[0088] Figure 4A is a top view of yet another intermediate structure 400 that may be used in forming a high-density capacitor (eg, high-density capacitors 200, 2200) according to various embodiments, and Figure 4B According to various embodiments Figure 4A A vertical cross-sectional view of the intermediate structure 400 is shown. Figure 4B The plane bounded by the vertical section view shown is Figure 4A The cross section BB' in FIG. Figure 4A The area of ​​the intermediate structure 400 shown in the top view is composed of Figure 4B The third dielectric layer 304c can be formed by performing anisotropic etching selective to the hard mask layer 306L. Figure 3A and Figure 3B The intermediate structure 300 is formed into the intermediate structure 400. In this way, a patterned hard mask 306 can be formed. Figure 4A As shown in , the process of etching the hard mask layer 306L can produce a patterned hard mask 306, so that the patterned hard mask 306 has an exposed rectangular area and a plurality of circular masking areas corresponding to the circular masking areas of the patterned photoresist 308. The patterned hard mask 306 can then be used to further etch the structure, as described below with reference to Figure 5A and Figure 5B Elaborate in more detail.

[0089] Figure 5Ais a top view of yet another intermediate structure 500 that may be used in forming a high-density capacitor (eg, high-density capacitors 200, 2200) according to various embodiments, and Figure 5B According to various embodiments Figure 5A A vertical cross-sectional view of the intermediate structure 500 is shown. Figure 5B The plane bounded by the vertical section view shown is Figure 5A The cross section BB' in FIG. Figure 5A The area of ​​the intermediate structure 500 shown in the top view is composed of Figure 5B The intermediate structure 400 may be self-removed by etching the intermediate structure 400 using the patterned hard mask 306. Figure 4A and Figure 4B The intermediate structure 400 is shown to form the intermediate structure 500. In this regard, an anisotropic etching process may be performed to etch through the third dielectric layer 304c, the third boundary layer 302c, the second dielectric layer 304b, the second boundary layer 302b, the first dielectric layer 304a, and the first boundary layer 302a. As such, the etching process may produce a plurality of pillar structures 502 in the otherwise exposed rectangular portions of the first interconnect structure 218a.

[0090] Fig. 6A is a horizontal cross-sectional view of yet another intermediate structure 600 that may be used in forming a high density capacitor according to various embodiments, and Figure 6B According to various embodiments Fig. 6A A vertical cross-sectional view of the intermediate structure 600 is shown. Fig. 6A The plane bounded by the horizontal section view shown is Figure 6B The cross section A-A' in the figure indicates that Figure 6B The plane bounded by the vertical section view shown is Fig. 6A The cross section BB' in FIG. 3 may be self-contained by removing the patterned photoresist 308 and forming a barrier layer 216 over the resulting structure. Figure 5A and Figure 5B The intermediate structure 500 is shown to form the intermediate structure 600. In this regard, the patterned photoresist 308 may be removed by ashing or by dissolving using a solvent.

[0091] The barrier layer 216 may include a conductive material, such as Ta and / or TaN. In other embodiments, the barrier layer 216 may include various other conductive layers, such as TiN, WN, TiC, TaC and / or WC. Other suitable conductive materials within the contemplated scope of the present disclosure may also be used. The barrier layer 216 may be deposited to form a conductive contact with the first interconnect structure 218a. The barrier layer 216 may be deposited by a conformal deposition process or a non-conformal deposition process. In one embodiment, the barrier layer 216 may be deposited by chemical vapor deposition, atomic layer deposition, or physical vapor deposition. The thickness of the barrier layer 216 may range from approximately 2 nanometers to approximately 20 nanometers (e.g., from approximately 3 nanometers to approximately 12 nanometers), but smaller thicknesses and larger thicknesses may also be used. For example, in some embodiments, the barrier layer 216 may have a thickness of less than 10 nanometers.

[0092] Fig. 7A is a horizontal cross-sectional view of yet another intermediate structure 700 that may be used in forming a high density capacitor according to various embodiments, and Figure 7B According to various embodiments Fig. 7A A vertical cross-sectional view of the intermediate structure 700 is shown. Fig. 7A The plane bounded by the horizontal section view shown is Figure 7B The cross section A-A' in the figure indicates that Figure 7B The plane bounded by the vertical section view shown is Fig. 7A The cross section BB' in FIG. 6 is indicated by depositing a first conductive layer 702 on the intermediate structure 600. Fig. 6A and Figure 6B The intermediate structure 600 is shown to form an intermediate structure 700. The first conductive layer 702 may include a conductive metal nitride or a conductive metal carbide, such as TiN, TaN, WN, TiC, TaC and / or WC. Other suitable conductive materials within the contemplated scope of the present disclosure may also be used. The first conductive layer 702 may be deposited to form a conductive contact with the barrier layer 216.

[0093] The first conductive layer 702 may be further processed to produce the above reference Figure 2A and Figure 2B The bottom electrode (including the inner shell 204a and some portions of the inner shell 204a) described above. For example, a flat horizontal portion 702a of the first conductive layer 702 can be formed on the corresponding flat horizontal portion 216a of the barrier layer 216. Such flat horizontal portion 216a of the barrier layer can in turn form a conductive contact with the first interconnect structure 218a. Similarly, a cylindrical portion 702b of the first conductive layer 702 can be formed on the cylindrical sidewalls of the pillar structure 502. After further processing, such cylindrical portion 702b of the first conductive layer 702 can form the above reference Figure 2A and Figure 2B The bottom electrode is illustrated as including an outer casing 204b of a corresponding non-concentric cylindrical portion 202 of the inner casing 204a.

[0094] Fig. 8A is a horizontal cross-sectional view of yet another intermediate structure 800 that may be used in forming a high density capacitor according to various embodiments, and Figure 8B According to various embodiments Fig. 8A A vertical cross-sectional view of the intermediate structure 800 is shown. Fig. 8A The plane bounded by the horizontal section view shown is Figure 8B The cross section A-A' in the figure indicates that Figure 8B The plane bounded by the vertical section view shown is Fig. 8A The cross section BB' in FIG. 8 is indicated by forming a first protective layer 802 around the pillar structure 502. Fig. 7A and Figure 7B The intermediate structure 700 is shown to form the intermediate structure 800. The first protective layer 802 can be a polymer material that can have anti-reflective properties for certain wavelengths of optical radiation. For example, the first protective layer 802 can be a photoresist that is sensitive to narrow bandwidth radiation (e.g., mercury i-line radiation). Fig. 7A and Figure 7B A polymer material is deposited over the intermediate structure 700 to form a first protective layer 802. The polymer material may then be etched to expose a top surface of the first conductive layer 702 including top portions of the pillar structures 502.

[0095] Fig. 9A is a horizontal cross-sectional view of yet another intermediate structure 900 that may be used in forming a high density capacitor according to various embodiments, and Fig. 9B According to various embodiments Fig. 9A A vertical cross-sectional view of the intermediate structure 900 is shown. Fig. 9A The plane bounded by the horizontal section view shown is Fig. 9B The cross section A-A' in the figure indicates that Fig. 9B The plane bounded by the vertical section view shown is Fig. 9A The cross section B-B' is indicated in FIG. Fig. 8A and Figure 8B The intermediate structure 800 is formed with a patterned photoresist 308. Fig. 8A and Figure 8B The intermediate structure 800 shown forms the intermediate structure 900. Fig. 9B As shown in FIG. , the patterned photoresist 308 exposes the top portion 902 of the pillar structure 502 while covering the rest of the intermediate structure 900. In this way, the top portion 902 of the pillar structure 502 can be exposed by performing the process described in reference to FIG. Fig. 10A and Fig. 10B The etching process described in more detail is used to remove the top portion 902 of the pillar structure 502 .

[0096] Fig. 10A is a horizontal cross-sectional view of yet another intermediate structure 1000 that may be used in forming a high density capacitor according to various embodiments, and Fig. 10B According to various embodiments Fig. 10A A vertical cross-sectional view of the intermediate structure 1000 is shown. Fig. 10A The plane bounded by the horizontal section view shown is Fig. 10B The cross section A-A' in the figure indicates that Fig. 10B The plane bounded by the vertical section view shown is Fig. 10A The top portion 902 of the pillar structure 502 may be removed by performing an etching operation (eg, see Fig. 9B ) and then remove the patterned photoresist 308 and the first protective layer 802 to Fig. 9A and Fig. 9B The intermediate structure 900 is shown forming the intermediate structure 1000 .

[0097] In this regard, an anisotropic etching process may be performed to remove a top portion of the first conductive layer 702, a top portion of the barrier layer 216, and some portions of the patterned hard mask 306. Fig. 10B As shown in , the etching process may expose the top cylindrical portion 1002 of the pillar structure 502. When the etching process is completed, the patterned photoresist 308 and the first protective layer 802 may be removed (eg, by ashing or by dissolving using a solvent). Fig. 10B As shown in FIG. 1 , for example, removing the top portion 902 of the pillar structure 502 converts the cylindrical portion 702 b of the first conductive layer 702 into the cylindrical portion 702 b of the first conductive layer 702 as shown in FIG. Figure 2A and Figure 2B The bottom electrode (including the inner shell 204a and the corresponding outer shell 204b of the cylindrical portion 202 of the inner shell 204a) is illustrated. In an additional processing operation, the top cylindrical portion 1002 of the pillar structure 502 and the cylindrical portion 1004 of the third boundary layer 302c and the cylindrical portion 1006 of the second dielectric layer 304b can be selectively etched, as described below with reference to Fig.11A and Fig. 11B Elaborate in more detail.

[0098] Fig.11A is a horizontal cross-sectional view of yet another intermediate structure 1100 that may be used in forming a high density capacitor according to various embodiments, and Fig. 11B According to various embodiments Fig.11A A vertical cross-sectional view of the intermediate structure 1100 is shown. Fig.11AThe plane bounded by the horizontal section view shown is Fig. 11B The cross section A-A' in the figure indicates that Fig. 11B The plane bounded by the vertical section view shown is Fig.11A The cylindrical portion of the pillar structure 502 (including the top cylindrical portion 1002, the cylindrical portion 1004 of the third boundary layer 302c, and the cylindrical portion 1006 of the second dielectric layer 304b (see, for example, Fig. 10A and Fig. 10B )) is etched and Fig. 10A and Fig. 10B The intermediate structure 1000 is formed into an intermediate structure 1100. In this way, the etching process can produce a plurality of cylindrical cavities 1102 in the pillar structure 502, such as Fig. 11B as shown in .

[0099] In some embodiments, wet chemical selective etching or vapor etching may be performed to etch the cylindrical portions (e.g., cylindrical portions 1002, 1004, 1006) of the pillar structure 502. In this regard, in some embodiments, a liquid or vapor including hydrofluoric acid (HF) may be introduced, which may etch the top cylindrical portion 1002, the cylindrical portion 1004 of the third boundary layer 302c, and the cylindrical portion 1006 of the second dielectric layer 304b.

[0100] Fig. 12A is a horizontal cross-sectional view of yet another intermediate structure 1200 that may be used in forming a high density capacitor according to various embodiments, and Fig. 12B According to various embodiments Fig. 12A A vertical cross-sectional view of the intermediate structure 1200 is shown. Fig. 12A The plane bounded by the horizontal section view shown is Fig. 12B The cross section A-A' in the figure indicates that Fig. 12B The plane bounded by the vertical section view shown is Fig. 12A The cross section BB' in FIG. 1 is indicated by the second conductive layer 704 deposited on the intermediate structure 1100. Fig.11A and Fig. 11B The intermediate structure 1100 is shown to form the intermediate structure 1200. The second conductive layer 704 may include a conductive metal nitride or a conductive metal carbide, such as TiN, TaN, WN, TiC, TaC and / or WC. Other suitable conductive materials within the contemplated scope of the present disclosure may also be used.

[0101] The second conductive layer 704 may be deposited to form conductive contact with the barrier layer 216 within the inner cylindrical sidewalls of the cylindrical cavities 1102 in the pillar structures 502 and to make conductive contact with the outer shell 204b. The portion of the second conductive layer 704 formed along the cylindrical sidewalls of the cylindrical cavities 1102 thereby forms the conductive contact described above with reference to Figure 2A and Figure 2B The bottom electrode (including the inner shell 204a and the inner shell 204a) is illustrated.

[0102] Fig.13A is a horizontal cross-sectional view of yet another intermediate structure 1300 that may be used in forming a high density capacitor according to various embodiments, and Fig. 13B According to various embodiments Fig.13A A vertical cross-sectional view of the intermediate structure 1300 is shown. Fig.13A The plane bounded by the horizontal section view shown is Fig. 13B The cross section A-A' in the figure indicates that Fig. 13B The plane bounded by the vertical section view shown is Fig.13A The cross section BB' in FIG. 1 is indicated by the dielectric layer 210 formed on the intermediate structure 1200. Fig. 12A and Fig. 12B The intermediate structure 1200 shown forms the intermediate structure 1300. Fig.13A and Fig. 13B As shown in FIG. 1 , the portion of the dielectric layer 210 formed on the inner cylindrical wall above the inner housing 204a may form the above reference Figure 2A and Figure 2B Similarly, the portion of the dielectric layer 210 formed on the outer cylindrical wall above the outer shell 204b may form the first concentric portion 210a of the dielectric layer described above. Figure 2A and Figure 2B A second concentric portion 210b of the dielectric layer is illustrated.

[0103] In various embodiments, the dielectric layer (e.g., dielectric layer 210, first concentric portion 210a, second concentric portion 210b) may be a high-k dielectric material. Examples of high-k dielectric materials include, but are not limited to, hafnium oxide, hafnium silicon oxide, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, zirconium oxide, titanium oxide, aluminum oxide, and hafnium dioxide-aluminum oxide. Other suitable dielectric materials are also within the contemplated scope of the present disclosure. In various embodiments, the dielectric layer (e.g., dielectric layer 210, first concentric portion 210a, second concentric portion 210b) may have a thickness in the range of 0.5 nanometers to 5.0 nanometers (e.g., 1 nanometer to 4 nanometers), although greater thicknesses or lesser thicknesses may also be used.

[0104] Fig.14Ais a horizontal cross-sectional view of yet another intermediate structure 1400 that may be used in forming a high density capacitor according to various embodiments, and Fig. 14B According to various embodiments Fig.14A A vertical cross-sectional view of the intermediate structure 1400 is shown. Fig.14A The plane bounded by the horizontal section view shown is Fig. 14B The cross section A-A' in the figure indicates that Fig. 14B The plane bounded by the vertical section view shown is Fig.14A The cross section BB' in FIG. 1 is indicated by the third conductive layer 206 deposited on the intermediate structure 1300. Fig.13A and Fig. 13B The intermediate structure 1300 is shown to form the intermediate structure 1400. The third conductive layer 206 may include a conductive metal nitride or a conductive metal carbide, such as TiN, TaN, WN, TiC, TaC and / or WC. Other suitable conductive materials within the contemplated scope of the present disclosure may also be used.

[0105] like Fig.14A and Fig. 14B As shown in , some portions of the third conductive layer 206 may form some portions of the top electrode (having a plurality of vertical portions 206a and surrounding portions 206b). In this regard, some portions of the third conductive layer 206 may include a plurality of vertical portions 206a and surrounding portions 206b, as described above with reference to Figure 2A and Figure 2B In addition, as mentioned above Figure 2A and Figure 2B As described above, in some embodiments, when a plurality of non-concentric cylindrical portions 202 having a spatial distribution with a first symmetry (e.g., hexagonal) are placed in a region with a second symmetry (e.g., rectangular), one or more dielectric spacer regions 215 may be formed. In this regard, the dielectric spacer region 215 may be a space that is too large to be completely filled by the third conductive layer 206.

[0106] Fig.15A is a top view of yet another intermediate structure 1500 that may be used in forming a high-density capacitor (eg, high-density capacitors 200, 2200) according to various embodiments, and Fig. 15B According to various embodiments Fig.15A A vertical cross-sectional view of the intermediate structure 1500 is shown. Fig. 15B The plane bounded by the vertical section view shown is Fig.15A The cross section BB' in FIG. Fig.15A The area of ​​the intermediate structure 1500 shown in the top view is composed of Fig. 15BThe fourth dielectric layer 304d and the second protective layer 1502L may be formed on the intermediate structure 1400. Fig.14A and Fig. 14B The intermediate structure 1400 is shown to form the intermediate structure 1500. A patterned photoresist 308 may then be formed over the second protective layer 1502L.

[0107] The fourth dielectric layer 304d may include, for example, undoped silicate glass, doped silicate glass (e.g., deposited by decomposing TEOS), organosilicate glass, silicon oxynitride, or silicon carbonitride. Other dielectric materials are also within the contemplated scope of the present disclosure. The dielectric material of the fourth dielectric layer 304d may be deposited by a conformal deposition process (e.g., a chemical vapor deposition process) or a self-planarization deposition process (e.g., spin coating). The second protective layer 1502L may include an etch stop material, such as silicon nitride, silicon carbide, silicon carbonitride, or a dielectric metal oxide (e.g., aluminum oxide, titanium oxide, tantalum oxide, etc.). In an exemplary embodiment, the second protective layer 1502L may include silicon nitride. The second protective layer 1502L may be deposited by a conformal deposition process or a non-conformal deposition process. In one embodiment, the second protective layer 1502L may be deposited by chemical vapor deposition, atomic layer deposition, or physical vapor deposition.

[0108] Fig.16A is a top view of yet another intermediate structure 1600 that may be used in forming a high-density capacitor (eg, high-density capacitors 200, 2200) according to various embodiments, and Fig. 16B According to various embodiments Fig.16A A vertical cross-sectional view of the intermediate structure 1600 is shown. Fig. 16B The plane bounded by the vertical section view shown is Fig.16A The cross section BB' in FIG. Fig.16A The area of ​​the intermediate structure 1600 shown in the top view is composed of Fig. 16B The anisotropic etching process may be performed to etch some portions of the second protection layer 1502L, some portions of the fourth dielectric layer 304d, and portions of the third conductive layer 206 that are not masked by the patterned photoresist 308. Fig.15A and Fig. 15B The intermediate structure 1500 is shown to form the intermediate structure 1600. The patterned photoresist 308 can then be removed by ashing or by dissolving using a solvent. The remaining portion of the second protective layer 1502L can thus form a patterned second protective layer 1502, which can act as a hard mask that can be used during further processing operations, as shown in FIG. Fig.17A and Fig. 17B Elaborate in more detail.

[0109] Fig.17A is a top view of yet another intermediate structure 1700 that may be used in forming a high-density capacitor (eg, high-density capacitors 200, 2200) according to various embodiments, and Fig. 17B According to various embodiments Fig.17A A vertical cross-sectional view of the intermediate structure 1700 is shown. Fig. 17B The plane bounded by the vertical section view shown is Fig.17A The cross section BB' in FIG. Fig.17A The area of ​​the intermediate structure 1700 shown in the top view is composed of Fig. 17B The fifth dielectric layer 304e and the third protective layer 1702L may be formed on the intermediate structure 1600. Fig.16A and Fig. 16B Intermediate structure 1600 is shown forming intermediate structure 1700 .

[0110] Fig.18A is a top view of yet another intermediate structure 1800 that may be used in forming a high-density capacitor (eg, high-density capacitors 200, 2200) according to various embodiments, and Fig.18B According to various embodiments Fig.18A A vertical cross-sectional view of the intermediate structure 1800 is shown. Fig.18B The plane bounded by the vertical section view shown is Fig.18A The cross section BB' in FIG. Fig.18A The area of ​​the intermediate structure 1800 shown in the top view is composed of Fig.18B The intermediate structure 1700 may be self-removed by performing an anisotropic etching process on the area not masked by the patterned second protective layer 1502. Fig.17A and Fig. 17B The intermediate structure 1700 shown forms an intermediate structure 1800, the region including some portions of the third protection layer 1702L, some portions of the fifth dielectric layer 304e, some portions of the dielectric layer 210, some portions of the first conductive layer 702, some portions of the barrier layer 216, some portions of the patterned hard mask 306, and some portions of the third dielectric layer 304c, as shown in FIG. Fig.18B As shown in . A sixth dielectric layer 304f may then be formed over the resulting structure. A planarization process (eg, chemical mechanical planarization) may then be used to planarize the sixth dielectric layer 304f. Fig.18B As shown in FIG. 1 , during the etching process, protection spacers 1802 may be formed from the third protection layer 1702L.

[0111] Fig.19Ais a top view of yet another intermediate structure 1900 that may be used in forming a high-density capacitor (eg, high-density capacitors 200, 2200) according to various embodiments, and Fig.19B According to various embodiments Fig.19A A vertical cross-sectional view of the intermediate structure 1900 is shown. Fig.19B The plane bounded by the vertical section view shown is Fig.19A The cross section BB' in FIG. Fig.19A The area of ​​the intermediate structure 1900 shown in the top view is composed of Fig.19B The fourth boundary layer 302d may be formed on the intermediate structure 1800. Fig.18A and Fig.18B The intermediate structure 1800 is shown to form the intermediate structure 1900. The fourth boundary layer 302d may include an etch stop material, such as silicon nitride, silicon carbide, silicon carbonitride, or a dielectric metal oxide (such as aluminum oxide, titanium oxide, tantalum oxide, etc.). In an exemplary embodiment, the fourth boundary layer 302d may include silicon nitride. The fourth boundary layer 302d may be deposited by a conformal deposition process or a non-conformal deposition process. In one embodiment, the fourth boundary layer 302d may be deposited by chemical vapor deposition, atomic layer deposition, or physical vapor deposition. The thickness of the fourth boundary layer 302d may range from approximately 2 nanometers to approximately 20 nanometers (e.g., from approximately 3 nanometers to approximately 12 nanometers), although smaller thicknesses and larger thicknesses may also be used.

[0112] Fig. 20A is a top view of yet another intermediate structure 2000 that may be used in forming a high-density capacitor (eg, high-density capacitors 200, 2200) according to various embodiments, and Fig. 20B According to various embodiments Fig. 20A A vertical cross-sectional view of the intermediate structure 2000 is shown. Fig. 20B The plane bounded by the vertical section view shown is Fig. 20A The cross section BB' in FIG. Fig. 20A The area of ​​the intermediate structure 2000 shown in the top view is composed of Fig. 20B The intermediate structure 1900 may be self-contained by forming one or more conductive via structures (e.g., conductive vias 2002a, 2002b) in the intermediate structure 1900. Fig.19A and Fig.19B Intermediate structure 1900 is shown forming intermediate structure 2000 .

[0113] In this regard, a patterned photoresist (not shown) may be formed over the fourth boundary layer 302d. The patterned photoresist may be used as a mask when etching the intermediate structure 1900. For example, the unmasked portion of the patterned photoresist may correspond to a location where a via cavity may be etched. In this regard, an anisotropic etching process may be performed to etch a via cavity through the fourth boundary layer 302d, the sixth dielectric layer 304f, the second protective layer 1502L, and the fourth dielectric layer 304d, such that the via cavity is etched down to the conductive surface of the third conductive layer 206, which forms a top portion of a top electrode (having a plurality of vertical portions 206a and a surrounding portion 206b). A conductive material may then be deposited in the via cavity to form a conductive via (e.g., conductive vias 2002a, 2002b). In this way, the conductive via 2002a may be electrically connected to the top electrode (having a plurality of vertical portions 206a and a surrounding portion 206b). In further processing operations, the conductive via 2002a may be further electrically connected to additional electrical interconnect structures to be formed subsequently.

[0114] Fig.21A According to various embodiments Figure 2A and Figure 2B A top view of the high density capacitor 200 is shown, and Fig.21B According to various embodiments Figure 2A , Figure 2B and Fig.21A A vertical cross-sectional view of a high-density capacitor 200 is shown. Fig.21B The plane bounded by the vertical section view shown is Fig.21A The cross section BB' in FIG. Fig.21A The high density capacitor 200 shown in the top view is composed of Fig.21B The seventh dielectric layer 304g may be formed on the fourth boundary layer 302d and conductive lines (such as conductive lines 2102a, 2102b) may be formed in the seventh dielectric layer 304g and the fourth boundary layer 302d. Fig. 20A and Fig. 20B The intermediate structure 2000 is shown to form a high density capacitor 200. As shown, the conductive lines (such as conductive lines 2102a, 2102b) can be electrically connected to the conductive vias (such as conductive vias 2002a, 2002b) to form an electrically interconnected structure. In this regard, the above reference Figure 2A and Figure 2B The second interconnect structure 218b illustrated may include the leftmost conductive via 2002a connected to the leftmost conductive line 2102a. Figure 2A and Figure 2BAs described above, the high-density capacitor 200 may be disposed on the interlayer dielectric layer 220 including the interconnect structure 218 a and may also be electrically connected to the second interconnect structure 218 b formed above the high-density capacitor 200 .

[0115] Fig.22A is a horizontal cross-sectional view of yet another high-density capacitor 2200 that can be formed in a BEOL process according to various embodiments, and Fig. 22B According to various embodiments Fig.22A A vertical cross-sectional view of the high-density capacitor 2200 is shown. Fig. 22B The plane bounded by the vertical section view shown is Fig.22A The cross section BB' in FIG. Fig.22A The high density capacitor 2200 shown in the top view consists of Fig. 22B The brackets marked with "A" indicate that the FIG. 3A to FIG. 21B High-density capacitor 2200 is formed using similar operations as described for forming high-density capacitor 200 .

[0116] With reference to above Fig. 11B The operation of etching the pillar structure 502 down to the second boundary layer 302b is reversed. Fig.22A and Fig. 22B When the high density capacitor 2200 is shown, the etching process can further etch through the second boundary layer 302b and the first dielectric layer 304a. Fig. 22B As shown in FIG. 1 , the inner shell 204a of the bottom electrode (including the inner shell 204a and the inner shell 204a), the vertical portion 206a of the top electrode (having a plurality of vertical portions 206a and surrounding portions 206b), and the first concentric portion 210a of the dielectric layer 210 can be relatively Figure 2A , Figure 2B , Fig.21A and Fig.21B The downward extension of the corresponding structure in the high-density capacitor 200 is shown to extend further downward into the region 2202. By extending the length of the inner shell 204a of the bottom electrode (including the inner shell 204a and the inner shell 204a), the length of the vertical portion 206a of the top electrode (having a plurality of vertical portions 206a and surrounding portions 206b), and the length of the first concentric portion 210a of the dielectric layer 210 in this manner, the capacitance of the high-density capacitor 2200 can be increased relative to the capacitance of the high-density capacitor 200. As a result, the high-density capacitor 2200 can have improved characteristics relative to the high-density capacitor 200.

[0117] Fig.23A According to various embodiments, Fig.22A and Fig. 22BThe high density capacitor 2200 is shown as a vertical cross-sectional view of an intermediate structure 2300a that can be used, and Fig. 23B According to various embodiments, Fig.22A and Fig. 22B 2 is a vertical cross-sectional view of yet another intermediate structure 2300b that may be used when high-density capacitor 2200 is shown. Fig.23A and Fig. 23B The plane bounded by the vertical section view shown is Fig.22A In this regard, the above reference can be improved by first etching the portion 2302 of the second boundary layer 302b. Fig. 11B Explained in the Formation Fig.22A and Fig. 22B The high density capacitor 2200 shown in FIG. Fig.23A As shown in FIG. 1 , after forming the first dielectric layer 304 a and the second boundary layer 302 b, a patterned photoresist 308 may be formed over the second boundary layer 302 b. And then the patterned photoresist 308 may be used as a mask during an etching process, which may be performed to remove a portion 2302 of the second boundary layer, such as Fig. 23B The patterned photoresist 308 may then be removed by ashing or by dissolving using a solvent. Additional operations may then be performed to produce Figure 3A and Figure 3B The starting structure can be used to form Figure 2A and Figure 2B The high density capacitor 200 or Fig.22A and Fig. 22B A high density capacitor 2200 is shown.

[0118] Fig.242 is a flow chart illustrating the operations of a method 2400 of forming a high-density capacitor (e.g., high-density capacitors 200, 2200). In operation 2402, the method 2400 may include etching an interlayer dielectric layer (e.g., interlayer dielectric layers 304a, 304b, 304c) to produce a plurality of pillar structures 502. In operation 2404, the method 2400 may include depositing a first conductive layer 702 over the plurality of pillar structures 502 and surrounding areas to produce a plurality of outer shells 204b of a bottom electrode (including an inner shell 204a and a plurality of outer shells 204b with the inner shell 204a). In operation 2406, the method 2400 may include etching the plurality of pillar structures 502 to form a plurality of cylindrical cavities 1102 in the plurality of pillar structures 502. In operation 2408, the method 2400 may include depositing the second conductive layer 704 within the plurality of cylindrical cavities 1102 to produce a plurality of inner shells 204a of the bottom electrode (including the inner shell 204a and the inner shell 204a). In operation 2410, the method 2400 may include depositing a dielectric layer 210 on the bottom electrode (including the inner shell 204a and the inner shell 204a), and in operation 2412, the method 2400 may include depositing a third conductive layer 206 on the dielectric layer 210 to produce a plurality of vertical portions 206a and surrounding portions 206b of the top electrode (having a plurality of vertical portions 206a and surrounding portions 206b).

[0119] In various embodiments, the method 2400 may further include forming a barrier layer 216 over the plurality of pillar structures 502 and the surrounding area before depositing the first conductive layer 702 over the plurality of pillar structures 502 and the surrounding area. The method 2400 may further include electrically connecting the bottom electrode (including the inner shell 204a and the inner shell 204a) to a first interconnect structure 218a formed below the high-density capacitor (e.g., high-density capacitor 200, 2200) and electrically connecting the top electrode (having the plurality of vertical portions 206a and the surrounding portion 206b) to a second interconnect structure 218b formed above the high-density capacitor (e.g., high-density capacitor 200, 2200). According to the method 2400, the operation 2406 of etching the interlayer dielectric layer (e.g., the interlayer dielectric layers 304a, 304b, 304c) to generate the plurality of pillar structures 502 may further include generating the plurality of pillar structures 502 such that the separation distance 212 between adjacent pillar structures 502 is less than or equal to 0.2 microns (e.g., see Figure 2A ).

[0120] With reference to all the drawings and according to various embodiments of the present disclosure, a high-density capacitor (e.g., high-density capacitor 200, 2200) is provided. The high-density capacitor (e.g., high-density capacitor 200, 2200) may include a bottom electrode (including an inner shell 204a and a first outer shell 204b concentric with the inner shell 204a), wherein the bottom electrode includes a first cylindrical structure (e.g., cylindrical portion 202), and the first cylindrical structure (e.g., cylindrical portion 202) includes a first inner shell 204a and a first outer shell 204b concentric with the first inner shell 204a. A high-density capacitor (e.g., high-density capacitors 200, 2200) may further include a top electrode (having multiple vertical portions 206a and surrounding portions 206b), wherein the top electrode includes a first vertical portion 206a and a surrounding portion 206b, such that the first vertical portion 206a is surrounded in a vertical direction by a first inner shell 204a of a bottom electrode (including an inner shell 204a and a first outer shell 204a with an inner shell 204a), and the surrounding portion 206b surrounds in a vertical direction a first outer shell 204b of the bottom electrode (including an inner shell 204a and a first outer shell 204a with an inner shell 204a). A high-density capacitor (e.g., high-density capacitors 200, 2200) may further include a dielectric layer 210 separating a top electrode (having a plurality of vertical portions 206a and surrounding portions 206b) from a bottom electrode (including an inner shell 204a and with the inner shell 204a), and a barrier layer 216 separating a first inner shell 204a of the bottom electrode (including an inner shell 204a and with the inner shell 204a) from a first outer shell 204b of the bottom electrode (including an inner shell 204a and with the inner shell 204a).

[0121] In various embodiments, the bottom electrode (including the inner shell 204a and the inner shell 204a) may include a second cylindrical structure (such as the cylindrical portion 202) that is not concentric with the first cylindrical structure (such as the cylindrical portion 202). The second cylindrical structure (such as the cylindrical portion 202) may include a second inner shell 204a and a second outer shell 204b that is concentric with the second inner shell 204a. The top electrode (having a plurality of vertical portions 206a and surrounding portions 206b) may further include a second vertical portion 206a surrounded by the second inner shell 204a of the bottom electrode (including the inner shell 204a and the inner shell 204a) in a vertical direction, and the surrounding portion 206b surrounds the second outer shell 204b of the bottom electrode (including the inner shell 204a and the inner shell 204a) in a vertical direction. In various embodiments, the first vertical portion 206a of the top electrode (having multiple vertical portions 206a and surrounding portions 206b) and the second vertical portion 206a of the top electrode (having multiple vertical portions 206a and surrounding portions 206b) may be separated from each other by a separation distance 212 less than or equal to 0.2 microns.

[0122] In various embodiments, the dielectric layer 210 may further include a first concentric portion 210a separating a first vertical portion 206a of the top electrode (having a plurality of vertical portions 206a and a surrounding portion 206b) from a first inner shell 204a of the bottom electrode (including an inner shell 204a and the inner shell 204a) and a second concentric portion 210b separating a first outer shell 204b of the bottom electrode (including an inner shell 204a and the inner shell 204a) from a surrounding portion 206b of the top electrode (having a plurality of vertical portions 206a and the surrounding portion 206b). In various embodiments, the diameter 214 of the second concentric portion 210b may be less than or equal to 0.2 microns. In still other embodiments (e.g., see Figure 2A and Figure 2B ), the bottom electrode (including the inner shell 204a and the outer shell 204b) may further include a plurality of non-concentric cylindrical portions 202, each of the plurality of non-concentric cylindrical portions 202 including the inner shell 204a and the outer shell 204b. In such an embodiment, the top electrode (having a plurality of vertical portions 206a and surrounding portions 206b) may further include a plurality of vertical portions 206a, each of which is surrounded in the vertical direction by the inner shell 204a of the corresponding cylindrical portion 202, and the surrounding portion 206b of the top electrode (having a plurality of vertical portions 206a and surrounding portions 206b) may respectively surround each of the plurality of non-concentric cylindrical portions 202 of the bottom electrode (including the inner shell 204a and the inner shell 204a), so that adjacent non-concentric cylindrical portions 202 of the bottom electrode (including the inner shell 204a and the inner shell 204a) are separated from each other by the surrounding portion 206b of the top electrode (having a plurality of vertical portions 206a and surrounding portions 206b).

[0123] In some embodiments, at least some of the plurality of non-concentric cylindrical portions 202 of the bottom electrode (including the inner shell 204a and the inner shell 204a) may include a spatial distribution having hexagonal symmetry (e.g., see Figure 2A and Figure 2B). In such an embodiment, the bottom electrode (including the inner shell 204a and the inner shell 204a) can be electrically connected to the first interconnect structure 218a formed below the high-density capacitor (e.g., high-density capacitors 200, 2200), and the top electrode (having a plurality of vertical portions 206a and a surrounding portion 206b) is electrically connected to the second interconnect structure 218b formed above the high-density capacitor (e.g., high-density capacitors 200, 2200). In various embodiments, the dielectric layer 210 can further include a high-k dielectric material, the high-k dielectric material including one or more of hafnium oxide, hafnium silicon oxide, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, zirconium oxide, titanium oxide, aluminum oxide, and hafnium dioxide-aluminum oxide. In various embodiments, the high-density capacitor (e.g., high-density capacitors 200, 2200) can be disposed on the interlayer dielectric layer 220 including the interconnect structure 218a.

[0124] In some embodiments, the first inner shell 204a and the first outer shell 204b may each include a conductive material having a thickness less than or equal to 10 nanometers, and the barrier layer 216 may include one or more of Ta and TaN. In various embodiments, the bottom electrode (including the inner shell 204a and the inner shell 204a) and the top electrode (having a plurality of vertical portions 206a and surrounding portions 206b) each include one or more of TiN, TaN, WN, TiC, TaC, or WC.

[0125] In yet another embodiment, a high-density capacitor (e.g., high-density capacitors 200 and 2200) is provided. The high-density capacitor (e.g., high-density capacitors 200 and 2200) may include a bottom electrode (including an inner shell 204a and an outer shell 204a) and a top electrode (having a plurality of vertical portions 206a and a surrounding portion 206b), wherein the bottom electrode has a plurality of non-concentric cylindrical portions 202, each of which includes an inner shell 204a and an outer shell 204b, and the top electrode includes a plurality of vertical portions 206a and a surrounding portion 206b. In such an embodiment, each of the multiple vertical portions 206a may be surrounded in the vertical direction by the inner shell 204a of the corresponding cylindrical portion 202 of the bottom electrode (including the inner shell 204a and the inner shell 204a), and the surrounding portion 206b of the top electrode (having the multiple vertical portions 206a and the surrounding portion 206b) may respectively surround each of the multiple non-concentric cylindrical portions 202 of the bottom electrode (including the inner shell 204a and the inner shell 204a), so that adjacent non-concentric cylindrical portions 202 of the bottom electrode (including the inner shell 204a and the inner shell 204a) are separated from each other by the surrounding portion 206b of the top electrode (having the multiple vertical portions 206a and the surrounding portion 206b).

[0126] The high-density capacitor (e.g., high-density capacitor 200, 2200) may further include a dielectric layer 210 separating the top electrode (having a plurality of vertical portions 206a and surrounding portions 206b) from the bottom electrode (including the inner shell 204a and the inner shell 204a). In various embodiments, at least some of the plurality of non-concentric cylindrical portions 202 of the bottom electrode (including the inner shell 204a and the inner shell 204a) include a spatial distribution having hexagonal symmetry (e.g., see Figure 2A and Figure 2B ). In various embodiments, adjacent vertical portions 206a of the plurality of vertical portions 206a may be separated from each other by a separation distance 212 less than or equal to 0.2 microns. The dielectric layer 210 may further include a first concentric portion 210a separating each of the plurality of vertical portions 206a of the top electrode (having a plurality of vertical portions 206a and a surrounding portion 206b) from the inner shell 204a of the bottom electrode (including the inner shell 204a and the inner shell 204a) and a second concentric portion 210b separating the outer shell 204b of the bottom electrode (including the inner shell 204a and the inner shell 204a) from the surrounding portion 206b of the top electrode (having a plurality of vertical portions 206a and the surrounding portion 206b). In some embodiments, a diameter 214 of the second concentric portion 210b may be less than or equal to 0.2 microns.

[0127] The dielectric layer 210 may include a high-k dielectric material including one or more of hafnium oxide, hafnium silicon oxide, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, zirconium oxide, titanium oxide, aluminum oxide, and hafnium dioxide-aluminum oxide. In addition, in various embodiments, the bottom electrode (including the inner shell 204a and the inner shell 204a) can be electrically connected to the first interconnect structure 218a formed below the high-density capacitor (e.g., high-density capacitors 200, 2200), and the top electrode (having a plurality of vertical portions 206a and a surrounding portion 206b) can be electrically connected to the second interconnect structure 218b formed above the high-density capacitor (e.g., high-density capacitors 200, 2200).

[0128] Various embodiments of the present disclosure provide a high-density capacitor (e.g., high-density capacitor 200, 2200) and a method of forming the same, which can be advantageous in terms of manufacturing flexibility, size reduction, and capacitance increase. In this regard, the high-density capacitor (e.g., high-density capacitor 200, 2200) can be formed in a BEOL process and can be incorporated with other BEOL circuit components (e.g., TFT devices). As such, the embodiment high-density capacitor (e.g., high-density capacitor 200, 2200) can include materials that can be processed at low temperatures and thus can cause no damage to previously fabricated devices (e.g., FEOL devices and MEOL devices). Embodiment high-density capacitors (e.g., high-density capacitors 200, 2200) include a bottom electrode (including an inner shell 204a and inner shell 204a) and a top electrode (having a plurality of vertical portions 206a and surrounding portions 206b), wherein the bottom electrode has a plurality of non-concentric cylindrical portions 202, each of the plurality of non-concentric cylindrical portions 202 having a diameter 214 less than or equal to 0.2 microns, and the top electrode has a vertical portion 206a surrounded in a vertical direction by the cylindrical portion of the bottom electrode (including the inner shell 204a and inner shell 204a). In addition, the vertical portions 206a may be separated from each other by a separation distance that is also less than or equal to 0.2 microns. In some embodiments, the plurality of non-concentric cylindrical portions 202 may have a spatial distribution having a hexagonal symmetry (e.g., see Figure 2A ), which enables dense packaging of the non-concentric cylindrical portions 202. As such, the bottom electrode (including the inner housing 204a and the inner housing 204a) and the top electrode (having the plurality of vertical portions 206a and the surrounding portions 206b) can form a densely packed capacitor structure (e.g., capacitors 200, 2200) that is compatible with other circuit components formed in BEOL processing operations.

[0129] In one embodiment, the first inner shell and the first outer shell each include a conductive material with a thickness less than or equal to 10 nanometers.

[0130] In one embodiment, adjacent vertical portions of the plurality of vertical portions are separated from each other by a separation distance less than or equal to 0.2 micrometers.

[0131] The foregoing summarizes the features of several embodiments so that those with ordinary knowledge in the art can better understand the aspects of the present disclosure. Those with ordinary knowledge in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for performing the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those with ordinary knowledge in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and those with ordinary knowledge in the art can make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure.

Claims

1. A high-density capacitor, comprising: A bottom electrode, comprising a first cylindrical structure, wherein the first cylindrical structure comprises: a first inner housing; and a first outer shell, concentric with the first inner shell; Top electrode, including: a first vertical portion; and a surrounding portion, wherein the first vertical portion is surrounded by the first inner shell of the bottom electrode in a vertical direction, and the surrounding portion surrounds the first outer shell of the bottom electrode in a vertical direction; a dielectric layer separating the top electrode from the bottom electrode; and A barrier layer separates the first inner shell of the bottom electrode from the first outer shell of the bottom electrode.

2. The high-density capacitor according to claim 1, wherein: The bottom electrode comprises a second cylindrical structure that is not concentric with the first cylindrical structure, and the second cylindrical structure comprises: a second inner housing; and a second outer shell, concentric with the second inner shell; The top electrode further includes a second vertical portion surrounded by the second inner shell of the bottom electrode in a vertical direction, and the surrounding portion surrounds the second outer shell of the bottom electrode in a vertical direction; and The first vertical portion of the top electrode and the second vertical portion of the top electrode are separated from each other by a separation distance less than or equal to 0.2 micrometers.

3. The high-density capacitor of claim 1, wherein the dielectric layer further comprises: a first concentric portion separating the first vertical portion of the top electrode from the first inner shell of the bottom electrode; as well as a second concentric portion separating the first outer shell of the bottom electrode from the surrounding portion of the top electrode, The diameter of the second concentric portion is less than or equal to 0.2 microns.

4. The high-density capacitor according to claim 1, wherein: The bottom electrode further comprises a plurality of non-concentric cylindrical portions, each of the plurality of non-concentric cylindrical portions comprising an inner shell and an outer shell; The top electrode further comprises a plurality of vertical portions, each of the plurality of vertical portions being surrounded in a vertical direction by the inner shell of a corresponding cylindrical portion of the plurality of non-concentric cylindrical portions; and The surrounding portion of the top electrode surrounds each of the multiple non-concentric cylindrical portions of the bottom electrode in the vertical direction, so that adjacent non-concentric cylindrical portions of the multiple non-concentric cylindrical portions of the bottom electrode are separated from each other by the surrounding portion of the top electrode. 5 . The high-density capacitor of claim 4 , wherein at least some of the plurality of non-concentric cylindrical portions of the bottom electrode comprise a spatial distribution having hexagonal symmetry.

6. The high-density capacitor according to claim 1, wherein: The bottom electrode is electrically connected to a first interconnect structure formed below the high-density capacitor; and The top electrode is electrically connected to a second interconnect structure formed above the high-density capacitor.

7. The high-density capacitor of claim 1, wherein the high-density capacitor is disposed on an interlayer dielectric layer including an interconnect structure.

8. A high-density capacitor, comprising: a bottom electrode comprising a plurality of non-concentric cylindrical portions, each of the plurality of non-concentric cylindrical portions comprising an inner shell and an outer shell; a top electrode comprising a plurality of vertical portions and a surrounding portion, wherein each of the plurality of vertical portions is surrounded in a vertical direction by the inner shell of a corresponding cylindrical portion of the plurality of non-concentric cylindrical portions of the bottom electrode, and the surrounding portion of the top electrode surrounds each of the plurality of non-concentric cylindrical portions of the bottom electrode in a vertical direction, respectively, so that adjacent non-concentric cylindrical portions of the plurality of non-concentric cylindrical portions of the bottom electrode are separated from each other by the surrounding portion of the top electrode; as well as a dielectric layer separating the top electrode from the bottom electrode, Wherein at least some of the plurality of non-concentric cylindrical portions of the bottom electrode comprise a spatial distribution having hexagonal symmetry.

9. The high-density capacitor of claim 8, wherein the dielectric layer further comprises: a first concentric portion separating each of the plurality of vertical portions of the top electrode from the inner casing of the bottom electrode; as well as a second concentric portion separating the outer shell of the bottom electrode from the surrounding portion of the top electrode, The diameter of the second concentric portion is less than or equal to 0.2 microns.

10. The high-density capacitor of claim 8, wherein: The bottom electrode is electrically connected to a first interconnect structure formed below the high-density capacitor; and The top electrode is electrically connected to a second interconnect structure formed above the high-density capacitor.

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