Pulse circuit of FD-121 pulse fetus-voice meter

Abstract

The utility model discloses a pulse circuit of an FD-121 pulse fetus-voice meter. The pulse circuit comprises a pulse time sequence control single chip microcomputer circuit, a pulse wave power amplification and emission circuit, a pulse receiving and small signal amplification circuit, a pulse wave phase quadrature demodulation circuit, a differential signal conversion single-end signal circuit and a filter circuit group. According to the utility model, a pulse wave working mode is adopted, and time division multiplexing is carried out on the whole piezoelectric sensor, so that 100% utilization of the sensor is achieved, the sending time of ultrasonic waves is controlled to be transmitted to a designed depth through software according to the sending propagation and receiving return time of the ultrasonic waves in water at 1500 meters per second, and then the ultrasonic waves are transmitted to the designed depth after waiting for the return time. And opening a receiving signal channel. In the whole process, the same sensor can be used for transmitting and receiving.

Description

Technical Field

[0001] The utility model relates to the technical field of fetal heart rate monitor equipment, in particular to a pulse circuit of a FD-121 pulse fetal heart rate monitor. Background Art

[0002] Fetal heart rate monitor, also known as fetal heart rate monitor, can obtain fetal heart movement information from the abdomen of pregnant women based on the Doppler principle. It is not used for continuous monitoring, but only obtains fetal heart movement information to monitor whether the fetal movement is abnormal. According to the fetal heart condition, it is convenient for medical staff to make corresponding treatment according to the fetal heart condition. In the prior art, the area of ​​the piezoelectric sensor of the continuous wave fetal heart rate monitor is fixed, generally used for transmission, and the other half is used for reception, which results in only 50% utilization of the sensor, which is inconvenient.

[0003] Therefore, the prior art has defects and needs to be improved. Utility Model Content

[0004] The utility model aims to overcome the deficiencies of the prior art and provide a FD-121 fetal heart rate monitor pulse circuit.

[0005] The technical solution of the utility model is as follows: a FD-121 pulse fetal heart rate monitor pulse circuit is provided, including: a pulse timing control single-chip microcomputer circuit, a pulse wave power amplification and transmission circuit, a pulse receiving and small signal amplification circuit, a pulse wave phase orthogonal demodulation circuit, a differential signal conversion single-ended signal circuit, and a filter circuit group, the pulse timing control single-chip microcomputer circuit is electrically connected to the pulse wave power amplification and transmission circuit, the two ends of the pulse receiving and small signal amplification circuit are respectively electrically connected to the pulse wave power amplification and transmission circuit and the pulse wave phase orthogonal demodulation circuit, and the two ends of the differential signal conversion single-ended signal circuit are respectively electrically connected to the pulse wave phase orthogonal demodulation circuit and the filter circuit group.

[0006] Furthermore, the pulse timing control single-chip microcomputer circuit includes: a single-chip microcomputer J2, a crystal oscillator Y1, a capacitor C6, and a capacitor C9. The second pin of the single-chip microcomputer J2 is connected to one end of the crystal oscillator Y1 and one end of the capacitor C6. The third pin of the single-chip microcomputer J2 is connected to the other end of the crystal oscillator Y1 and one end of the capacitor C9. The other end of the capacitor C6 and the other end of the capacitor C9 are connected to the ground in parallel. The 11th pin of the single-chip microcomputer J2 is electrically connected to the pulse wave power amplification transmitting circuit.

[0007] Further, the pulse wave power amplification transmitting circuit includes: a resistor R4, a resistor R5, a resistor R7, an inductor L2, an inductor L3, a transistor Q1, a transistor Q2, a transistor Q3, a polarity capacitor C8, a polarity capacitor C10, a capacitor C7, a capacitor C11, a capacitor C12 and a capacitor C13, one end of the capacitor C13 and one end of the resistor R7 are connected in parallel to the CPUB_1 port of the pulse timing control single-chip circuit, the other end of the capacitor C13 is connected to the other end of the resistor R7 and the base of the transistor Q2, the emitter of the transistor Q2 is grounded, the collector of the transistor Q2 is connected to the base of the transistor Q1, the base of the transistor Q3, and one end of the resistor R5, the other end of the resistor R5 is connected to the The collector, one end of the resistor R4, the positive end of the polar capacitor C8, and one end of the capacitor C7 are connected, the negative end of the polar capacitor C8 and the other end of the capacitor C7 are connected to the ground in parallel, the other end of the resistor R4 and one end of the inductor L2 are connected to D+12V respectively, the other end of the inductor L2 and the positive end of the polar capacitor C10 and one end of the capacitor C11 are connected to +12V in parallel, the negative end of the polar capacitor C10 and the other end of the capacitor C11 are connected to the ground in parallel, the emitter of the transistor Q1 is connected to the emitter of the transistor Q3 and one end of the capacitor C12, the collector of the transistor Q3 is grounded, the other end of the capacitor C12 is connected to one end of the inductor L3, and the other end of the inductor L3 is connected to the pulse receiving and small signal amplification circuit.

[0008] Furthermore, the pulse receiving and small signal amplifying circuit includes: a bidirectional limiting circuit Q6, a sensor J4, an inductor L4, a capacitor C16, a capacitor C21, a capacitor C22, a capacitor C25, a capacitor C26, a capacitor C27, a capacitor C28, a capacitor C29, a capacitor C30, a resistor R9, a resistor R10, a resistor R12, a resistor R13, a resistor R19, a resistor R20, a resistor R21, a resistor R22, a resistor R23, and a resistor R26. One end of the sensor J4 and one end of the inductor L4 are connected to the pulse wave power amplifying transmitting circuit, and the other end of the sensor J4 is connected to the pulse wave power amplifying transmitting circuit. The other end of the inductor L4 is connected to one end of the capacitor C27, one end of the resistor R19, and one end of the capacitor C25. The other end of the capacitor C27 and the other end of the resistor R19 are connected to the ground in parallel. The other end of the capacitor C25 is connected to one end of the capacitor C26 and the control electrode of the bidirectional limiting circuit Q6. The positive terminal and the negative terminal of the bidirectional limiting circuit Q6 are connected to the ground in parallel. The other end of the capacitor C26 is connected to one end of the resistor R12, one end of the resistor R20, and the base of the transistor Q5. The other end of the resistor R20 is grounded. The collector of the transistor Q5 is connected to the capacitor C 22 is connected to one end of the resistor R13, the other end of the resistor R12 is connected to the other end of the resistor R13 and one end of the capacitor C20 and connected to +12V, the other end of the capacitor C20 is grounded, the emitter of the transistor Q5 is connected to one end of the resistor R21, the other end of the resistor R21 is connected to one end of the resistor R26 and one end of the capacitor C30, the other end of the resistor R26 and the other end of the capacitor C30 are connected to the ground in parallel, the other end of the capacitor C22 is connected to one end of the resistor R9, one end of the resistor R22 and the base of the transistor Q4, the transistor The collector of Q4 is connected to one end of the resistor R10 and one end of the capacitor C21, the other end of the resistor R9 is connected to the other end of the resistor R10 and one end of the capacitor C16 and connected to +12V, the other end of the capacitor C16 is grounded, the other end of the resistor R22 is grounded, the emitter of the transistor Q4 is connected to one end of the resistor R23, one end of the capacitor C29 and one end of the capacitor C28, the other end of the resistor R23 and the other end of the capacitor C29 are connected to the ground in parallel, and the other end of the capacitor C21 and the other end of the capacitor C28 are respectively connected to the pulse wave phase orthogonal demodulation circuit.

[0009] Furthermore, the pulse wave phase orthogonal demodulation circuit includes: a dual-channel analog switch chip U3, a resistor R11, a resistor R14, a resistor R16, a resistor R17, a resistor R18, a resistor R25, a resistor R28, a resistor R29, a capacitor C17, and a capacitor C18, the 1st pin and the 8th pin of the dual-channel analog switch chip U3 are connected in parallel to the CPU6_1 port of the pulse timing control single-chip circuit, the 16th pin and the 9th pin of the dual-channel analog switch chip U3 are connected in parallel to the CPU7_1 port of the pulse timing control single-chip circuit, the 2nd pin and the 5th pin of the dual-channel analog switch chip U3 are connected to one end of the resistor R11 and one end of the resistor R16 and connected to the pulse receiving and small signal amplification circuit, the 7th pin and the 10th pin of the dual-channel analog switch chip U3 are connected to one end of the resistor R18 and one end of the resistor R25 and connected to the pulse receiving and small signal amplification circuit, The other end of the resistor R11 and the other end of the resistor R18 are respectively connected to +12V, the other end of the resistor R16 and the other end of the resistor R25 are respectively grounded, the 3rd pin and the 11th pin of the dual-way analog switch chip U3 are connected to one end of the resistor R17 and one end of the resistor R14, the 4th pin and the 14th pin of the dual-way analog switch chip U3 are connected to one end of the resistor R28 and one end of the resistor R29, the other end of the resistor R17 and the other end of the resistor R29 are respectively grounded, the other end of the resistor R14 and the resistor R28 are respectively connected to the differential signal conversion single-ended signal circuit, the 12th pin of the dual-way analog switch chip U3 is connected to one end of the capacitor C17 and connected to +5V, the 13th pin of the dual-way analog switch chip U3 is connected to one end of the capacitor C18 and connected to +12V, and the other end of the capacitor C17 and the other end of the capacitor C18 are respectively grounded.

[0010] Furthermore, the differential signal conversion single-ended signal circuit includes: an operational amplifier chip U2A, an operational amplifier chip U2B, an operational amplifier chip U4A, a capacitor C19, a capacitor C24, a capacitor C31, a resistor R15, a resistor R27, a resistor R24, and a resistor R8. The third pin of the operational amplifier chip U2A is connected to one end of the resistor R24 ​​and connected to the pulse wave phase orthogonal demodulation circuit, the fifth pin of the operational amplifier chip U2B is connected to one end of the capacitor C31 and connected to the pulse wave phase orthogonal demodulation circuit, the other end of the resistor R24 ​​and the other end of the capacitor C31 are grounded respectively, and the first pin of the operational amplifier chip U2A is connected to one end of the resistor R24 ​​and the other end of the capacitor C31 are grounded respectively. The 7th pin and the 6th pin of the operational amplifier chip U2B are connected to one end of the resistor R27, the 8th pin of the operational amplifier chip U2A is connected to one end of the capacitor C19 and connected to +12V, the other end of the resistor R15 is connected to one end of the resistor R8 and the 2nd pin of the operational amplifier chip U4A, the other end of the resistor R27 is connected to one end of the resistor R24 ​​and the 3rd pin of the operational amplifier chip U4A, the other end of the resistor R24 ​​is connected to the Vref1 port, and the other end of the resistor R8 is connected in parallel with the 1st pin of the operational amplifier chip U4A and connected to the filter circuit group.

[0011] Furthermore, the filter circuit group includes: two groups of active low-pass filter circuits and two groups of active high-pass filter circuits, and the active low-pass filter circuits and the active high-pass filter circuits are arranged in sequence and at intervals.

[0012] Furthermore, the active low-pass filter circuit includes: an operational amplifier chip U6A, a resistor R31, a resistor R34, a resistor R35, a resistor R38, a capacitor C35, and a capacitor C43, one end of the resistor R34 is connected to the differential signal conversion single-ended signal circuit or the front-end active high-pass filter circuit, the other end of the resistor R34 is connected to one end of the resistor R38, one end of the resistor R31, and one end of the capacitor C43, the other end of the capacitor C43 is grounded, the other end of the resistor R38 is connected to one end of the capacitor C35 and the second pin of the operational amplifier chip U6A, and the first pin of the operational amplifier chip U6A is connected in parallel with the other end of the capacitor C35 and the other end of the resistor R31 to the back-end active high-pass filter circuit.

[0013] Furthermore, the active high-pass filter circuit includes: an operational amplifier chip U6B, a capacitor C33, a capacitor C39, a capacitor C41, a resistor R33, and a resistor R39, one end of the capacitor C39 is connected to the active low-pass filter circuit at the front end, the other end of the capacitor C39 is connected to one end of the resistor R39, one end of the capacitor C41 and one end of the capacitor C33, the other end of the capacitor C41 is connected to one end of the resistor R33 and the 6th pin of the operational amplifier chip U6B, the other end of the resistor R39 is grounded, and the 7th pin of the operational amplifier chip U6B is connected in parallel with the other end of the capacitor C33 and the other end of the resistor R33 to the active low-pass filter circuit or the output end of the back end.

[0014] By adopting the above scheme, the utility model uses a pulse wave working mode and time-division multiplexing the entire piezoelectric sensor, thereby achieving 100% utilization of the sensor, and controls the transmission time of the ultrasonic wave to the designed depth through software control by using the transmission propagation and receiving return time of the sound wave in the water at 1500 meters / second, and then opens the receiving signal channel after waiting for the return time. The whole process realizes the function of the same sensor being able to both transmit and receive. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 This is the circuit diagram of the pulse timing control microcontroller circuit.

[0016] Figure 2 This is a circuit diagram of a pulse wave power amplification and transmission circuit.

[0017] Figure 3 This is the circuit diagram of the pulse receiving and small signal amplifying circuit.

[0018] Figure 4 This is the circuit diagram of the pulse wave phase orthogonal demodulation circuit.

[0019] Figure 5 This is a circuit diagram for converting differential signals into single-ended signals.

[0020] Figure 6 This is a circuit diagram of the filter circuit group.

[0021] Figure 7 Figure 2 is a circuit diagram of an active low-pass filter circuit.

[0022] Figure 8 Figure 2 is a circuit diagram of an active high-pass filter circuit. DETAILED DESCRIPTION

[0023] The present invention is described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0024] See also Figures 1 to 8The utility model provides a pulse circuit of FD-121 pulse fetal heart rate monitor, including: pulse timing control single chip microcomputer circuit, pulse wave power amplification and transmission circuit, pulse receiving and small signal amplification circuit, pulse wave phase quadrature demodulation circuit, differential signal conversion single-ended signal circuit, and filter circuit group, the pulse timing control single chip microcomputer circuit is electrically connected to the pulse wave power amplification and transmission circuit, the two ends of the pulse receiving and small signal amplification circuit are respectively electrically connected to the pulse wave power amplification and transmission circuit and the pulse wave phase quadrature demodulation circuit, and the two ends of the differential signal conversion single-ended signal circuit are respectively electrically connected to the pulse wave phase quadrature demodulation circuit and the filter circuit group. By adopting the pulse wave working mode and time-division multiplexing the entire piezoelectric sensor, the sensor can be 100% utilized, and the transmission and reception return time of the sound wave in the water is 1500 meters / second. The sending time of the ultrasonic wave is controlled by software to transmit to the designed depth, and then the receiving signal channel is opened after waiting for the return time. The whole process realizes the function that the same sensor can both transmit and receive.

[0025] See also Figure 1 The pulse timing control single-chip circuit includes: single-chip J2, crystal oscillator Y1, capacitor C6, and capacitor C9. The second pin of the single-chip J2 is connected to one end of the crystal oscillator Y1 and one end of the capacitor C6. The third pin of the single-chip J2 is connected to the other end of the crystal oscillator Y1 and one end of the capacitor C9. The other end of the capacitor C6 and the other end of the capacitor C9 are connected to the ground in parallel. The 11th pin of the single-chip J2 is electrically connected to the pulse wave power amplification transmitting circuit. This circuit is the core part of the pulse wave fetal heart rate monitor, and its functions are as follows: (1) Generate the transmitting frequency required by the matching sensor (2MHZ in this circuit); (2) Control the transmission time of the transmitting frequency, which is 96us in this circuit; (3) Control the time to wait for the return ultrasound of the deepest reflection surface, which is 32us in this circuit; (4) Control the opening time of the receiving signal circuit, which is 128us in this circuit; (5) When the reception is turned on, generate the demodulation waveform corresponding to the sensor resonant frequency required for demodulation to realize the extraction of Doppler frequency shift signal.

[0026] See also Figure 2The pulse wave power amplification transmitting circuit includes: a resistor R4, a resistor R5, a resistor R7, an inductor L2, an inductor L3, a transistor Q1, a transistor Q2, a transistor Q3, a polarity capacitor C8, a polarity capacitor C10, a capacitor C7, a capacitor C11, a capacitor C12 and a capacitor C13. One end of the capacitor C13 and one end of the resistor R7 are connected in parallel to the CPUB_1 port of the pulse timing control single-chip circuit. The other end of the capacitor C13 is connected to the other end of the resistor R7 and the base of the transistor Q2. The emitter of the transistor Q2 is grounded. The collector of the transistor Q2 is connected to the base of the transistor Q1, the base of the transistor Q3 and one end of the resistor R5. The other end of the resistor R5 is connected to the collector of the transistor Q1. The first electrode, one end of the resistor R4, the positive terminal of the polar capacitor C8, and one end of the capacitor C7 are connected, the negative terminal of the polar capacitor C8 and the other end of the capacitor C7 are connected in parallel to the ground, the other end of the resistor R4 and one end of the inductor L2 are connected to D+12V respectively, the other end of the inductor L2 and the positive terminal of the polar capacitor C10 and one end of the capacitor C11 are connected in parallel to +12V, the negative terminal of the polar capacitor C10 and the other end of the capacitor C11 are connected in parallel to the ground, the emitter of the transistor Q1 is connected to the emitter of the transistor Q3 and one end of the capacitor C12, the collector of the transistor Q3 is grounded, the other end of the capacitor C12 is connected to one end of the inductor L3, and the other end of the inductor L3 is connected to the pulse receiving and small signal amplification circuit. The 2MHz local oscillator signal passes through the capacitor C13 and the resistor R7 parallel frequency selection network, and then is amplified by the transistor push-pull power amplifier circuit composed of transistors Q1, Q2 and Q3. Finally, it is input to the 2MHz piezoelectric sensor through the series resonant network composed of inductor L3 and capacitor C12 to generate corresponding ultrasonic vibration waves.

[0027] See also Figure 3The pulse receiving and small signal amplifying circuit includes: a bidirectional limiting circuit Q6, a sensor J4, an inductor L4, a capacitor C16, a capacitor C21, a capacitor C22, a capacitor C25, a capacitor C26, a capacitor C27, a capacitor C28, a capacitor C29, a capacitor C30, a resistor R9, a resistor R10, a resistor R12, a resistor R13, a resistor R19, a resistor R20, a resistor R21, a resistor R22, a resistor R23, and a resistor R26. One end of the sensor J4 and one end of the inductor L4 are connected to the pulse wave power amplifying and transmitting circuit, and the other end of the sensor J4 is grounded. The other end of the inductor L4 is connected to one end of the capacitor C27, one end of the resistor R19, and one end of the capacitor C25. The other end of the capacitor C27 and the other end of the resistor R19 are connected to the ground in parallel. The other end of the capacitor C25 is connected to one end of the capacitor C26 and the control electrode of the bidirectional limiting circuit Q6. The positive terminal and the negative terminal of the bidirectional limiting circuit Q6 are connected to the ground in parallel. The other end of the capacitor C26 is connected to one end of the resistor R12, one end of the resistor R20, and the base of the transistor Q5. The other end of the resistor R20 is grounded. The collector of the transistor Q5 is connected to the capacitor C22. The other end of the resistor R12 is connected to the other end of the resistor R13 and one end of the capacitor C20 and connected to +12V, the other end of the capacitor C20 is grounded, the emitter of the transistor Q5 is connected to one end of the resistor R21, the other end of the resistor R21 is connected to one end of the resistor R26 and one end of the capacitor C30, the other end of the resistor R26 and the other end of the capacitor C30 are connected to the ground in parallel, the other end of the capacitor C22 is connected to one end of the resistor R9, one end of the resistor R22 and the base of the transistor Q4, the transistor Q The collector of transistor Q4 is connected to one end of resistor R10 and one end of capacitor C21, the other end of resistor R9 is connected to the other end of resistor R10 and one end of capacitor C16 and connected to +12V, the other end of capacitor C16 is grounded, the other end of resistor R22 is grounded, the emitter of transistor Q4 is connected to one end of resistor R23, one end of capacitor C29 and one end of capacitor C28, the other end of resistor R23 and the other end of capacitor C29 are connected to the ground in parallel, and the other end of capacitor C21 and the other end of capacitor C28 are respectively connected to the pulse wave phase quadrature demodulation circuit. When the pulse wave power amplification transmitting circuit transmits 2MHz ultrasonic waves through sensor J4, the receiving circuit is in a closed state and does not process signals. After waiting for a delay of 32μs, the analog switch is turned on by the single-chip microcomputer. The received ultrasonic frequency shift signal is transmitted to the base of the first-stage amplifier circuit transistor Q5 through the series-connected frequency selection network inductor L4 and capacitor C25 via the bidirectional limiting circuit Q6. After the first amplification, it is amplified twice by the second-stage amplifier circuit transistor Q4 to obtain a Doppler signal with a larger amplitude.

[0028] See also Figure 4 The pulse wave phase quadrature demodulation circuit includes: a dual-channel analog switch chip U3, a resistor R11, a resistor R14, a resistor R16, a resistor R17, a resistor R18, a resistor R25, a resistor R28, a resistor R29, a capacitor C17, and a capacitor C18. The 1st pin and the 8th pin of the dual-channel analog switch chip U3 are connected in parallel to the CPU6_1 port of the pulse timing control single-chip circuit. The 16th pin and the 9th pin of the dual-channel analog switch chip U3 are connected in parallel to the CPU7_1 port of the pulse timing control single-chip circuit. The 2nd pin and the 5th pin of the dual-channel analog switch chip U3 are connected to one end of the resistor R11 and one end of the resistor R16 and connected to the pulse receiving and small signal amplification circuit. The 7th pin and the 10th pin of the dual-channel analog switch chip U3 are connected to one end of the resistor R18 and one end of the resistor R25 and connected to the pulse receiving and small signal amplification circuit. The other end of the resistor R11 and the other end of the resistor R18 are connected to +12V respectively, the other end of the resistor R16 and the other end of the resistor R25 are grounded respectively, the 3rd pin and the 11th pin of the dual-channel analog switch chip U3 are connected to one end of the resistor R17 and one end of the resistor R14, the 4th pin and the 14th pin of the dual-channel analog switch chip U3 are connected to one end of the resistor R28 and one end of the resistor R29, the other end of the resistor R17 and the other end of the resistor R29 are grounded respectively, the other end of the resistor R14 and the resistor R28 are connected to the differential signal conversion single-ended signal circuit respectively, the 12th pin of the dual-channel analog switch chip U3 is connected to one end of the capacitor C17 and connected to +5V, the 13th pin of the dual-channel analog switch chip U3 is connected to one end of the capacitor C18 and connected to +12V, and the other end of the capacitor C17 and the other end of the capacitor C18 are grounded respectively. After the two-stage triode small signal amplification, two receiving signals with a 2MHz carrier signal with a phase difference of 180 degrees are taken respectively. The pulse wave phase quadrature demodulation circuit is composed of a dual-channel analog switch chip U3. The single-chip microcomputer generates two 2MHz demodulation signals with opposite phases. Under the action of the analog switch, an analog multiplier operation result is generated, and finally the fetal heart audio signal is extracted from the carrier.

[0029] See also Figure 5The differential signal conversion single-ended signal circuit includes: an operational amplifier chip U2A, an operational amplifier chip U2B, an operational amplifier chip U4A, a capacitor C19, a capacitor C24, a capacitor C31, a resistor R15, a resistor R27, a resistor R24, and a resistor R8. The third pin of the operational amplifier chip U2A is connected to one end of the resistor R24 ​​and connected to the pulse wave phase orthogonal demodulation circuit. The fifth pin of the operational amplifier chip U2B is connected to one end of the capacitor C31 and connected to the pulse wave phase orthogonal demodulation circuit. The other end of the resistor R24 ​​and the other end of the capacitor C31 are grounded respectively. The first pin, Pin 2 is connected to one end of resistor R15, Pin 7 and Pin 6 of the operational amplifier chip U2B are connected to one end of resistor R27, Pin 8 of the operational amplifier chip U2A is connected to one end of capacitor C19 and connected to +12V, the other end of the resistor R15 is connected to one end of resistor R8 and Pin 2 of the operational amplifier chip U4A, the other end of the resistor R27 is connected to one end of resistor R24 ​​and Pin 3 of the operational amplifier chip U4A, the other end of the resistor R24 ​​is connected to the Vref1 port, and the other end of the resistor R8 is connected in parallel to Pin 1 of the operational amplifier chip U4A and connected to the filter circuit group. The demodulated fetal heart audio signal is a differential signal, which is not convenient for the subsequent circuit to process. The differential signal conversion single-ended signal circuit consists of three groups of operational amplifiers to form a first-stage instrument amplifier, which converts the differential signal into a single-ended signal for output.

[0030] See also Figure 6 The filter circuit group includes: two groups of active low-pass filter circuits and two groups of active high-pass filter circuits, and the active low-pass filter circuits and the active high-pass filter circuits are arranged in sequence and at intervals.

[0031] See also Figure 7 The active low-pass filter circuit includes: an operational amplifier chip U6A, a resistor R31, a resistor R34, a resistor R35, a resistor R38, a capacitor C35, and a capacitor C43, one end of the resistor R34 is connected to a differential signal conversion single-ended signal circuit or a front-end active high-pass filter circuit, the other end of the resistor R34 is connected to one end of a resistor R38, one end of a resistor R31, and one end of a capacitor C43, the other end of the capacitor C43 is grounded, the other end of the resistor R38 is connected to one end of a capacitor C35 and the second pin of the operational amplifier chip U6A, the first pin of the operational amplifier chip U6A is connected in parallel with the other end of the capacitor C35 and the other end of the resistor R31 to the back-end active high-pass filter circuit.

[0032] See also Figure 8The active high-pass filter circuit includes: an operational amplifier chip U6B, a capacitor C33, a capacitor C39, a capacitor C41, a resistor R33, and a resistor R39, one end of the capacitor C39 is connected to the active low-pass filter circuit at the front end, the other end of the capacitor C39 is connected to one end of the resistor R39, one end of the capacitor C41 and one end of the capacitor C33, the other end of the capacitor C41 is connected to one end of the resistor R33 and the 6th pin of the operational amplifier chip U6B, the other end of the resistor R39 is grounded, and the 7th pin of the operational amplifier chip U6B is connected in parallel with the other end of the capacitor C33 and the other end of the resistor R33 to the active low-pass filter circuit or the output end of the back end.

[0033] The fetal heart audio converted into a single-ended signal is input into the first-stage active low-pass filter circuit. Since the signal is demodulated, there is a lot of high-frequency interference noise in the signal. Therefore, an active low-pass filter circuit is used to filter out the high-frequency interference noise. In the first-stage active low-pass filter circuit, the cutoff frequency is 2KHz.

[0034] The fetal heart audio signal passing through the active low-pass filter circuit will have obvious signal attenuation. Therefore, an active high-pass filter circuit with a cut-off frequency of 50Hz is used to filter out power frequency interference on the one hand, and on the other hand, effectively amplify the fetal heart signal to provide current driving capability for the subsequent circuit.

[0035] The frequency range of the secondary active low-pass filter circuit and the secondary active high-pass filter circuit is 50-500Hz. The secondary active low-pass filter circuit is used to further filter out noise, and the fetal heart audio signal is effectively amplified by the secondary active high-pass filter circuit, so that there is a steep attenuation effect at the cutoff frequency.

[0036] In summary, the utility model adopts the pulse wave working mode and time-division multiplexing of the entire piezoelectric sensor to achieve 100% utilization of the sensor. By using the transmission and reception return time of the sound wave in the water at 1500 m / s, the sending time of the ultrasonic wave is controlled by software to transmit to the designed depth, and then the receiving signal channel is opened after waiting for the return time. The whole process realizes the function of the same sensor being able to both transmit and receive.

[0037] The above are only preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. An FD-121 fetal heart rate monitor pulse circuit, characterized in that: include: A pulse timing control single-chip microcomputer circuit, a pulse wave power amplification and transmission circuit, a pulse receiving and small signal amplification circuit, a pulse wave phase orthogonal demodulation circuit, a differential signal conversion single-ended signal circuit, and a filter circuit group. The pulse timing control single-chip microcomputer circuit is electrically connected to the pulse wave power amplification and transmission circuit, and the two ends of the pulse receiving and small signal amplification circuit are respectively electrically connected to the pulse wave power amplification and transmission circuit and the pulse wave phase orthogonal demodulation circuit, and the two ends of the differential signal conversion single-ended signal circuit are respectively electrically connected to the pulse wave phase orthogonal demodulation circuit and the filter circuit group.

2. The FD-121 fetal heart rate monitor pulse circuit according to claim 1, characterized in that: The pulse timing control single-chip microcomputer circuit includes: a single-chip microcomputer J2, a crystal oscillator Y1, a capacitor C6, and a capacitor C9. The second pin of the single-chip microcomputer J2 is connected to one end of the crystal oscillator Y1 and one end of the capacitor C6. The third pin of the single-chip microcomputer J2 is connected to the other end of the crystal oscillator Y1 and one end of the capacitor C9. The other end of the capacitor C6 and the other end of the capacitor C9 are connected to the ground in parallel. The 11th pin of the single-chip microcomputer J2 is electrically connected to the pulse wave power amplification transmitting circuit.

3. The FD-121 fetal heart rate monitor pulse circuit according to claim 1, characterized in that: The pulse wave power amplification and transmission circuit includes: a resistor R4, a resistor R5, a resistor R7, an inductor L2, an inductor L3, a transistor Q1, a transistor Q2, a transistor Q3, a polarity capacitor C8, a polarity capacitor C10, a capacitor C7, a capacitor C11, a capacitor C12 and a capacitor C13. One end of the capacitor C13 and one end of the resistor R7 are connected in parallel to the CPUB_1 port of the pulse timing control single-chip circuit. The other end of the capacitor C13 is connected to the other end of the resistor R7 and the base of the transistor Q2. The emitter of the transistor Q2 is grounded. The collector of the transistor Q2 is connected to the base of the transistor Q1, the base of the transistor Q3 and one end of the resistor R5. The other end of the resistor R5 is connected to the collector of the transistor Q1. , one end of the resistor R4, the positive end of the polar capacitor C8, and one end of the capacitor C7 are connected, the negative end of the polar capacitor C8 and the other end of the capacitor C7 are connected in parallel to the ground, the other end of the resistor R4 and one end of the inductor L2 are connected to D+12V respectively, the other end of the inductor L2 and the positive end of the polar capacitor C10 and one end of the capacitor C11 are connected in parallel to +12V, the negative end of the polar capacitor C10 and the other end of the capacitor C11 are connected in parallel to the ground, the emitter of the transistor Q1 is connected to the emitter of the transistor Q3 and one end of the capacitor C12, the collector of the transistor Q3 is grounded, the other end of the capacitor C12 is connected to one end of the inductor L3, and the other end of the inductor L3 is connected to the pulse receiving and small signal amplification circuit.

4. The FD-121 fetal heart rate monitor pulse circuit according to claim 1, characterized in that: The pulse receiving and small signal amplifying circuit includes: a bidirectional limiting circuit Q6, a sensor J4, an inductor L4, a capacitor C16, a capacitor C21, a capacitor C22, a capacitor C25, a capacitor C26, a capacitor C27, a capacitor C28, a capacitor C29, a capacitor C30, a resistor R9, a resistor R10, a resistor R12, a resistor R13, a resistor R19, a resistor R20, a resistor R21, a resistor R22, a resistor R23, and a resistor R26. One end of the sensor J4 and one end of the inductor L4 are connected to the pulse wave power amplifying and transmitting circuit, and the other end of the sensor J4 is grounded. The other end of the inductor L4 is connected to one end of the capacitor C27, one end of the resistor R19, and one end of the capacitor C25. The other end of the capacitor C27 and the other end of the resistor R19 are connected to the ground in parallel. The other end of the capacitor C25 is connected to one end of the capacitor C26 and the control electrode of the bidirectional limiting circuit Q6. The positive terminal and the negative terminal of the bidirectional limiting circuit Q6 are connected to the ground in parallel. The other end of the capacitor C26 is connected to one end of the resistor R12, one end of the resistor R20, and the base of the transistor Q5. The other end of the resistor R20 is grounded. The collector of the transistor Q5 is connected to the capacitor C22. The other end of the resistor R12 is connected to the other end of the resistor R13 and one end of the capacitor C20 and connected to +12V, the other end of the capacitor C20 is grounded, the emitter of the transistor Q5 is connected to one end of the resistor R21, the other end of the resistor R21 is connected to one end of the resistor R26 and one end of the capacitor C30, the other end of the resistor R26 and the other end of the capacitor C30 are connected to the ground in parallel, the other end of the capacitor C22 is connected to one end of the resistor R9, one end of the resistor R22 and the base of the transistor Q4, the transistor Q The collector of transistor Q4 is connected to one end of resistor R10 and one end of capacitor C21, the other end of resistor R9 is connected to the other end of resistor R10 and one end of capacitor C16 and connected to +12V, the other end of capacitor C16 is grounded, the other end of resistor R22 is grounded, the emitter of transistor Q4 is connected to one end of resistor R23, one end of capacitor C29 and one end of capacitor C28, the other end of resistor R23 and the other end of capacitor C29 are connected to ground in parallel, and the other end of capacitor C21 and the other end of capacitor C28 are respectively connected to the pulse wave phase orthogonal demodulation circuit.

5. The FD-121 fetal heart rate monitor pulse circuit according to claim 1, characterized in that: The pulse wave phase quadrature demodulation circuit includes: a dual-channel analog switch chip U3, a resistor R11, a resistor R14, a resistor R16, a resistor R17, a resistor R18, a resistor R25, a resistor R28, a resistor R29, a capacitor C17, and a capacitor C18. The 1st pin and the 8th pin of the dual-channel analog switch chip U3 are connected in parallel to the CPU6_1 port of the pulse timing control single-chip circuit. The 16th pin and the 9th pin of the dual-channel analog switch chip U3 are connected in parallel to the CPU7_1 port of the pulse timing control single-chip circuit. The 2nd pin and the 5th pin of the dual-channel analog switch chip U3 are connected to one end of the resistor R11 and one end of the resistor R16 and connected to the pulse receiving and small signal amplification circuit. The 7th pin and the 10th pin of the dual-channel analog switch chip U3 are connected to one end of the resistor R18 and one end of the resistor R25 and connected to the pulse receiving and small signal amplification circuit. The other end of the resistor R11 and the other end of the resistor R18 are respectively connected to +12V, the other end of the resistor R16 and the other end of the resistor R25 are respectively grounded, the 3rd pin and the 11th pin of the dual-way analog switch chip U3 are connected to one end of the resistor R17 and one end of the resistor R14, the 4th pin and the 14th pin of the dual-way analog switch chip U3 are connected to one end of the resistor R28 and one end of the resistor R29, the other end of the resistor R17 and the other end of the resistor R29 are respectively grounded, the other end of the resistor R14 and the resistor R28 are respectively connected to the differential signal conversion single-ended signal circuit, the 12th pin of the dual-way analog switch chip U3 is connected to one end of the capacitor C17 and connected to +5V, the 13th pin of the dual-way analog switch chip U3 is connected to one end of the capacitor C18 and connected to +12V, and the other end of the capacitor C17 and the other end of the capacitor C18 are respectively grounded.

6. The FD-121 fetal heart rate monitor pulse circuit according to claim 1, characterized in that: The differential signal conversion single-ended signal circuit includes: an operational amplifier chip U2A, an operational amplifier chip U2B, an operational amplifier chip U4A, a capacitor C19, a capacitor C24, a capacitor C31, a resistor R15, a resistor R27, a resistor R24, and a resistor R8. The third pin of the operational amplifier chip U2A is connected to one end of the resistor R24 ​​and connected to a pulse wave phase orthogonal demodulation circuit. The fifth pin of the operational amplifier chip U2B is connected to one end of the capacitor C31 and connected to the pulse wave phase orthogonal demodulation circuit. The other end of the resistor R24 ​​and the other end of the capacitor C31 are grounded respectively. The first pin and the fifth pin of the operational amplifier chip U2A are connected to one end of the resistor R24 ​​and the capacitor C31 are grounded respectively. Pin 2 is connected to one end of the resistor R15, the 7th pin and the 6th pin of the operational amplifier chip U2B are connected to one end of the resistor R27, the 8th pin of the operational amplifier chip U2A is connected to one end of the capacitor C19 and connected to +12V, the other end of the resistor R15 is connected to one end of the resistor R8 and the 2nd pin of the operational amplifier chip U4A, the other end of the resistor R27 is connected to one end of the resistor R24 ​​and the 3rd pin of the operational amplifier chip U4A, the other end of the resistor R24 ​​is connected to the Vref1 port, and the other end of the resistor R8 is connected in parallel with the 1st pin of the operational amplifier chip U4A and connected to the filter circuit group.

7. The FD-121 fetal heart rate monitor pulse circuit according to claim 1, characterized in that: The filter circuit group includes: two groups of active low-pass filter circuits and two groups of active high-pass filter circuits, and the active low-pass filter circuits and the active high-pass filter circuits are arranged in sequence and at intervals.

8. The FD-121 fetal heart rate monitor pulse circuit according to claim 7, characterized in that: The active low-pass filter circuit includes: an operational amplifier chip U6A, a resistor R31, a resistor R34, a resistor R35, a resistor R38, a capacitor C35, and a capacitor C43. One end of the resistor R34 is connected to a differential signal conversion single-ended signal circuit or a front-end active high-pass filter circuit. The other end of the resistor R34 is connected to one end of a resistor R38, one end of a resistor R31, and one end of a capacitor C43. The other end of the capacitor C43 is grounded. The other end of the resistor R38 is connected to one end of a capacitor C35 and the second pin of the operational amplifier chip U6A. The first pin of the operational amplifier chip U6A is connected in parallel with the other end of the capacitor C35 and the other end of the resistor R31 to the back-end active high-pass filter circuit.

9. The FD-121 fetal heart rate monitor pulse circuit according to claim 7, characterized in that: The active high-pass filter circuit includes: an operational amplifier chip U6B, a capacitor C33, a capacitor C39, a capacitor C41, a resistor R33, and a resistor R39. One end of the capacitor C39 is connected to the active low-pass filter circuit at the front end, the other end of the capacitor C39 is connected to one end of the resistor R39, one end of the capacitor C41, and one end of the capacitor C33. The other end of the capacitor C41 is connected to one end of the resistor R33 and the 6th pin of the operational amplifier chip U6B. The other end of the resistor R39 is grounded. The 7th pin of the operational amplifier chip U6B is connected in parallel with the other end of the capacitor C33 and the other end of the resistor R33 to the active low-pass filter circuit or the output end of the back end.

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