Integrated circuit with nine-port input and nine-port image splicing matrix output and electronic equipment

Abstract

The utility model discloses an integrated circuit with nine-port input and nine-port image splicing matrix output and an electronic device, and relates to the field of image video splicing matrices, the integrated circuit comprises nine HDMI input interfaces and HDMI input conversion chips which are correspondingly connected; the first FPGA is connected with the first HDMI input conversion chip to the fourth HDMI input conversion chip; the second FPGA is connected with the fifth to eight HDMI input conversion chips; the nine HDMI output conversion chips and the nine HDMI output interfaces are correspondingly connected; the third FPGA is connected with the ninth HDMI input conversion chip, the first FPGA, the second FPGA, the first HDMI conversion chip, the second HDMI conversion chip, the third HDMI conversion chip and the fourth HDMI conversion chip; the fourth FPGA is connected with the third FPGA and connected with the fifth HDMI conversion chip, the sixth HDMI conversion chip and the ninth HDMI conversion chip; and the micro-control unit is used for controlling each connected element. The cost can be saved.

Description

Technical Field

[0001] The utility model relates to the technical field of image and video splicing matrices, in particular to an integrated circuit and electronic equipment with nine-port inputs and nine-port image splicing matrix outputs. Background Art

[0002] The multi-interface image card splicing matrix server is a high-end video signal processing device, which is mainly used to achieve efficient management and high-quality display of multiple video signal sources to multi-screen display systems.

[0003] At present, conventional multi-interface image card splicing matrix servers are usually composed of multiple integrated boards to achieve multi-interface input and multi-channel image processing. However, the multiple integrated boards in this type of multi-interface image card splicing matrix server will increase the size and weight of the equipment, as well as increase the cost and have poor applicability.

[0004] In summary, how to reduce the cost of integrated circuit boards in a multi-interface image card splicing matrix server has become an urgent problem to be solved in this field. Utility Model Content

[0005] The main purpose of the utility model is to provide an integrated circuit and electronic equipment with nine-port input and nine-port image splicing matrix output, aiming to solve the technical problem of how to reduce the cost of integrated circuit boards in a multi-interface image card splicing matrix server.

[0006] To achieve the above object, the utility model provides an integrated circuit with nine inputs and nine image stitching matrix outputs, the integrated circuit with nine inputs and nine image stitching matrix outputs comprising: nine HDMI (High Definition Multimedia Interface) input interfaces for connecting external image devices;

[0007] Nine HDMI input conversion chips, each of which is connected to each of the HDMI input interfaces in a one-to-one correspondence, and is used to convert the input HDMI signal into an RGB (a color representation method based on a red, green, and blue primary color light model) signal;

[0008] A first FPGA (Field-Programmable Gate Array), connected to the first to fourth HDMI input conversion chips among the HDMI input conversion chips, for encoding and packaging the received RGB signals into image data;

[0009] A second FPGA, connected to the fifth to eighth HDMI input conversion chips among the HDMI input conversion chips, and used for encoding and packaging the received RGB signals into image data;

[0010] Nine HDMI output conversion chips, used to convert received YUV (a color encoding method) signals into HDMI signals;

[0011] Nine HDMI output interfaces, each of which is connected to each of the HDMI output conversion chips in a one-to-one correspondence, and is used to connect to an external display device;

[0012] A third FPGA is connected to the ninth HDMI input conversion chip of the HDMI input conversion chips, and is connected to the first FPGA and the second FPGA, and is also connected to the first to fourth HDMI conversion chips in the HDMI output interfaces to package the received RGB signals into image data, and splice the received image data into YUV signals;

[0013] A fourth FPGA, connected to the third FPGA and connected to the fifth to ninth HDMI conversion chips in each of the HDMI output interfaces, for splicing the received image data into a YUV signal;

[0014] A micro control unit is used to control the connected HDMI input conversion chips, the connected HDMI output conversion chips, the first FPGA, the second FPGA, the third FPGA and the fourth FPGA.

[0015] Optionally, for each set of HDMI input interface and HDMI input conversion chip, after the HDMI input interface is connected to an external imaging device, the HDMI signal is input to the HDMI input conversion chip through the HDMI input interface, and the HDMI input chip converts the input HDMI signal into an RGB signal, and outputs the RGB signal to the first FPGA or the second FPGA.

[0016] Optionally, the first FPGA receives RGB signals output by the first to fourth HDMI input conversion chips among the HDMI input conversion chips, and outputs the RGB signals to the third FPGA;

[0017] The second FPGA receives the RGB signals output by the fifth to eighth HDMI input conversion chips among the HDMI input conversion chips, and outputs the RGB signals to the third FPGA;

[0018] The third FPGA receives the RGB signals input by the first FPGA and the second FPGA, receives the RGB signals output by the ninth HDMI input conversion chip among the HDMI input conversion chips, stores the received RGB signals in the first memory, and outputs them to the fourth FPGA;

[0019] The fourth FPGA stores the received RGB signal into the second memory;

[0020] The third FPGA and the fourth FPGA respectively edit and splice the RGB signals stored in the first memory and the second memory in response to the instructions output by the micro control unit to obtain YUV signals, and then output them to the connected HDMI output conversion chips respectively.

[0021] Optionally, for each set of HDMI output conversion chip and HDMI output interface, the HDMI output conversion chip converts the received YUV signal into an HDMI signal, and then outputs it to the connected HDMI output interface, and the HDMI output interface outputs the HDMI signal to the connected external display device.

[0022] Optionally, the micro control unit is connected to each of the HDMI input conversion chips, each of the HDMI output conversion chips, the first FPGA, the second FPGA, the third FPGA and the fourth FPGA respectively through a multiplexer or a signal separator chip.

[0023] Optionally, the integrated circuit further comprises: a multi-frequency division clock signal chip;

[0024] The multi-frequency clock signal chip is respectively connected to the third FPGA, the fourth FPGA, the first memory and the second memory to ensure synchronous output of the circuit.

[0025] Optionally, the integrated circuit further includes:

[0026] A power supply step-by-step conversion circuit, used to convert an external 220V voltage into a 12V voltage, then convert the 12V voltage into a 5V voltage, and then convert the 5V voltage into a 3.3V voltage, and use the 3.3V voltage to power the microcontroller unit, the multi-frequency clock signal chip, the first FPGA, the second FPGA, the third FPGA, and the fourth FPGA;

[0027] The 3.3V voltage is converted into 1.5V and 0.75V voltages to power the first memory and the second memory.

[0028] In addition, to achieve the above-mentioned purpose, the utility model also provides an electronic device, including the integrated circuit with nine-port input and nine-port image splicing matrix output as described above.

[0029] Optionally, the electronic device also includes a 1U architecture chassis.

[0030] Optionally, the electronic device further includes an image server power supply, which supplies power to the integrated circuit.

[0031] In the technical solution of the utility model, nine HDMI input interfaces and output interfaces are integrated into one integrated circuit, and four FPGAs are used to realize the transmission and editing splicing of image signals, and a conversion chip is used to realize the conversion of signal formats, so that the integrated circuit can process and output multi-channel input HDMI signals at the same time, making maximum use of the resources of the FPGA chip, reducing the number of circuit boards such as input cards, output cards, control cards, and switching boards compared to the traditional splicing matrix, and reducing the cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the embodiments of the utility model or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the utility model. For ordinary technicians in this field, other drawings can be obtained based on the structures shown in these drawings without paying creative work.

[0033] Figure 1 It is a schematic diagram of the framework of the integrated circuit with nine-port input and nine-port image splicing matrix output of the utility model;

[0034] Figure 2 A circuit diagram of the input interface of the integrated circuit with nine input ports and nine image splicing matrix output ports of the utility model;

[0035] Figure 3 A circuit diagram of the input interface of the integrated circuit with nine input ports and nine image splicing matrix output ports of the utility model;

[0036] Figure 4 It is a schematic diagram of the image editing and splicing processing circuit framework of the integrated circuit of the utility model with nine-port input and nine-port image splicing matrix output;

[0037] Figure 5 It is a flow chart of the MCU control circuit of the integrated circuit with nine-port input and nine-port image splicing matrix output of the utility model;

[0038] Figure 6 A block flow chart of a clock frequency supply circuit for an integrated circuit with nine input ports and nine image splicing matrix output ports of the utility model;

[0039] Figure 7A block diagram of the power supply for the power conversion circuit portion of the integrated circuit with nine input ports and nine image splicing matrix output ports of the utility model.

[0040] Description of Figure Numbers:

[0041]

[0042]

[0043] The realization of the purpose, functional features and advantages of the present invention will be further described in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0044] The following will be combined with the drawings in the embodiments of the utility model to clearly and completely describe the technical solutions in the embodiments of the utility model. Obviously, the described embodiments are only part of the embodiments of the utility model, not all of the embodiments. Based on the embodiments of the utility model, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the utility model.

[0045] It should be noted that if the embodiments of the present invention involve directional indications (such as up, down, left, right, front, back...), the directional indications are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0046] In addition, if there are descriptions involving "first", "second", etc. in the embodiments of the utility model, the descriptions of "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or suggesting their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of ordinary technicians in the field to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by the utility model.

[0047] Reference Figure 1 As shown, Figure 1 The utility model provides a framework schematic diagram of an integrated circuit 10 with nine-port input and nine-port image stitching matrix output, and the integrated circuit with nine-port input and nine-port image stitching matrix output includes: nine HDMI input interfaces (11 to 19) for connecting external image devices;

[0048] Nine HDMI input conversion chips (21 to 29), each of which is connected to each of the HDMI input interfaces in a one-to-one correspondence, and is used to convert an input HDMI signal into an RGB signal;

[0049] The first FPGA 30 is connected to the first to fourth HDMI input conversion chips among the HDMI input conversion chips, and is used to encode and package the received RGB signals into image data;

[0050] The second FPGA 40 is connected to the fifth to eighth HDMI input conversion chips among the HDMI input conversion chips, and is used to encode and package the received RGB signals into image data;

[0051] Nine HDMI output conversion chips (81 to 89) for converting received YUV signals into HDMI signals;

[0052] Nine HDMI output interfaces (91 to 99), each of which is connected to each of the HDMI output conversion chips in a one-to-one correspondence, and is used to connect to an external display device;

[0053] The third FPGA 50 is connected to the ninth HDMI input conversion chip of the HDMI input conversion chips, and is connected to the first FPGA and the second FPGA, and is also connected to the first to fourth HDMI conversion chips of the HDMI output interfaces for packaging the received RGB signals into image data, and splicing the received image data into YUV signals;

[0054] A fourth FPGA 60, connected to the third FPGA and connected to the fifth to ninth HDMI conversion chips in each of the HDMI output interfaces, for splicing the received image data into a YUV signal;

[0055] The micro control unit 70 is used to control the connected HDMI input conversion chips, the connected HDMI output conversion chips, the first FPGA, the second FPGA, the third FPGA and the fourth FPGA.

[0056] In this embodiment, the HDMI signal is input into the technical product through the external device, and the image signal is decomposed into RGB-TTL 24-bit signal through the HDMI conversion chip. RGB usually refers to the red, green and blue three-primary color signals. Each color signal occupies 8 bits, so it is 24 bits. In this core circuit board, each conversion chip outputs 24 equal-length data lines. A total of 9 chips (input 9 HDMI signals) are connected to FPGA1 and FPGA2. Each data line uses TTL level to transmit the three-primary color signal. FPGA1 and FPGA2 identify the 0 and 1 in the 24-bit three-primary color equal-length data lines, arrange and package them, and package the arranged data lines. The image data is sent to FPGA3 and FPGA4 through the SerDes high-speed data bus interface of the chip. When FPGA3 and FPGA4 receive the image signals, they are decompressed and cached in DDR3 memory. In addition, FPGA3 and FPGA4 can also receive the configuration instructions sent by MCU through the IIC bus, which is how to splice the video image signals in DDR. After splicing, it is transmitted to the HDMI conversion chip in the form of YUV-TTL level for YUV-TTL to HDMI image signal operation. FPGA3 and FPGA4 can output 9 channels of YUV-TTL (16Bit) at the same time. When the conversion chip converts the YUV-TTL signal into HDMI signal, it can be connected to the display through the HDMI socket to display the spliced ​​image signal on the display screen.

[0057] Furthermore, in a feasible embodiment, for each set of HDMI input interface and HDMI input conversion chip, after the HDMI input interface is connected to an external imaging device, the HDMI signal is input to the HDMI input conversion chip through the HDMI input interface, and the HDMI input chip converts the input HDMI signal into an RGB signal, and outputs the RGB signal to the first FPGA or the second FPGA.

[0058] In this embodiment, please refer to Figure 2 and Figure 3 ,like Figure 2 and Figure 3The above is one of the 9 HDMI interfaces. Since the circuits of the 9 interfaces are the same, we select one of them to explain. In the picture, J15 is the HDMI input interface, which can be connected to computers, cameras and all external devices that output image and video signals. J15 has four sets of differential HDMI signal outputs to pins 26-34 of U46, and Y3 supplies its 27MHZ clock. Network R0-R7 is the red primary color signal output pin with a total of 8 bits = 8Bit, network G0-G7 is the green primary color signal output pin with a total of 8 bits = 8Bit, and network B0-B7 is the blue primary color signal output pin with a total of 8 bits = 8Bit. The three channels together form RBG-TTL 24Bit signals. RN41-RN46 are damping resistors, and each resistor outputs 4 TTL signals to FPGA. Pins 9 and 10 of the chip are line field scanning signals, and pin 75 outputs the pixel clock signal PCLK generated by the chip. The main purpose of HDMI to RGB-TTL is to generate a level signal that can be recognized by FPGA.

[0059] Further, in a feasible embodiment, please refer to Figure 4 , the first FPGA receives the RGB signals output by the first to fourth HDMI input conversion chips among the HDMI input conversion chips, and outputs the RGB signals to the third FPGA;

[0060] The second FPGA receives the RGB signals output by the fifth to eighth HDMI input conversion chips among the HDMI input conversion chips, and outputs the RGB signals to the third FPGA;

[0061] The third FPGA receives the RGB signals input by the first FPGA and the second FPGA, receives the RGB signals output by the ninth HDMI input conversion chip among the HDMI input conversion chips, stores the received RGB signals in the first memory, and outputs them to the fourth FPGA;

[0062] The fourth FPGA stores the received RGB signal into the second memory;

[0063] The third FPGA and the fourth FPGA respectively edit and splice the RGB signals stored in the first memory and the second memory in response to the instructions output by the micro control unit to obtain YUV signals, and then output them to the connected HDMI output conversion chips respectively.

[0064] In this embodiment, FPGA1 and FPGA2 receive RGB-TTL 24-bit image signals and arrange them in time sequence. Each of FPGA2 and FPGA1 can receive 4 RGB-TTL signals, and the remaining 9th RGB-TTL is directly transmitted to FPGA3. FPGA1 packages 1-4 image signal data and transmits them to FPGA3 through the high-speed SERDES bus. At the same time, 4-8 RGB-TTL signals received by FPGA2 are also synchronously forwarded to FPGA3 through the high-speed SERDES bus. FPGA3 receives the packaged forwarded signals from ports 1-8 of FPGA1 and FPGA2 and the image signal from port 9 directly connected to FPGA3 and stores them in DDR. 3 memory and synchronously send it to FPGA4 through the high-speed SERDES bus of FPGA3. FPGA4 stores the data of ports 1-9 into DDR3. Therefore, the image signals of all HDMI inputs of ports 1-9 are cached in the DDR3 memory of FPGA3 and FPGA4. MCU configures the image output mode of FPGA3 and FPGA4 through the IIC bus. FPGA3 outputs RGB-TTL images of ports 1-4 and FPGA3 outputs RGB-TTL images of ports 5-9. Therefore, through the editing of FPGA3 and FPGA4, the image input to port 1 can be output at any HDMI interface of output 1-9 controlled by FPGA3 and FPGA4 through the instruction protocol issued by MCU.

[0065] Furthermore, in a feasible embodiment, for each set of HDMI output conversion chip and HDMI output interface, the HDMI output conversion chip converts the received YUV signal into an HDMI signal, and then outputs it to the connected HDMI output interface, and the HDMI output interface outputs the HDMI signal to the connected external display device.

[0066] In this embodiment, FPGA3 and FPGA4 output the spliced ​​image signals as 1-4 and 5-9 RGB-TTL signals respectively, which are received by the conversion chip and converted into HDMI signals and sent to the HDMI interface.

[0067] Further, in a feasible embodiment, please refer to Figure 5 The micro control unit is connected to each of the HDMI input conversion chips, each of the HDMI output conversion chips, the first FPGA, the second FPGA, the third FPGA and the fourth FPGA through a multiplexer or a signal separator chip.

[0068] In this embodiment, all FPGAs and conversion chips receive the IIC bus protocol through the MCU in the flow chart, and the protocol enables the chip to generate execution operations through the instructions of the MCU.

[0069] Further, in a feasible embodiment, please refer to Figure 6 , the integrated circuit also includes: a multi-frequency clock signal chip;

[0070] The multi-frequency clock signal chip is respectively connected to the third FPGA, the fourth FPGA, the first memory and the second memory to ensure synchronous output of the circuit.

[0071] In this embodiment, for a more accurate clock, the output images of all output interfaces are unified, the image output will not drop frames, and the image pixels are more accurately divided by a unified frequency division method to provide a more accurate oscillation clock frequency to FPGA / DDR3.

[0072] Further, in a feasible embodiment, please refer to Figure 7 , the integrated circuit further comprises:

[0073] A power supply step-by-step conversion circuit, used to convert an external 220V voltage into a 12V voltage, then convert the 12V voltage into a 5V voltage, and then convert the 5V voltage into a 3.3V voltage, and use the 3.3V voltage to power the microcontroller unit, the multi-frequency clock signal chip, the first FPGA, the second FPGA, the third FPGA, and the fourth FPGA;

[0074] The 3.3V voltage is converted into 1.5V and 0.75V voltages to power the first memory and the second memory.

[0075] In this embodiment, after the DC12V power supply is input, the BUCK step-down method is used to step down the DC12V to VCC5V, VCC3.3V, and the MCU power supply adopts the LDO method to step down the 5V to 3.3V for powering it. The advantage of using LDO power supply for MCU is that the power supply ripple is small, the interference is small, and the stable operation of MCU can be improved.

[0076] In the technical solution of the utility model, nine HDMI input interfaces and output interfaces are integrated into one integrated circuit, and four FPGAs are used to realize the transmission and editing splicing of image signals, and a conversion chip is used to realize the conversion of signal formats, so that the integrated circuit can process and output multi-channel input HDMI signals at the same time, making maximum use of the resources of the FPGA chip, reducing the number of circuit boards such as input cards, output cards, control cards, and switching boards compared to the traditional splicing matrix, and reducing the cost.

[0077] The utility model also provides an electronic device, the electronic device includes an integrated circuit with nine-port input and nine-port image stitching matrix output, the structure of the integrated circuit with nine-port input and nine-port image stitching matrix output can refer to the above embodiment, and will not be repeated here. As a matter of course, since the electronic device of this embodiment adopts the technical solution of the integrated circuit with nine-port input and nine-port image stitching matrix output, the electronic device has all the beneficial effects of the integrated circuit with nine-port input and nine-port image stitching matrix output.

[0078] In a feasible embodiment, the electronic device further includes a 1U architecture chassis.

[0079] In this embodiment, the 1U architecture chassis refers to a rack-mounted chassis that complies with the 1U size specification and is mainly used in servers, network equipment, and other data center equipment.

[0080] In a feasible embodiment, the electronic device further includes an image server power supply, and the image server power supply supplies power to the integrated circuit.

[0081] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or system including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or system. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or system including the element.

[0082] The serial numbers of the above-mentioned embodiments of the present invention are only for description and do not represent the advantages and disadvantages of the embodiments.

[0083] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the utility model in essence or the part that contributes to the prior art can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) as described above, including a number of instructions for a terminal device (which can be a mobile phone, a computer, a server, or a network device, etc.) to execute the methods described in each embodiment of the utility model.

[0084] The above are only preferred embodiments of the present invention, and are not intended to limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made using the contents of the specification and drawings of the present invention, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. An integrated circuit with nine input ports and nine image splicing matrix output ports, characterized in that: The integrated circuit with nine-port input and nine-port image stitching matrix output includes: Nine HDMI input interfaces for connecting external image devices; Nine HDMI input conversion chips, each of which is connected to each of the HDMI input interfaces in a one-to-one correspondence, and is used to convert an input HDMI signal into an RGB signal; A first FPGA, connected to the first to fourth HDMI input conversion chips among the HDMI input conversion chips, and used for encoding and packaging the received RGB signals into image data; A second FPGA, connected to the fifth to eighth HDMI input conversion chips among the HDMI input conversion chips, and used for encoding and packaging the received RGB signals into image data; Nine HDMI output conversion chips, used to convert received YUV signals into HDMI signals; Nine HDMI output interfaces, each of which is connected to each of the HDMI output conversion chips in a one-to-one correspondence, and is used to connect to an external display device; A third FPGA, connected to the ninth HDMI input conversion chip among the HDMI input conversion chips, connected to the first FPGA and the second FPGA, and also connected to the first to fourth HDMI output conversion chips among the HDMI output interfaces, for packaging the received RGB signal into image data, and splicing the received image data into a YUV signal; A fourth FPGA, connected to the third FPGA and connected to the fifth to ninth HDMI output conversion chips in each of the HDMI output interfaces, for splicing the received image data into a YUV signal; A micro control unit is used to control the connected HDMI input conversion chips, the connected HDMI output conversion chips, the first FPGA, the second FPGA, the third FPGA and the fourth FPGA.

2. The integrated circuit with nine-port input and nine-port image splicing matrix output as claimed in claim 1, characterized in that: For each set of HDMI input interface and HDMI input conversion chip, after the HDMI input interface is connected to an external imaging device, the HDMI signal is input to the HDMI input conversion chip through the HDMI input interface, and the HDMI input chip converts the input HDMI signal into an RGB signal and outputs the RGB signal to the first FPGA or the second FPGA.

3. The integrated circuit with nine-port input and nine-port image splicing matrix output as claimed in claim 2, characterized in that: The first FPGA receives the RGB signals output by the first to fourth HDMI input conversion chips among the HDMI input conversion chips, and outputs the RGB signals to the third FPGA; The second FPGA receives the RGB signals output by the fifth to eighth HDMI input conversion chips among the HDMI input conversion chips, and outputs the RGB signals to the third FPGA; The third FPGA receives the RGB signals input by the first FPGA and the second FPGA, receives the RGB signals output by the ninth HDMI input conversion chip among the HDMI input conversion chips, stores the received RGB signals in the first memory, and outputs them to the fourth FPGA; The fourth FPGA stores the received RGB signal into the second memory; The third FPGA and the fourth FPGA respectively edit and splice the RGB signals stored in the first memory and the second memory in response to the instructions output by the micro control unit to obtain YUV signals, and then output them to the connected HDMI output conversion chips respectively.

4. The integrated circuit with nine-port input and nine-port image splicing matrix output as claimed in claim 3, characterized in that: For each set of HDMI output conversion chip and HDMI output interface, the HDMI output conversion chip converts the received YUV signal into an HDMI signal, and then outputs it to the connected HDMI output interface, and the HDMI output interface outputs the HDMI signal to the connected external display device.

5. The integrated circuit with nine-port input and nine-port image splicing matrix output as claimed in claim 4, characterized in that: The micro control unit is connected to each of the HDMI input conversion chips, each of the HDMI output conversion chips, the first FPGA, the second FPGA, the third FPGA and the fourth FPGA respectively through a multiplexer or a signal separator chip.

6. The integrated circuit with nine-port input and nine-port image splicing matrix output as claimed in claim 5, characterized in that: The integrated circuit also includes: a multi-frequency clock signal chip; The multi-frequency clock signal chip is respectively connected to the third FPGA, the fourth FPGA, the first memory and the second memory to ensure synchronous output of the circuit.

7. The integrated circuit with nine-port input and nine-port image splicing matrix output as claimed in claim 6, characterized in that: The integrated circuit further comprises: A power supply step-by-step conversion circuit, used to convert an external 220V voltage into a 12V voltage, then convert the 12V voltage into a 5V voltage, and then convert the 5V voltage into a 3.3V voltage, and use the 3.3V voltage to power the microcontroller unit, the multi-frequency clock signal chip, the first FPGA, the second FPGA, the third FPGA, and the fourth FPGA; The 3.3V voltage is converted into 1.5V and 0.75V voltages to power the first memory and the second memory.

8. An electronic device, characterized in that: The electronic device comprises an integrated circuit with nine-port input and nine-port image stitching matrix output as claimed in any one of claims 1 to 7.

9. The electronic device according to claim 8, characterized in that: The electronic device also includes a 1U architecture chassis.

10. The electronic device according to claim 9, characterized in that: The electronic device further comprises an image server power supply, which supplies power to the integrated circuit.

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