Test circuit for testing chip

Abstract

The utility model relates to a test circuit of a test chip, which comprises a circuit board and a test machine, the circuit board is connected with a chip to be tested, the power supply output end of the chip to be tested is connected with the power supply input end of the test machine, and the DDR3 output end of the chip to be tested is connected with the digital test input end of the test machine. The BOOT output end of the chip to be tested is connected with the digital test input end of the test machine, the SPI output end of the chip to be tested is connected with the digital test input end of the test machine, the HDMI output end of the chip to be tested is connected with the digital test input end of the test machine, and the HDMI output end of the chip to be tested is connected with the high-speed digital test input end of the test machine. The HPOUT output end of the chip to be tested is connected with the digital test input end of the test machine through the first relay, and the APamp of the chip to be tested is connected with the HPOUT output end of the chip to be tested; the output end of the EDP is connected with the digital test input end of the test machine; the output end of the EDP is connected with the APamp of the chip to be tested through the loop module; the input end of the EDP is connected. According to the utility model, the test efficiency can be improved.

Description

Technical Field

[0001] The utility model relates to a test circuit for testing a chip. Background Art

[0002] Integrated Circuit (IC) is small in size and powerful in function. It is one of the indispensable electronic components of information equipment. In order to ensure the normal function of the chip, the chip must undergo rigorous testing before leaving the factory. The general testing method is to input a known test signal into the circuit in the chip, and then obtain the feedback signal of the chip circuit to determine whether the chip function is normal.

[0003] After searching, the patent: Chip test circuit (CN201010267091.7) is a chip test circuit that uses a judgment circuit to switch the interface circuit between the input and output units of different compression groups, so that a single interface circuit can be used to obtain multiple sets of compressed test data, effectively improving the test output speed. The above test function is not enough and cannot meet the test requirements of this application.

[0004] In view of the above-mentioned defects, the designers have actively carried out research and innovation in order to create a test circuit for a test chip with a new structure to make it more valuable for industrial use. Utility Model Content

[0005] In order to solve the above technical problems, the purpose of the utility model is to provide a test circuit for testing a chip.

[0006] In order to achieve the above purpose, the utility model adopts the following technical solutions:

[0007] A test circuit for testing a chip comprises a circuit board and a test machine, wherein the circuit board is connected with a chip to be tested, a power output end of the chip to be tested is connected to a power input end of the test machine, a DDR3 output end of the chip to be tested is connected to a digital test input end of the test machine, a BOOT output end of the chip to be tested is connected to a digital test input end of the test machine, an SPI output end of the chip to be tested is connected to a digital test input end of the test machine, an HDMI output end of the chip to be tested is connected to a digital test input end of the test machine, an HDMI output end of the chip to be tested is connected to a high-speed digital test input end of the test machine, an HPOUT output end of the chip to be tested is connected to an input end of a first relay, an output end of the first relay is connected to a digital test input end of the test machine, an AP&EDP output end of the chip to be tested is connected to a digital test input end of the test machine, and the AP&EDP output end of the chip to be tested is connected to the AP&EDP input end of the chip to be tested via a loop module.

[0008] Preferably, in the test circuit for testing a chip, the first relay is connected to an external tester.

[0009] Preferably, in the test circuit for testing a chip, the GND output terminal of the chip to be tested is connected to the GND input terminal of a tester.

[0010] Preferably, in the test circuit of the test chip, the loop module is a capacitive loop.

[0011] Preferably, in the test circuit for testing a chip, the DDR3 output terminal of the chip to be tested is connected to the tester via a second relay.

[0012] By means of the above solution, the utility model has at least the following advantages:

[0013] The utility model can realize the testing of different functions of the chip to be tested, and effectively improve the working efficiency of the test.

[0014] The above description is only an overview of the technical solution of the utility model. In order to more clearly understand the technical means of the utility model and implement it according to the contents of the specification, the following is a detailed description of the preferred embodiments of the utility model in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions of the embodiments of the utility model, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the utility model and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without paying creative work.

[0016] Figure 1 It is a principle block diagram of the utility model;

[0017] Figure 2 It is a DP&EDP test circuit diagram of the chip to be tested of the utility model;

[0018] Figure 3 It is the HPOUT test circuit diagram of the chip to be tested of the utility model;

[0019] Figure 4 It is a DDR3 test circuit diagram of the chip to be tested of the utility model;

[0020] Figure 5 It is a BOOT test circuit diagram of the chip to be tested of the utility model;

[0021] Figure 6 It is the SPI test circuit diagram of the chip to be tested of the utility model;

[0022] Figure 7 It is a HDMI test circuit diagram of the chip to be tested of the utility model;

[0023] Figure 8 It is a HDMI high-speed test circuit diagram of the chip to be tested of the utility model;

[0024] Fig. 9 This is a GND test circuit diagram of the chip to be tested of the utility model;

[0025] Fig.10 The utility model discloses a power supply test circuit diagram of a chip to be tested. DETAILED DESCRIPTION

[0026] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.

[0027] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for which protection is sought, but merely represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0028] Example

[0029] like Figures 1 to 10 As shown, a test circuit for testing a chip includes a circuit board 1 and a test machine 2, wherein a chip to be tested 3 is connected to the circuit board 1, a power output end of the chip to be tested 3 is connected to a power input end of the test machine 2, a DDR3 output end of the chip to be tested 3 is connected to a digital test input end of the test machine 2, a BOOT output end of the chip to be tested 3 is connected to a digital test input end of the test machine 2, an SPI output end of the chip to be tested 3 is connected to a digital test input end of the test machine 2, an HDMI output end of the chip to be tested 3 is connected to a digital test input end of the test machine 2, an HDMI output end of the chip to be tested 3 is connected to a high-speed digital test input end of the test machine 2, an HPOUT output end of the chip to be tested 3 is connected to an input end of a first relay 4, an output end of the first relay 4 is connected to a digital test input end of the test machine 2, an AP&EDP output end of the chip to be tested 3 is connected to a digital test input end of the test machine 2, and an AP&EDP output end of the chip to be tested 3 is connected to an AP&EDP input end of the chip to be tested 3 through a loop module 5.

[0030] In the present invention, the first relay 4 is connected to an external tester.

[0031] The GND output terminal of the chip to be tested 3 in the present invention is connected to the GND input terminal of the tester 2 .

[0032] The loop module 5 in the present invention is a capacitor loop.

[0033] The DDR3 output terminal of the chip to be tested 3 in the utility model is connected to the test machine through the second relay.

[0034] The working principle of the utility model is as follows:

[0035] During specific operation, different functional units on the chip to be tested are connected to the test units of the test machine through corresponding circuits, and the different units of the chip to be tested are tested by the test machine.

[0036] The testing method in the testing machine of the utility model is the prior art known to those skilled in the art, and has been disclosed in the patent: Chip Testing Circuit (CN201010267091.7), and no further description will be made.

[0037] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0038] In the description of this application, it should be noted that the terms "vertical", "horizontal", "inside", "outside", etc. indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, or the positions or positional relationships in which the product of the application is usually placed when in use. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on this application. In addition, the terms "first", "second", etc. are only used to distinguish the description, and cannot be understood as indicating or implying relative importance.

[0039] In addition, the terms "horizontal", "vertical" and the like do not mean that the components are required to be absolutely horizontal or vertical, but can be slightly tilted. For example, "horizontal" only means that its direction is more horizontal than "vertical", and does not mean that the structure must be completely horizontal, but can be slightly tilted.

[0040] In the description of this application, it should also be noted that, unless otherwise clearly specified and limited, the terms "set", "install", "connect", and "connect" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0041] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. It should be pointed out that a person skilled in the art can make several improvements and modifications without departing from the technical principle of the present invention, and these improvements and modifications should also be regarded as within the protection scope of the present invention.

Claims

1. A test circuit for testing a chip, comprising a circuit board (1) and a test machine (2), wherein a chip to be tested (3) is connected to the circuit board (1), and characterized in that: The power output end of the chip under test (3) is connected to the power input end of the test machine (2); the DDR3 output end of the chip under test (3) is connected to the digital test input end of the test machine (2); the BOOT output end of the chip under test (3) is connected to the digital test input end of the test machine (2); the SPI output end of the chip under test (3) is connected to the digital test input end of the test machine (2); the HDMI output end of the chip under test (3) is connected to the digital test input end of the test machine (2); the HDMI output end of the chip under test (3) is connected to the high-speed digital test input end of the test machine (2); the HPOUT output end of the chip under test (3) is connected to the input end of the first relay (4); the output end of the first relay (4) is connected to the digital test input end of the test machine (2); the AP&EDP output end of the chip under test (3) is connected to the digital test input end of the test machine (2); and the AP&EDP output end of the chip under test (3) is connected to the AP&EDP input end of the chip under test (3) through a loop module (5).

2. The test circuit of a test chip according to claim 1, characterized in that: The first relay (4) is connected to an external tester.

3. The test circuit of a test chip according to claim 1, characterized in that: The GND output terminal of the chip to be tested (3) is connected to the GND input terminal of the test machine (2).

4. The test circuit of a test chip according to claim 1, characterized in that: The loop module (5) is a capacitive loop.

5. The test circuit of a test chip according to claim 1, characterized in that: The DDR3 output terminal of the chip to be tested (3) is connected to the test machine via a second relay.

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