Industrial control bus conversion IO control device

Abstract

The utility model discloses an industrial control bus conversion IO control device, comprising a control logic circuit used for receiving and sending a contact signal between a CPU and IO equipment through a PXI interface; the device selection circuit performs addressing according to an address signal sent by the CPU; the command register stores a control command sent by the CPU; the command decoder is used for identifying the control command and controlling the IO equipment to perform corresponding operation; the data buffer is used for storing data needing to be transmitted; the serial-parallel conversion circuit realizes data format conversion; the level matching logic realizes level conversion; the A / D conversion module performs analog-to-digital conversion; the D / A conversion module performs digital-to-analog conversion; and the digital I / O module completes interaction with the bus. The digital and analog signal processor supports various IO interfaces and protocols, realizes integration and control of various digital and analog signals, and can process AI, AO, DI and DO signals. And bus signals including Modbus, CAN, EtherCAT and the like can be received, multiple functions can be realized, and the applicability of the IO module is improved.

Description

Technical Field

[0001] The utility model relates to the technical field of data acquisition and control, in particular to an industrial control bus conversion IO control device. Background Art

[0002] The industrial control bus conversion I0 control module connects the PLC with external decentralized signals (such as buttons, contactors, actuators, etc.). It is mainly used for data input and output operation and control signal transmission between the PLC and external devices. It usually has lower bandwidth and speed requirements because the data transmission speed of external devices is relatively slow, and there are many types and interfaces of external devices, which need to support different standards and protocols. In the prior art, different IO module communication protocols are not unified and the module functions are single. Utility Model Content

[0003] The utility model aims to provide an industrial control bus conversion IO control device, which is used to solve the problems of different IO module communication protocols not being unified and the module functions being single in the prior art.

[0004] The utility model solves the above problems through the following technical solutions:

[0005] An industrial control bus conversion IO control device, comprising:

[0006] The control logic circuit is used to receive and send communication signals between the CPU and the IO device through the PXI interface to realize communication control; the communication signals include address signals, control commands and data; and is used to realize communication control between the CPU and the multi-protocol interface circuit, and between the multi-protocol interface circuit and the IO device;

[0007] The device selection circuit is used to receive and identify the address signal sent by the CPU and send a selection signal SEL to the command register;

[0008] A command register, used to store control commands sent by the CPU under the control of a selection signal SEL;

[0009] The command decoder is used to identify the control commands stored in the command register and control the IO device to perform corresponding operations;

[0010] A data buffer for storing data to be transmitted;

[0011] A serial-to-parallel conversion circuit is connected to the data buffer and is used to realize data format conversion between the CPU and the IO device;

[0012] Level matching logic, connected to the data buffer, is used to achieve level conversion between the CPU and the IO device;

[0013] A / D conversion module, used for receiving analog input and performing analog-to-digital conversion, and inputting into a data buffer;

[0014] A D / A conversion module is used to convert the digital signal to be output from the data buffer into an analog signal and output it to the IO device;

[0015] The digital I / O module is connected to the data buffer and is used to input and output digital signals to complete the interaction with the bus;

[0016] The multi-protocol interface circuit includes a CAN bus interface, an Ethernet interface and a protocol stack for realizing protocol conversion, wherein the CAN bus interface is used to realize CAN bus communication, the Ethernet interface is used to realize Ethernet communication, and the protocol stack is used to realize the conversion of one protocol data to another protocol data, and realize the conversion logic between protocols.

[0017] The utility model can convert analog signals into digital signals, and transmit them to the upper controller, i.e., CPU, at high speed through bus protocol, so as to realize real-time data processing and transmission of control signals. Through data buffer, speed matching between CPU and IO device is realized; serial-parallel conversion circuit is realized to realize data format conversion between CPU and IO device; level matching logic is realized to realize electrical conversion between CPU and IO device; control commands of CPU are received and transmitted to realize operation control of IO device by CPU; status of IO device is saved and transmitted to realize status query of IO device by CPU; device selection circuit identifies the address sent by CPU, and sends selection signal SEL when matching, so as to complete IO addressing function; command register receives and saves control commands sent by CPU under control of SEL signal; command decoder identifies commands to control IO device to perform corresponding operation; data buffer DBR stores data to be transmitted, so as to alleviate speed mismatch problem between CPU and IO device; device status mark stores current operation status of IO device; control logic circuit is responsible for receiving and sending corresponding communication signals between CPU and IO device, so as to realize communication control between CPU and interface, and between interface and device.

[0018] By designing a multi-protocol interface circuit, including: CAN bus interface, using the practical MCP2515 CAN controller and MCP2551 CAN transceiver to realize CAN bus communication; Ethernet interface, using the W5500 Ethernet controller to realize Ethernet communication. And for each supported protocol, a corresponding protocol stack is implemented, Modbus RTU, CANOpen, TCP / IP (for Ethernet), and the conversion logic between protocol stacks is implemented to convert the data frame of one protocol into the data frame of another protocol. Through this hardware design, the utility model unifies the communication protocol of the IO control device and solves the problem of inconsistent communication protocols.

[0019] Furthermore, the data buffer also includes a device status marking circuit for storing the current operating status of the IO device.

[0020] Furthermore, the A / D conversion module is connected to multiple input channels, and the D / A conversion module is connected to multiple output channels.

[0021] Furthermore, the A / D conversion module is connected to 32 input channels, and the D / A conversion module is connected to 32 output channels.

[0022] Furthermore, isolation circuits are respectively provided between the A / D conversion module and the D / A conversion module and the data buffer.

[0023] Furthermore, the isolation circuit uses an optical coupler TLP 2367.

[0024] Furthermore, the PXI interface is implemented by combining FPGA with a PCI bridge chip PCI 9054.

[0025] Furthermore, the data buffer is DDR2 SDRAM.

[0026] Compared with the prior art, the utility model has the following advantages and beneficial effects:

[0027] (1) The utility model supports multiple IO interfaces and protocols, realizes the integration and control of various digital and analog signals, and can process AI, AO, DI, and DO signals. It can also receive bus signals including Modbus, CAN, EtherCAT, etc., can achieve multi-functions, and improve the applicability of IO modules.

[0028] (2) The utility model unifies the communication protocol of IO control devices and can be used to monitor and control parameters such as temperature, pressure, flow and liquid level. It can acquire sensor data and interact with the control system to achieve precise process control and optimization.

[0029] (3) The utility model supports multiple signal types such as AI, AO, DI, and DO. These four signal types support the HART protocol, and the signal cycle is 100ms. The utility model can also receive bus signals including Modbus, CAN, EtherCAT, etc., thereby improving the applicability of the field multi-functional IO module. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 This is a principle block diagram of the utility model. DETAILED DESCRIPTION

[0031] The present invention is further described in detail below in conjunction with the embodiments, but the implementation manner of the present invention is not limited thereto.

[0032] Example:

[0033] Combined with Figure 1 As shown, an industrial control bus conversion IO control device includes:

[0034] Control logic circuit, used for receiving and sending communication signals between CPU and IO devices through PXI interface to realize communication control; the communication signals include address signals, control commands and data; and for realizing communication control between CPU and multi-protocol interface circuit, and between multi-protocol interface circuit and IO devices;

[0035] The device selection circuit is used to receive and identify the address signal sent by the CPU and send a selection signal SEL to the command register;

[0036] A command register, used to store control commands sent by the CPU under the control of a selection signal SEL;

[0037] The command decoder is used to identify the control commands stored in the command register and control the IO device to perform corresponding operations;

[0038] A data buffer for storing data to be transmitted;

[0039] A serial-to-parallel conversion circuit is connected to the data buffer and is used to realize data format conversion between the CPU and the IO device;

[0040] Level matching logic, connected to the data buffer, is used to achieve level conversion between the CPU and the IO device;

[0041] A / D conversion module, used for receiving analog input and performing analog-to-digital conversion, and inputting into a data buffer;

[0042] A D / A conversion module is used to convert the digital signal to be output from the data buffer into an analog signal and output it to the IO device;

[0043] The digital I / O module is connected to the data buffer and is used to input and output digital signals to complete the interaction with the bus;

[0044] The multi-protocol interface circuit includes a CAN bus interface, an Ethernet interface and a protocol stack for realizing protocol conversion, wherein the CAN bus interface is used to realize CAN bus communication, the Ethernet interface is used to realize Ethernet communication, and the protocol stack is used to realize the conversion of one protocol data to another protocol data, and realize the conversion logic between protocols.

[0045] The utility model can convert analog signals into digital signals, and transmit them to the upper controller, i.e., CPU, at high speed through bus protocol, so as to realize real-time data processing and transmission of control signals. Through data buffer, speed matching between CPU and IO device is realized; serial-parallel conversion circuit is realized to realize data format conversion between CPU and IO device; level matching logic is realized to realize electrical conversion between CPU and IO device; control commands of CPU are received and transmitted to realize operation control of IO device by CPU; status of IO device is saved and transmitted to realize status query of IO device by CPU; device selection circuit identifies the address sent by CPU, and sends selection signal SEL when matching, so as to complete IO addressing function; command register receives and saves control commands sent by CPU under control of SEL signal; command decoder identifies commands to control IO device to perform corresponding operation; data buffer DBR stores data to be transmitted, so as to alleviate speed mismatch problem between CPU and IO device; device status mark stores current operation status of IO device; control logic circuit is responsible for receiving and sending corresponding communication signals between CPU and IO device, so as to realize communication control between CPU and interface, and between interface and device.

[0046] By designing a multi-protocol interface circuit, including: CAN bus interface, using the practical MCP2515 CAN controller and MCP2551 CAN transceiver to realize CAN bus communication; Ethernet interface, using the W5500 Ethernet controller to realize Ethernet communication. And for each supported protocol, a corresponding protocol stack is implemented, Modbus RTU, CANOpen, TCP / IP (for Ethernet), and the conversion logic between protocol stacks is implemented to convert the data frame of one protocol into the data frame of another protocol. Through this hardware design, the utility model unifies the communication protocol of the IO control device and solves the problem of inconsistent communication protocols.

[0047] Furthermore, the data buffer also includes a device status marking circuit for storing the current operating status of the IO device.

[0048] Furthermore, the A / D conversion module is connected to multiple input channels, and the D / A conversion module is connected to multiple output channels.

[0049] Furthermore, the A / D conversion module is connected to 32 input channels, and the D / A conversion module is connected to 32 output channels.

[0050] Furthermore, isolation circuits are respectively provided between the A / D conversion module and the D / A conversion module and the data buffer.

[0051] Furthermore, the isolation circuit uses an optical coupler TLP 2367.

[0052] Furthermore, the PXI interface is implemented by combining FPGA with a PCI bridge chip PCI 9054.

[0053] Furthermore, the data buffer is DDR2 SDRAM.

[0054] Although the present invention is described herein with reference to the illustrative embodiments of the present invention, the above embodiments are merely preferred embodiments of the present invention, and the embodiments of the present invention are not limited to the above embodiments. It should be understood that those skilled in the art can design many other modifications and implementations, which will fall within the scope and spirit of the principles disclosed in this application.

Claims

1. An industrial control bus conversion IO control device, characterized in that: include: Control logic circuit, used for receiving and sending communication signals between CPU and IO devices through PXI interface to realize communication control; the communication signals include address signals, control commands and data; and for realizing communication control between CPU and multi-protocol interface circuit, and between multi-protocol interface circuit and IO devices; The device selection circuit is used to receive and identify the address signal sent by the CPU and send a selection signal SEL to the command register; A command register, used to store control commands sent by the CPU under the control of a selection signal SEL; The command decoder is used to identify the control commands stored in the command register and control the IO device to perform corresponding operations; A data buffer for storing data to be transmitted; A serial-to-parallel conversion circuit is connected to the data buffer and is used to realize data format conversion between the CPU and the IO device; Level matching logic, connected to the data buffer, is used to achieve level conversion between the CPU and the IO device; A / D conversion module, used for receiving analog input and performing analog-to-digital conversion, and inputting into a data buffer; A D / A conversion module is used to convert the digital signal to be output from the data buffer into an analog signal and output it to the IO device; The digital I / O module is connected to the data buffer and is used to input and output digital signals to complete the interaction with the bus; The multi-protocol interface circuit includes a CAN bus interface, an Ethernet interface and a protocol stack for realizing protocol conversion, wherein the CAN bus interface is used to realize CAN bus communication, the Ethernet interface is used to realize Ethernet communication, and the protocol stack is used to realize the conversion of one protocol data to another protocol data, and realize the conversion logic between protocols.

2. The industrial control bus conversion IO control device according to claim 1, characterized in that: The data buffer also includes a device status marking circuit for storing the current operating status of the IO device.

3. The industrial control bus conversion IO control device according to claim 1, characterized in that: The A / D conversion module is connected to multiple input channels, and the D / A conversion module is connected to multiple output channels.

4. The industrial control bus conversion IO control device according to claim 3, characterized in that: The A / D conversion module is connected to 32 input channels, and the D / A conversion module is connected to 32 output channels.

5. The industrial control bus conversion IO control device according to claim 3, characterized in that: Isolation circuits are respectively arranged between the A / D conversion module and the D / A conversion module and the data buffer.

6. The industrial control bus conversion IO control device according to claim 5, characterized in that: The isolation circuit uses an optical coupler TLP 2367.

7. The industrial control bus conversion IO control device according to claim 1, characterized in that: The PXI interface is implemented by combining FPGA with PCI bridge chip PCI 9054.

8. The industrial control bus conversion IO control device according to claim 1, characterized in that: The data buffer is DDR2 SDRAM.

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