High-cleanliness vacuum plasma wafer activation equipment
By designing a vacuum plasma wafer activation equipment with high cleanliness, the plasma input structure and plasma corrosion-resistant coating are used to solve the problem of contaminants on the wafer surface, and wafer activation and organic residue cleaning are achieved, ensuring process stability and high cleanliness.
Patent Information
- Application Number
- CN202421783277.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-07-26
- Publication Date
- 2025-05-06
- Estimated Expiration
- 2034-07-26
AI Technical Summary
In semiconductor processes, the control requirements for wafer surface pollutants are extremely high during wafer-level stacking. The existing plasma activation process is difficult to effectively control the pollution of particles and metal elements, affecting the quality of the chip.
A high-cleanness vacuum plasma wafer activation device is designed. By setting an upper electrode and a lower electrode on the main body of the process chamber, and a hollow area and through holes are provided on the upper electrode to form a plasma input structure. Combining a plasma corrosion-resistant coating and a high-density coating, the bombardment of the plasma on the chamber wall is controlled to avoid contamination.
The surface activation and organic residue cleaning of single wafers are effectively realized, the surface contaminants of wafers are strictly controlled, and the stability and cleanliness of the overall process are ensured.
Smart Images

Figure CN222838788U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to a surface treatment technology, in particular to a surface treatment device, specifically a high-cleanliness vacuum plasma wafer activation device. Background Art
[0002] With the continuous advancement of new infrastructure construction such as 5G and artificial intelligence, the improvement of system functions and performance brought about by simply reducing process size and increasing single chip area can no longer meet the needs of future development. Multi-layer stacking technology, as an advanced integration technology that can break through the limitations of single-layer chips, has become one of the important alternative solutions to achieve system performance, bandwidth, power consumption and other indicators.
[0003] With the continuous advancement of semiconductor technology, wafer size is getting larger and larger, and the chip manufacturing process is becoming more and more complicated. Wafer-level stacking (wafer-level bonding) technology can bond multiple wafers together to complete the manufacturing of multiple chips at one time, greatly improving production efficiency. The development of this technology has brought new possibilities to the semiconductor industry. For example, it can realize the manufacture of three-dimensional integrated circuits (3D ICs), further improving the integration and performance of chips.
[0004] Plasma activation is an important process in wafer-level stacking. Before wafer bonding, plasma treatment can improve the surface energy of the wafer, remove microscopic organic pollutants, improve surface roughness, etc., to increase the bonding strength of the van der Waals force. Wafer-level stacking has extremely high requirements for the control of pollutants on the wafer surface. The contamination of particles and metal elements will directly affect the performance of the wafer after bonding and determine whether the produced chips are qualified. Therefore, there are also extremely high requirements for the contamination of particles and metal elements in the plasma treatment process.
[0005] Therefore, it is necessary to provide a high-cleanliness vacuum plasma wafer activation device to solve the above problems. Utility Model Content
[0006] The utility model aims to provide a high-cleanliness vacuum plasma wafer activation device, which can effectively control the pollutants on the wafer surface to ensure the overall process stability while realizing the activation of the single wafer surface and the cleaning of organic residues.
[0007] The utility model achieves the above-mentioned purpose through the following technical solutions:
[0008] A high-cleanliness vacuum plasma wafer activation device comprises a process chamber body, wherein an upper electrode and a lower electrode corresponding to each other and used in combination are arranged inside the process chamber body, a process air inlet is provided on the process chamber body corresponding to the upper electrode, a wafer ejector pin assembly is provided corresponding to the lower electrode, a sedimentation groove corresponding to the size of the wafer is provided on the contact surface between the lower electrode and the wafer, and the wafer ejector pin assembly descends and the wafer falls into the sedimentation groove of the lower electrode;
[0009] A hollow area is provided on the upper surface of the upper electrode to form a process gas buffer area with the main body of the process chamber. The main body of the upper electrode is provided with a number of through holes. After the process gas enters the process gas buffer area, it enters the main body of the process chamber through the through holes. The through holes are irregularly distributed to achieve uniformity of air intake and exhaust, thereby forming a high-concentration, low-damage plasma input structure.
[0010] Furthermore, the process chamber body includes a cavity body and an upper cover plate, and the upper cover plate is connected to the cavity body through a hinge with a limiting function to achieve opening and closing for installation and maintenance.
[0011] Furthermore, a chamber compression seal is provided at the connection between the upper cover plate and the cavity body.
[0012] Furthermore, a vacuum port is provided below the process chamber body.
[0013] Furthermore, the interior of the cavity body and the upper cover plate are provided with a plasma corrosion resistant coating, which is a high-density coating obtained by oxidation, PVD processing or spraying processing.
[0014] Furthermore, the surfaces of the upper electrode and the lower electrode are also provided with coatings.
[0015] Furthermore, an upper electrode plasma power input connection module may be provided corresponding to the upper electrode, and a lower electrode plasma power input connection module may be provided corresponding to the lower electrode.
[0016] Furthermore, a wafer transfer port and an observation window are provided on the process chamber body.
[0017] Furthermore, the lower electrode is mounted on a lower electrode mounting plate, which is made of insulating material, and the lower electrode mounting plate is fixed in the process chamber body through a lower electrode supporting column.
[0018] Furthermore, the upper electrode is mounted on an upper electrode mounting plate, the upper electrode mounting plate is made of insulating material, and the upper electrode mounting plate is fixed to the upper cover plate.
[0019] Compared with the existing methods, the utility model can effectively control the pollutants on the surface of the wafer to ensure the overall process stability while realizing the activation of the surface of the single wafer and the cleaning of organic residues. BRIEF DESCRIPTION OF THE DRAWINGS
[0020] Figure 1 It is one of the isometric test diagrams of the utility model.
[0021] Figure 2 This is the second isometric test diagram of the present utility model.
[0022] Figure 3 It is a cross-sectional view of the utility model.
[0023] Figure 4 yes Figure 3 A partial enlarged view of . DETAILED DESCRIPTION
[0024] Example:
[0025] See also Figure 1-4 This embodiment shows a high-cleanliness vacuum plasma wafer activation device, including: a process chamber body 1, wherein the process chamber body 1 is provided with an upper electrode 2 and a lower electrode 3 corresponding to and used in conjunction with each other, wherein a process air inlet 4 is provided on the process chamber body 1 corresponding to the upper electrode 3, and a wafer ejector pin assembly 5 is provided corresponding to the lower electrode, and a sedimentation groove corresponding to the size of the wafer is provided on the contact surface between the lower electrode 3 and the wafer, and the wafer ejector pin assembly 5 descends, and the wafer falls into the sedimentation groove of the lower electrode 3;
[0026] A hollow area is provided on the upper surface of the upper electrode 2 to form a process gas buffer area 200 with the process chamber body 1. The body of the upper electrode 2 is provided with a plurality of through holes 20. After the process gas enters the process gas buffer area 200, it enters the interior of the process chamber body 1 through the through holes 20 on the upper electrode 2. The through holes 20 of the upper electrode 2 are irregularly distributed to achieve uniformity of air intake and exhaust, thereby forming a high-concentration, low-damage plasma input structure.
[0027] in:
[0028] The process chamber body 1 comprises a chamber body 11 and an upper cover plate 12. The upper cover plate 12 is connected to the chamber body 11 via a hinge 13 with a limiting function to achieve opening and closing for installation and maintenance.
[0029] A chamber compression seal 14 is provided at the connection between the upper cover plate 12 and the chamber body 11 .
[0030] A vacuum port 15 is also provided below the process chamber body 1 .
[0031] The interior of the cavity body 11 and the upper cover plate 12 are both provided with a plasma corrosion resistant coating, which is a high-density coating obtained by oxidation, PVD processing or spraying processing.
[0032] The processing technology and coating material are selected according to the actual process requirements of the user, and a double coating method is used to ensure that no metal elements and particle pollution will be generated due to plasma bombardment during use.
[0033] The upper electrode 2 and the lower electrode 3 are also provided with coatings on their surfaces.
[0034] The coating effectively controls the bombardment of the plasma on the chamber wall to avoid the generation of particles and metal element pollution. At the same time, the coating can constrain the plasma to ensure the stability and consistency of the process.
[0035] The required process gas is introduced into the process gas inlet 4, and the introduced gas must be a high-purity gas.
[0036] The upper electrode 2 may be provided with an upper electrode plasma power input connection module 21 correspondingly. The upper electrode plasma power input connection structure includes a conductive column, an insulating column, a screen box and a radio frequency connection connector to realize the input of plasma power to the upper electrode.
[0037] The lower electrode 3 may be provided with a lower electrode plasma power input connection module 31 correspondingly to input the plasma power to the lower electrode.
[0038] A wafer transfer port 6 and an observation window 7 are provided on the process chamber body 1 .
[0039] The observation window 7 is used to observe the internal state of the chamber; the wafer transfer port 6 is used for a high vacuum gate valve.
[0040] The wafer ejector pin assembly 5 is used to realize the lifting and lowering of the wafer. When the wafer is taken in and out, the high vacuum gate valve is opened, the wafer ejector pin is raised, and the wafer is placed on or taken out of the ejector pin in cooperation with the robot or vacuum suction pen. After the wafer transfer is completed, the high vacuum gate valve is closed, and the wafer ejector pin assembly 5 falls.
[0041] When placing a wafer, the wafer ejector pin assembly 5 drops the wafer to the lower electrode 3 ; when taking a wafer, the wafer ejector pin assembly 5 rises to lift the wafer from the lower electrode 3 .
[0042] The settling trough can constrain the wafer on the lower electrode to prevent displacement and misalignment of the wafer.
[0043] The lower electrode 3 is mounted on a lower electrode mounting plate 32 . The lower electrode mounting plate 32 is made of insulating material. The lower electrode mounting plate 32 is fixed in the process chamber body 1 through a lower electrode supporting column 33 .
[0044] The upper electrode 2 is mounted on an upper electrode mounting plate 22, and the upper electrode mounting plate 22 is made of insulating material. The upper electrode mounting plate 21 is fixed to the upper cover plate.
[0045] In order to ensure the cleanliness of the process chamber body 1, all components must be cleaned with high cleanliness before installation to prevent them from bringing in pollutants.
[0046] Assembly must be carried out in a highly clean space environment; assemblers must strictly follow operating standards to assemble each component to avoid the generation of pollutants during the installation process.
[0047] The process chamber body 1 is connected to the chamber mounting plate 8, and the chamber mounting plate 8 has height fine-tuning and leveling functions.
[0048] The upper electrode 2 and the lower electrode 3 are connected to at least one plasma power supply, and the other electrode can be grounded or connected to a second plasma power supply to ensure that a plasma electric field is formed between the two electrodes.
[0049] The connected plasma power source may be a high frequency power source or a low frequency power source, and if a radio frequency power source is connected, it is not limited to the commonly used 13.56 MHz radio frequency power source.
[0050] In a specific implementation, after the upper electrode 2 is connected to the plasma power supply, the lower electrode 3 can be grounded or connected to a second plasma power supply, which can usually be a low-frequency power supply or a radio frequency power supply. Similarly, after the lower electrode is connected to the plasma power supply, the upper electrode can be connected to the second plasma power supply, which can usually be a low-frequency power supply or a radio frequency power supply.
[0051] Similarly, the upper electrode and the lower electrode can also be connected to plasma power supplies of various frequencies according to process requirements.
[0052] This equipment also includes process air intake components, plasma power supply, electrical control part, vacuum control part, whole machine frame structure and other components.
[0053] It is worth noting that:
[0054] 1) In addition to wafer stacking, this embodiment can also be applied to other high-cleanliness surface treatments in the wafer manufacturing process, such as photolithography machine coating pre-treatment, metallization pre-treatment, silicon nitride coating pre-treatment, and chip bonding pre-treatment.
[0055] 2) This embodiment is a single-size wafer processing structure, which can be applied to the surface processing of 4-inch to 12-inch wafers. At the same time, through structural adjustment, high-cleanliness processing of products of other shapes can be achieved.
[0056] This equipment is usually a single-size wafer processing structure and can be used for surface processing of 4-inch to 12-inch wafers. At the same time, through structural adjustment, high-cleanliness processing of products of other shapes can be achieved.
[0057] Compared with the existing methods, the utility model can effectively control the pollutants on the surface of the wafer to ensure the overall process stability while realizing the activation of the surface of the single wafer and the cleaning of organic residues.
[0058] The above are only some embodiments of the present invention. For those skilled in the art, several modifications and improvements can be made without departing from the inventive concept of the present invention, which all belong to the protection scope of the present invention.
Claims
1. A high cleanliness vacuum plasma wafer activation device, characterized in that: It includes a process chamber body, wherein an upper electrode and a lower electrode corresponding to each other and used in conjunction with each other are arranged inside the process chamber body, a process air inlet is opened on the process chamber body corresponding to the upper electrode, a wafer ejector assembly is arranged corresponding to the lower electrode, and a sedimentation groove corresponding to the size of the wafer is arranged on the contact surface between the lower electrode and the wafer, and the wafer ejector assembly descends, and the wafer falls into the sedimentation groove of the lower electrode; A hollow area is provided on the upper surface of the upper electrode to form a process gas buffer area with the main body of the process chamber. The main body of the upper electrode is provided with a number of through holes. After the process gas enters the process gas buffer area, it enters the main body of the process chamber through the through holes. The through holes are irregularly distributed to achieve uniformity of air intake and exhaust, thereby forming a high-concentration, low-damage plasma input structure.
2. The high cleanliness vacuum plasma wafer activation equipment according to claim 1, characterized in that: The process chamber body includes a cavity body and an upper cover plate. The upper cover plate is connected to the cavity body through a hinge with a limit function to achieve opening and closing for installation and maintenance.
3. The high cleanliness vacuum plasma wafer activation equipment according to claim 2, characterized in that: A chamber compression seal is provided at the connection between the upper cover plate and the chamber body.
4. The high cleanliness vacuum plasma wafer activation equipment according to claim 3, characterized in that: A vacuum port is also provided below the process chamber body.
5. The high cleanliness vacuum plasma wafer activation equipment according to claim 4, characterized in that: The interior of the cavity body and the upper cover plate are both provided with a plasma corrosion resistant coating, which is a high-density coating obtained by oxidation, PVD processing or spraying processing.
6. The high cleanliness vacuum plasma wafer activation equipment according to claim 5, characterized in that: The upper electrode and the lower electrode also have coatings on their surfaces.
7. The high cleanliness vacuum plasma wafer activation equipment according to claim 6, characterized in that: The upper electrode may be provided with an upper electrode plasma power input connection module correspondingly, and the lower electrode may be provided with a lower electrode plasma power input connection module correspondingly.
8. The high cleanliness vacuum plasma wafer activation equipment according to claim 7, characterized in that: A wafer transfer port and an observation window are arranged on the process chamber body.
9. The high cleanliness vacuum plasma wafer activation equipment according to claim 8, characterized in that: The lower electrode is mounted on a lower electrode mounting plate, which is made of insulating material. The lower electrode mounting plate is fixed in the main body of the process chamber through a lower electrode supporting column.
10. The high cleanliness vacuum plasma wafer activation equipment according to claim 9, characterized in that: The upper electrode is mounted on an upper electrode mounting plate, the upper electrode mounting plate is made of insulating material, and the upper electrode mounting plate is fixed to the upper cover plate.