Packaging structure and electronic equipment

Abstract

The utility model relates to a packaging structure and electronic equipment, and the packaging structure comprises a device body which is provided with a solder resist window; and a first pin, a second pin and a third pin, the first pin and the second pin are respectively arranged on opposite sides of the device body and are connected with the device body, the third pin is arranged between the solder resist window and the second pin, and the third pin is connected with the solder resist window. And a preset distance is formed between the solder resist window and the first pin. And the first pin and the third pin are intercepted by using the solder mask window, so that solder paste and rosin are prevented from overflowing, micro short between different polarities is effectively inhibited, and a leakage voltage phenomenon is avoided. Moreover, the distance between the first pin and the solder resist window can further intercept solder paste and rosin, thereby avoiding the influence on the first pin, guaranteeing the production yield of the packaging structure, and reducing the production loss cost.

Description

Technical Field

[0001] The present application relates to the technical field of electronic equipment, and in particular to a packaging structure and electronic equipment. Background Art

[0002] With the continuous advancement of science and technology, electronic devices have become one of the indispensable items for people. The devices that support the operation of electronic devices include circuit boards or device bodies, such as metal oxide semiconductor field effect transistors (Metal Oxide Semiconductor Field Effect Transistor, referred to as MOSFET), which belongs to the insulated gate type of field effect transistors. It has the advantages of fast switching speed, good high frequency performance, high input impedance, low driving power, excellent thermal stability, no secondary breakdown problem, wide full working range, high working linearity, etc., and is widely used.

[0003] In the related art, when the MOS tube packaging structure is produced, solder paste and rosin are prone to overflow when soldering the pins, which in turn causes micro shorts or poor leakage voltage. Utility Model Content

[0004] The present application provides a packaging structure and an electronic device, which can avoid the occurrence of micro-short or leakage voltage phenomena, ensure the production yield of the packaging structure, and reduce production loss costs.

[0005] In a first aspect, the present application provides a packaging structure, comprising: a device body, provided with a solder resist window; and a first pin, a second pin and a third pin, wherein the first pin and the second pin are respectively arranged on opposite sides of the device body and connected to the device body, and the third pin is arranged between the solder resist window and the second pin, and the third pin is connected to the solder resist window; wherein there is a preset spacing between the solder resist window and the first pin.

[0006] In one possible implementation, the solder resist window includes a groove opened in the device body, the device body has a first direction and a second direction, and the first direction and the second direction intersect; the size of the groove along the first direction is 2.95mm-3.3mm, and the size of the groove along the second direction is 0.575mm-0.95mm.

[0007] In a possible implementation, the preset spacing is 0.25 mm-0.335 mm.

[0008] In a possible implementation manner, an ink layer is provided between the solder resist window and the first pin.

[0009] In a possible implementation, the height of the ink layer is 10 um-40 um.

[0010] In a possible implementation, the first pin includes a gate and multiple sources, and the gate and the multiple sources are arranged in sequence along a first direction; wherein the center distance between the gate and the adjacent source and / or the center distance between two adjacent sources is 0.60mm-0.70mm.

[0011] In a possible implementation, the second pin includes a plurality of first drains, and the plurality of first drains are sequentially spaced apart along a first direction; wherein a center distance between two adjacent first drains is 0.60 mm-0.70 mm.

[0012] In a possible implementation manner, the third pin includes a second drain electrode; wherein a distance between the second drain electrode and each of the first drain electrodes is 0.2 mm-0.25 mm.

[0013] In a possible implementation, when the first pin and the second pin are along the first direction, a distance between the outermost edges thereof is 3.50 mm-4.00 mm.

[0014] In a second aspect, the present application proposes an electronic device, including a circuit board and a packaging structure as described in the first aspect of the embodiment, wherein the packaging structure is arranged on the circuit board.

[0015] The above technical solution provided by the embodiment of the present application has the following advantages compared with the prior art:

[0016] The packaging structure, circuit board and electronic device provided by the embodiment of the present application use the solder resist window to intercept the first pin and the third pin, prevent the solder paste and rosin from overflowing, effectively suppress the micro short between different polarities, and avoid the leakage voltage phenomenon. There is a certain distance between the first pin and the solder resist window, which can further intercept the solder paste and rosin to avoid affecting the first pin, ensure the production yield of the packaging structure, and reduce the production loss cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0018] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0019] One or more embodiments are exemplarily described by pictures in the corresponding drawings, and these exemplified descriptions do not constitute limitations on the embodiments. Elements with the same reference numerals in the drawings represent similar elements, and unless otherwise stated, the figures in the drawings do not constitute proportional limitations.

[0020] Figure 1 A schematic diagram of a packaging structure provided in an embodiment of the present application;

[0021] Figure 2 A schematic diagram of the packaging structure provided in an embodiment of the present application;

[0022] Figure 3 A schematic diagram of a circuit board provided in an embodiment of the present application.

[0023] Description of reference numerals:

[0024] 1. Packaging structure; 11. Device body; 111. Solder mask window; 1111. Groove; 12. First pin; 121. Gate; 122. Source; 13. Second pin; 131. First drain; 14. Third pin; 15. Ink layer; 2. Circuit board. DETAILED DESCRIPTION

[0025] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0026] The disclosure below provides many different embodiments or examples to implement different structures of the present invention. In order to simplify the disclosure of the present invention, the parts and settings of specific examples are described below. Of course, they are only examples, and the purpose is not to limit the present invention. In addition, the present invention can repeat reference numbers and / or letters in different examples. This repetition is for the purpose of simplification and clarity, and does not itself indicate the relationship between the various embodiments and / or settings discussed.

[0027] For ease of description, spatial relative terms may be used herein to describe the relative positional relationship or movement of one element or feature relative to another element or feature as shown in the figure, such as "inside", "outside", "inner side", "outer side", "below", "below", "above", "above", "front", "back", etc. Such spatial relative terms are intended to include different orientations of the device in use or operation in addition to the orientation depicted in the figure. For example, if the device in the figure undergoes a position flip or a posture change or a motion state change, then these directional indications also change accordingly, for example: an element described as "below other elements or features" or "below other elements or features" will subsequently be oriented as "above other elements or features" or "above other elements or features". Therefore, the example term "below..." may include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or in other directions) and the spatial relative descriptors used herein are interpreted accordingly.

[0028] In order to solve the technical problem that when soldering pins during the production of MOS tube packaging structure in the related art, solder paste and rosin are prone to overflow, which in turn causes micro short or poor leakage voltage, the present application provides a packaging structure that uses solder resist windows to intercept the first pin and the third pin to prevent solder paste and rosin from overflowing, effectively suppress micro short between different polarities, and avoid leakage voltage. The spacing between the first pin and the solder resist window can further intercept solder paste and rosin to avoid affecting the first pin, thereby ensuring the production yield of the packaging structure and reducing production loss costs.

[0029] In some exemplary embodiments, Figure 1-Figure 3 As shown, a packaging structure 1 is a structure for MOS tube packaging, which adopts a dual flat no-lead (DNF) packaging specification to reduce costs and facilitate molding. The packaging structure 1 can be applied to a circuit board 2 to support different functions of the circuit board 2. Among them, one, two or more packaging structures 1 can be set in the circuit board 2, and the packaging structure 1 can be welded to the circuit board 2, or can be plugged and connected to the circuit board 2, which shall be subject to actual conditions.

[0030] Here, it should be noted that other electronic components are also provided on the circuit board 2 to support different functions, which shall be subject to actual conditions and will not be described in detail.

[0031] The packaging structure 1 includes a device body 11 , a first pin 12 , a second pin 13 and a third pin 14 . The device body 11 is electrically connected to other electronic components or a circuit board 2 via the first pin 12 , the second pin 13 and the third pin 14 .

[0032] The device body 11 is, for example, a rectangular plate-shaped structure, which occupies a small space and is convenient for layout when applied to the circuit board 2. The device body 11 is provided with a solder resist window 111, and the solder resist window 111 includes a groove 1111 provided in the device body 11. The groove 1111 is rectangular and can expose the substrate in the device body 11. The groove 1111 can intercept the device body 11 area on both sides. The device body 11 has a first direction (refer to Figure 1 X-axis shown) and a second direction (reference Figure 1 The first direction and the second direction intersect and are preferably perpendicular to each other.

[0033] The dimension j of the groove 1111 along the first direction is 2.95mm-3.3mm, and the dimension b of the groove 1111 along the second direction is 0.575mm-0.95mm, which effectively blocks the areas on both sides of the device body 11 and does not span the entire device body 11, thereby ensuring the strength of the device body 11 and avoiding affecting the service life of the device body 11.

[0034] The first pin 12 and the second pin 13 are arranged on opposite sides of the device body 11 along the second direction. The first pin 12 and the second pin 13 are fixedly connected to the device body 11. The first pin 12 and the second pin 13 are soldered to the device body 11 with solder paste and rosin, for example, so that the connection between the first pin 12 and the second pin 13 is more reliable.

[0035] The third pin 14 is arranged between the solder resist window 111 and the second pin 13. The third pin 14 is connected to the solder resist window 111, that is, the third pin 14 is adjacent to the solder resist window 111, so that when the third pin 14 is soldered, its excess solder paste and rosin can flow into the groove 1111, and avoid flowing to the first pin 12 to cause a micro-short phenomenon, and then produce a poor leakage voltage, affecting the safety of the packaging structure 1 when it is used.

[0036] Among them, there is a predetermined distance between the solder resist window 111 and the first pin 12, and the preset distance a is, for example, 0.25mm-0.335mm, which will neither affect the layout of the first pin 12 nor occupy too much area of ​​the packaging structure, and can also effectively intercept the solder paste and rosin of the third pin 14.

[0037] In this embodiment, if Figure 1As shown, an ink layer 15 is provided between the solder resist window 111 and the first pin 12, and the ink layer 15 covers the device body 11 between the solder resist window 111 and the first pin 12, and the height of the ink layer 15 is, for example, 10um-40um, so as to form a height difference between the area with ink and the area without ink, so as to further intercept the solder paste and rosin in the groove 1111, avoid overflow of the solder paste and rosin in the groove 1111, and ensure that the solder paste and rosin will not be slightly shorted with the first pin 12.

[0038] It should be noted that the above-mentioned ink layer 15 can be partially laid or fully laid. For example, when partially laid, along the first direction, the edge of the ink layer 15 is flush with the edge of the first pin 12, and the ink layer 15 can be set close to the solder mask window 111, or it can be set in the middle position of the preset spacing, as long as effective interception can be achieved. Its width can be 0.1mm, 0.15mm, etc., depending on the actual situation. When the area between the solder mask window 111 and the first pin 12 is fully laid, it can further enhance the interception effect and effectively prevent the rosin or solder paste overflowing from the groove 1111 from flowing to the first pin 12.

[0039] When the first pin 12 and the second pin 13 are along the first direction, the interval i between the outermost edges of the first pin 12 and the second pin 13 is 3.50 mm-4.00 mm, preferably i is 3.82 mm.

[0040] The first pin 12 includes a gate 121 and a plurality of source electrodes 122. The source electrodes 122 may be, for example, but not limited to, three. The gate 121 and the plurality of source electrodes 122 are sequentially spaced along the first direction to avoid mutual interference. The center distance n between the gate 121 and the adjacent source electrode 122 is, for example, 0.60 mm-0.70 mm, preferably n is 0.65 mm, to achieve an effective distance, which will neither increase the length of the device body 11 along the first direction too much nor interfere with each other. The center distance k between two adjacent source electrodes 122 may also be, for example, 0.60 mm-0.70 mm, preferably k is 0.65 mm, to achieve an effective distance.

[0041] The second pin 13 includes a plurality of first drain electrodes 131, for example, four first drain electrodes 131, which are sequentially spaced along the first direction to avoid contact and short circuit. The center distance h between two adjacent first drain electrodes 131 is 0.60 mm-0.70 mm, preferably 0.65 mm.

[0042] The third pin 14 includes a second drain electrode, which disconnects the first drain electrode 131 and the second drain electrode. The spacing d between the second drain electrode and each first drain electrode 131 is 0.2 mm-0.25 mm, and d is specifically 0.24 mm. The second drain electrode and the first drain electrode 131 are designed separately from the device body 11, which effectively prevents the mounting deviation and improves its accuracy.

[0043] The dimension m of the gate electrode 121 along the first direction is 0.35 mm-0.45 mm, preferably m is 0.40 mm, the dimension o of the gate electrode 121 along the second direction is 0.35 mm-0.45 mm, preferably o is 0.40 mm. The dimension p of the source electrode 122 along the first direction is 0.35 mm-0.45 mm, preferably p is 0.40 mm, the dimension l of the source electrode 122 along the second direction is 0.60 mm-0.70 mm, preferably l is 0.65 mm.

[0044] The dimension of the first drain electrode 131 along the first direction e is 0.35mm-0.45mm, preferably e is 0.40mm, the dimension of the second drain electrode along the second direction g is 0.70mm-0.75mm, preferably g is 0.72mm. The dimension of the second drain electrode along the first direction c is 1mm-1.30mm, the dimension of the second drain electrode along the second direction f is 2.00mm-2.50mm, preferably f is 2.35mm.

[0045] Here, it should be noted that within the above-mentioned parameters regarding the size range, the performance of the packaging structure is the best without occupying too much space, which is conducive to the miniaturization of the packaging structure and is suitable for market promotion.

[0046] The package structure proposed in this embodiment uses solder mask openings to intercept the first pin and the third pin, prevent solder paste and rosin from overflowing, effectively suppress micro-shorts between different polarities, and avoid leakage voltage. The ink layer can change the local height to further intercept solder paste and rosin, ensure that micro-shorts do not occur, and improve the production yield of the package structure. The second pin and the third pin can reduce the size of the drain in the device body, which is conducive to the miniaturization design of the package structure.

[0047] The present application also proposes a circuit board, characterized in that it includes a packaging structure as in the above embodiment, and the circuit board is, for example, a printed circuit board (PCB), a flexible printed circuit board (FPCB), or a soft and hard combination plate (reechas) to achieve an integrated design. The packaging structure can be, for example, welded to the circuit board, or plugged into the circuit board to achieve a detachable connection, or can be fixedly connected to improve the reliability of the connection.

[0048] The present application also proposes an electronic device, characterized in that it includes a circuit board as in the above embodiment to support the functions of the electronic device, wherein the electronic device is, for example, a portable device such as a mobile phone, a wearable device, a computer, a display screen, etc.

[0049] It should be understood that the terms used herein are only for the purpose of describing specific example embodiments and are not intended to be limiting. Unless the context clearly indicates otherwise, the singular forms "one", "an" and "said" as used herein may also be meant to include plural forms. The terms "include", "comprise", "contain", and "have" are inclusive, and therefore specify the existence of stated features, steps, operations, elements and / or parts, but do not exclude the existence or addition of one or more other features, steps, operations, elements, parts, and / or combinations thereof. The method steps, processes, and operations described herein are not interpreted as necessarily requiring them to be performed in the specific order described or illustrated, unless the execution order is clearly indicated. It should also be understood that additional or alternative steps may be used.

[0050] Although the terms first, second, third, etc. can be used in the text to describe multiple elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms can only be used to distinguish an element, component, region, layer or section from another region, layer or section. Unless the context clearly indicates, terms such as "first", "second" and other numerical terms do not imply order or sequence when used in the text. Therefore, the first element, component, region, layer or section discussed below can be referred to as the second element, component, region, layer or section without departing from the teaching of the example embodiments.

[0051] The foregoing is merely a specific embodiment of the present invention, which enables those skilled in the art to understand or implement the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A packaging structure, characterized in that: include: The device body is provided with a solder resist window; as well as A first pin, a second pin and a third pin, wherein the first pin and the second pin are respectively arranged at opposite sides of the device body and connected to the device body, and the third pin is arranged between the solder resist window and the second pin, and the third pin is connected to the solder resist window; Wherein, there is a preset distance between the solder resist window and the first pin.

2. The packaging structure according to claim 1, characterized in that: The solder resist opening comprises a groove formed in the device body, the device body has a first direction and a second direction, and the first direction and the second direction intersect; The dimension of the groove along the first direction is 2.95 mm-3.3 mm, and the dimension of the groove along the second direction is 0.575 mm-0.95 mm.

3. The packaging structure according to claim 1, characterized in that: The preset spacing is 0.25mm-0.335mm.

4. The packaging structure according to claim 1, characterized in that: An ink layer is arranged between the solder resist window and the first pin.

5. The packaging structure according to claim 4, characterized in that: The height of the ink layer is 10um-40um.

6. The packaging structure according to claim 1, characterized in that: The first pin includes a gate and a plurality of sources, and the gate and the plurality of sources are arranged in sequence and spaced apart along a first direction; wherein a center distance between the gate and an adjacent source and / or a center distance between two adjacent sources is 0.60 mm-0.70 mm.

7. The packaging structure according to claim 1, characterized in that: The second pin includes a plurality of first drain electrodes, and the plurality of first drain electrodes are sequentially spaced apart along a first direction; wherein a center distance between two adjacent first drain electrodes is 0.60 mm-0.70 mm.

8. The packaging structure according to claim 7, characterized in that: The third pin includes a second drain electrode; wherein the distance between the second drain electrode and each of the first drain electrodes is 0.2 mm-0.25 mm.

9. The packaging structure according to claim 1, characterized in that: When the first pin and the second pin are along the first direction, the distance between the outermost edges thereof is 3.50 mm-4.00 mm.

10. An electronic device, characterized in that: It comprises a circuit board and a packaging structure as claimed in any one of claims 1 to 9, wherein the packaging structure is arranged on the circuit board.

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