Power device and packaging module

Abstract

The utility model provides a power device and a packaging module, the power device has a first direction, the power device comprises a substrate, a first gate region, a first source region, a second gate region and a second source region, the first source region, the substrate and the second source region are stacked in sequence along the first direction, and the first source region and the second source region are both connected with the substrate. The first gate region is located between the first source region and the substrate and connected with the first source region, and the second gate region is located between the second source region and the substrate and connected with the second source region.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductors, and in particular to a power device and a packaging module. Background Art

[0002] Chip Scale Packaging (CSP) technology uses solder balls on the chip surface to replace the bonding metal wires in traditional packaging, which can reduce the parasitic inductance and parasitic resistance caused by the metal wires. CSP technology uses the contact position between the solder balls and the circuit board for mounting, and has the advantages of small package size, simple packaging process and good heat dissipation performance. It is now widely used.

[0003] In the related art, in a trench-type Metal Oxide Semiconductor Field Effect Transistor (MOSFET) power device, the gate and source of the device are arranged on the front side of the substrate, and the drain terminal is arranged on the back side of the substrate. Due to this special electrode arrangement, when CSP packaging is currently performed, the trench-type MOSFET power device adopts a dual-unit structure, and the gate and source terminals of the two units are separately arranged on the front side of the substrate, and a back gold is arranged on the back side of the substrate to connect the two units and serve as a common drain. When this dual-unit trench-type MOSFET power device is turned on, the current is introduced from the source of one unit, first flows through the substrate to the common drain on the back side of the substrate, then flows from the common drain to the substrate of the other unit, and flows from the substrate to the source of the other unit on the front.

[0004] However, the total on-resistance of the trench MOSFET power device with a dual-unit structure includes three parts: the resistance between the source and substrate of one unit, the resistance of the back metal, and the resistance between the source and substrate of another unit, resulting in a higher on-resistance of the power device and a correspondingly higher operating power. Utility Model Content

[0005] The embodiments of the utility model provide a power device and a packaging module to solve the problems of high on-state internal resistance and high working power of the power device in the related art.

[0006] In order to solve the above technical problems, the utility model is achieved as follows:

[0007] In a first aspect, an embodiment of the utility model provides a power device, which has a first direction, and includes a substrate, a first gate region, a first source region, a second gate region, and a second source region. The first source region, the substrate, and the second source region are stacked in sequence along the first direction, and the first source region and the second source region are both connected to the substrate, the first gate region is located between the first source region and the substrate, and is connected to the first source region, and the second gate region is located between the second source region and the substrate, and is connected to the second source region.

[0008] Optionally, the first gate region includes a first gate doping region and a first gate connection region, the first gate doping region and the first gate connection region are stacked along the first direction, the first gate connection region is close to the first source region and connected to the first source region, and the first gate doping region is located between the first gate connection region and the substrate and connected to the first gate connection region.

[0009] Optionally, the first source region includes a first source connection region and a first source doping region, a first trench is provided on the side of the first source connection region facing the substrate, the first gate connection region is located in the first trench, and part of the first gate doping region is embedded in the first trench, and the first source doping region is located between the trench wall of the first trench and the first source doping region.

[0010] Optionally, a first insulating layer is disposed between the first source doping region and the first gate connection region, and between the first source doping region and the first gate connection region.

[0011] Optionally, the first gate region and the second source region are symmetrical with respect to the substrate, and the second source region and the second gate region are symmetrical with respect to the substrate.

[0012] Optionally, a first epitaxial layer is provided between the first source region and the substrate, the first epitaxial layer is connected to both the substrate and the first source region, and the first gate region is located between the first source region and the first epitaxial layer;

[0013] And / or, a second epitaxial layer is arranged between the second source region and the substrate, the second epitaxial layer is connected to the substrate and the second source region, and the second gate region is located between the second source region and the second epitaxial layer.

[0014] Optionally, a second trench is provided on a side of the first epitaxial layer facing the first source region, a second insulating layer is provided on a trench wall of the second trench, and a portion of the first gate region is embedded in the second trench and connected to the second insulating layer;

[0015] And / or, a third trench is provided on the side of the second epitaxial layer facing the second source region, a third insulating layer is provided on the trench wall of the third trench, and a portion of the second gate region is embedded in the third trench and connected to the third insulating layer.

[0016] Optionally, the first source region is provided with a first pad, and the first pad is connected to a side of the first source region facing away from the substrate;

[0017] And / or, the second source region is provided with a second pad, and the second pad is connected to a side of the second source region facing away from the substrate.

[0018] Optionally, a first connecting hole is provided on a side of the first source region away from the substrate, the first connecting hole is connected to the first gate region, the first gate region is provided with a third pad, the third pad is connected to a side of the first gate region away from the substrate, and is embedded in the first connecting hole;

[0019] And / or, a second connecting hole is provided on the side of the second source region away from the substrate, the second connecting hole is connected to the second gate region, the second gate region is provided with a fourth pad, the fourth pad is connected to the side of the second gate region away from the substrate, and is embedded in the second connecting hole.

[0020] In a second aspect, an embodiment of the utility model further provides a packaging module, which includes a circuit board and any one of the power devices described above, wherein the first gate region and the second gate region are both electrically connected to the circuit board.

[0021] In an embodiment of the utility model, the power device includes a substrate, a first gate region, a first source region, a second gate region, and a second source region. Since the first source region, the substrate, and the second source region are stacked in sequence along the first direction, the first source region and the second source region are located on opposite sides of the substrate in the first direction. The first gate region is located between the first source region and the substrate, and is connected to the first source region. The second gate region is located between the second source region and the substrate, and is connected to the second source region. Thus, the first gate region and the second gate region are also located on opposite sides of the substrate in the first direction. The first gate region can control the current to flow between the first source region and the substrate, and the second gate region can control the current to flow between the second source region and the substrate. Since both the first source region and the second source region are connected to the substrate, when the power device is turned on, the current can flow to the substrate through the first source region on one side of the substrate, and then flow to the second source region on the other side of the substrate through the substrate.

[0022] That is, in the power device provided in the embodiment of the utility model, the on-state internal resistance of the power device includes the resistance between the first source region and the substrate, and the resistance between the second source region and the substrate. Compared with the power device in the related art, the total on-state internal resistance is less than the back metal resistance, so that the on-state internal resistance of the power device is lower, thereby reducing its operating power. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 A structural diagram showing a power device in the related art;

[0024] Figure 2 One of the structural diagrams of a power device provided by an embodiment of the utility model is shown;

[0025] Figure 3 A second structural diagram showing a power device provided by an embodiment of the utility model;

[0026] Figure 4 A top view of a power device provided by an embodiment of the utility model is shown;

[0027] Figure 5 A bottom view of a power device provided by an embodiment of the utility model is shown.

[0028] Reference numerals:

[0029] 100: power device; 10: substrate; 20: first source region; 30: second source region; 40: first gate region; 50: second gate region; 41: first gate doping region; 42: first gate connection region; 21: first source doping region; 22: first source connection region; 51: second gate doping region; 52: second gate connection region; 31: second source doping region; 32: second source connection region; 23: first trench; 101: first insulating layer; 60: first epitaxial layer; 70: second epitaxial layer; 61: second trench; 62: second insulating layer; 71: third trench; 72: third insulating layer; 24: first pad; 33: second pad; 43: third pad; 53: fourth pad; 25: first connecting hole; 35: second connecting hole; 201: first unit; 202: second unit; 203: back gold; X: first direction. DETAILED DESCRIPTION

[0030] The following will be combined with the drawings in the embodiments of the utility model to clearly and completely describe the technical solutions in the embodiments of the utility model. Obviously, the described embodiments are part of the embodiments of the utility model, not all of the embodiments. Based on the embodiments of the utility model, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the utility model.

[0031] It should be understood that the references to "one embodiment" or "an embodiment" throughout the specification mean that the specific features, structures, or characteristics associated with the embodiment are included in at least one embodiment of the present invention. Therefore, the references to "in one embodiment" or "in an embodiment" appearing throughout the specification do not necessarily refer to the same embodiment. In addition, these specific features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0032] like Figures 2 to 5 As shown, the power device 100 has a first direction X, and the power device 100 includes a substrate 10, a first gate region 40, a first source region 20, a second gate region 50, and a second source region 30. The first source region 20, the substrate 10, and the second source region 30 are stacked in sequence along the first direction X, and the first source region 20 and the second source region 30 are both connected to the substrate 10. The first gate region 40 is located between the first source region 20 and the substrate 10, and is connected to the first source region 20. The second gate region 50 is located between the second source region 30 and the substrate 10, and is connected to the second source region 30.

[0033] In the embodiment of the utility model, the power device 100 includes a substrate 10, a first gate region 40, a first source region 20, a second gate region 50, and a second source region 30. Since the first source region 20, the substrate 10, and the second source region 30 are sequentially stacked along the first direction X, the first source region 20 and the second source region 30 are located on opposite sides of the substrate 10 in the first direction X. The first gate region 40 is located between the first source region 20 and the substrate 10, and is connected to the first source region 20. The second gate region 50 is located between the second source region 30 and the substrate 10, and is connected to the second source region 30. Therefore, the first gate region 40 and the second gate region 50 are also located on opposite sides of the substrate 10 in the first direction X. The first gate region 40 can control the current to flow between the first source region 20 and the substrate 10, and the second gate region 50 can control the current to flow between the second source region 30 and the substrate 10. Since the first source region 20 and the second source region 30 are both connected to the substrate 10 , when the power device 100 is turned on, current can flow to the substrate 10 through the first source region 20 on one side of the substrate 10 , and then flow to the second source region 30 on the other side of the substrate 10 through the substrate 10 .

[0034] That is, in the power device 100 provided in the embodiment of the utility model, the on-state internal resistance of the power device 100 includes the resistance between the first source region 20 and the substrate 10, and the resistance between the second source region 30 and the substrate 10. Compared with the power device 100 in the related art, the total on-state internal resistance is less than the resistance of the back gold 203, so that the on-state internal resistance of the power device 100 is lower, thereby reducing its operating power.

[0035] See also Figure 1 , Figure 1 The structure diagram of the power device in the related art is shown. Figure 1 It can be seen that in the related art, the first unit 201 and the second unit 202 are arranged at intervals on the same side of the substrate 10, and the other side of the substrate 10 is provided with a back gold 203. When the substrate 10 is placed horizontally, the first unit 201 and the second unit 202 are arranged in a bilaterally symmetrical manner. When the power device 100 is turned on, the current flows from the source of the first unit 201 through the substrate 10, the back gold 203, and the substrate 10 to the source of the second unit 202, as shown in FIG. Figure 1 As shown by the direction of the arrow in the figure. The resistance of the back gold 203 is generally large, and it occupies a large proportion of the total on-resistance of the power device. In the embodiment of the utility model, the first source region 20 and the first gate region 40 can form a unit, and the second source region 30 and the second gate region 50 can form another unit, and the two units are respectively located on both sides of the substrate 10. When the substrate 10 is placed horizontally, the first direction X is also consistent with the thickness direction of the power device 100. At this time, the two units are arranged in a "back-to-back" manner above and below the substrate 10. When the power device 100 is turned on, the current diameter flows from the source of the first unit 201 through the substrate 10 to the source of the second unit 202, shortening the current flow path and reducing the overall on-resistance of the power device 100.

[0036] In addition, in some embodiments, Figure 3 The first gate region 40 may include a first gate doping region 41 and a first gate connection region 42. The first gate doping region 41 and the first gate connection region 42 are stacked along the first direction X. The first gate connection region 42 faces the first source region 20 and is connected to the first source region 20. The first gate doping region 41 is located between the first gate connection region 42 and the substrate 10, and is connected to the first gate connection region 42.

[0037] The first gate region 40 includes a first gate doping region 41 and a first gate connection region 42, and the first gate doping region 41 and the first gate connection region 42 may be both located between the first source region 20 and the substrate 10. Specifically, the first gate doping region 41 and the first gate connection region 42 may also be stacked along the first direction X, and the first gate connection region 42 is close to the first source region 20, and the first gate doping region 41 is far away from the first source region 20, wherein the first gate connection region 42 is connected to the first source region 20, so that the first gate region 40 can be set, so that the first gate region 40 can receive a voltage to change the electric field between the first gate region 40 and the substrate 10, so as to control the current flow direction between the first source region 20 and the substrate 10.

[0038] In addition, in some embodiments, Figure 3As shown, the first source region 20 may include a first source connection region 22 and a first source doping region 21. A first trench 23 is provided on the side of the first source connection region 22 facing the substrate 10. The first gate connection region 42 is located in the first trench 23, and part of the first gate doping region 41 is embedded in the first trench 23. The first source doping region 21 is located between the groove wall of the first trench 23 and the first source doping region 21.

[0039] The first source region 20 includes a first source connection region 22 and a first source doping region 21. A first trench 23 is provided on the side of the first source connection region 22 facing the substrate 10. The first gate connection region 42 is located in the first trench 23, and part of the first gate doping region 41 is embedded in the first trench 23. That is, the first gate connection region 42 is entirely located in the first trench 23 and is wrapped by the first source connection region 22. Part of the first gate doping region 41 is located in the first trench, and the other part extends out of the first source connection region 22. The first source doping region 21 is located between the groove wall of the first trench 23 and the first source doping region 21. The first source doping region 21 and the first gate doping region 41 can increase the carriers in the power device 100 and improve the conductivity, so that when the power device 100 is turned on, the current can flow normally in the power device 100.

[0040] The first source connection region 22 and the first gate connection region 42 can be used as the parts for connecting the power device 100 with external devices and as the connection terminals of the power device 100 so as to place the power device 100 in a circuit for application.

[0041] It should be noted that, in the actual production process, after the substrate 10 is manufactured, the first gate doping region 41 and the first gate connection region 42 can be deposited on the substrate 10. After the first gate doping region 41 and the first gate connection region 42 are deposited, the first source doping region 21 and the first source connection region 22 can be deposited on the first gate connection region 42. When the first source connection region 22 is deposited, the first gate connection region 42 and the first gate doping region 41 will block part of the area, so that there will be a groove on the first source connection region 22 at a position opposite to the first gate connection region 42, which is the above-mentioned first groove 23. That is, the first groove 23 is generated when the first source connection region 22 is deposited, which is reflected in the power device 100 after the manufacturing is completed. In actual production, the first groove 23 is not pre-set and is set outside the first gate.

[0042] In addition, in some embodiments, Figure 3 As shown, a first insulating layer 101 may be disposed between the first source doping region 21 and the first gate connection region 42 , and between the first source doping region 21 and the first gate connection region 42 .

[0043] A first insulating layer 101 is provided between the first source doping region 21 and the first gate connection region 42, and between the first source doping region 21 and the first gate connection region 42. The first insulating layer 101 can isolate the first source doping region 21 from the first gate doping region 41, and isolate the first source doping region 21 from the first source connection region 22, thereby preventing current from flowing directly between the first gate region 40 and the first source region 20, which would affect the normal operation of the power device 100.

[0044] It should be noted that the first insulating layer 101 may be made of silicon oxide, silicon nitride, etc. The specific material of the first insulating layer 101 is not specifically limited in the embodiment of the utility model.

[0045] In addition, in some embodiments, Figure 1 As shown, the first gate region 40 and the second source region 30 may be symmetrical relative to the substrate 10 , and the second source region 30 and the second gate region 50 may be symmetrical relative to the substrate 10 .

[0046] Since the first gate region 40 and the second source region 30 are symmetrical relative to the substrate 10, and the second source region 30 and the second gate region 50 are symmetrical relative to the substrate 10, the two units are symmetrically arranged along the thickness direction of the power device 100. When manufacturing the power device 100, it can be manufactured on two opposite surfaces of the substrate 10 respectively.

[0047] In the case where the first gate region 40 includes the first gate doping region 41 and the first gate connection region 42, and the first source region 20 includes the first source doping region 21 and the first source connection region 22, correspondingly, the second gate region 50 may also include the second gate doping region 51 and the second gate connection region 52, and the second source region 30 may also include the second source doping region 31 and the second source connection region 32. The arrangement of the second gate doping region 51, the second gate connection region 52, the second source doping region 31, and the second source connection region 32 may refer to the arrangement of the first gate doping region 41, the first gate connection region 42, the first source doping region 21, and the first source connection region 22, and the embodiment of the utility model is not specifically limited here.

[0048] In addition, in some embodiments, Figure 3 As shown, a first epitaxial layer 60 may be arranged between the first source region 20 and the substrate 10, the first epitaxial layer 60 is connected to both the substrate 10 and the first source region 20, and the first gate region 40 is located between the first source region 20 and the first epitaxial layer 60; and / or a second epitaxial layer 70 is arranged between the second source region 30 and the substrate 10, the second epitaxial layer 70 is connected to both the substrate 10 and the second source region 30, and the second gate region 50 is located between the second source region 30 and the second epitaxial layer 70.

[0049] A first epitaxial layer 60 may be disposed between the first source region 20 and the substrate 10. The first epitaxial layer 60 is connected to the substrate 10 and the first source region 20. The first source region 20 and the first gate region 40 above may be supported by the first substrate 10, and the performance of the power device 100 may be guaranteed. Specifically, the surface of the substrate 10 will inevitably have defects during the production process. If the first gate region 40 and the first source region 20 are directly disposed on the substrate 10, the defects on the surface of the substrate 10 will directly affect the performance of the power device 100.

[0050] A second epitaxial layer 70 may be disposed between the second source region 30 and the substrate 10. The second epitaxial layer 70 is connected to the substrate 10 and the second source region 30. The second source region 30 and the second gate region 50 above may be supported by the second substrate 10, and the performance of the power device 100 may be guaranteed. Specifically, the surface of the substrate 10 will inevitably have defects during the production process. If the second gate region 50 and the second source region 30 are directly disposed on the substrate 10, the defects on the surface of the substrate 10 will directly affect the performance of the power device 100.

[0051] In addition, in some embodiments, Figure 3 As shown, a second trench 61 may be provided on the side of the first epitaxial layer 60 facing the first source region 20, a second insulating layer 62 may be provided on the wall of the second trench 61, a portion of the first gate region 40 may be embedded in the second trench 61 and connected to the second insulating layer 62; and / or a third trench 71 may be provided on the side of the second epitaxial layer 70 facing the second source region 30, a third insulating layer 72 may be provided on the wall of the third trench 71, a portion of the second gate region 50 may be embedded in the third trench 71 and connected to the third insulating layer 72.

[0052] A second trench 61 is provided on one side of the first epitaxial layer 60 facing the first source region 20, a second insulating layer 62 may be provided on the groove wall of the second trench 61, and a portion of the first gate region 40 is embedded in the second trench 61 and connected to the second insulating layer 62. Specifically, a portion of the first gate doping region 41 may extend from the first source connection region 22, a portion of the first gate doping region 41 may be embedded in the first trench 23, and another portion of the first gate doping region 41 may be embedded in the second trench 61. Since the second insulating layer 62 is provided in the second trench 61, the first gate doping region 41 and the substrate 10 may be isolated by the second insulating layer 62, thereby playing a role in protecting and controlling the current.

[0053] It should be noted that, in actual production, the first epitaxial layer 60 can be first deposited on the substrate 10, and in the process of depositing the first epitaxial layer 60, a second groove 61 is provided on the first epitaxial layer 60, and then the first source doping region 21 is deposited on the first epitaxial layer 60, and the first source doping region 21 is located at the periphery of the first groove 23, exposing the notch of the second groove 61; then, the first insulating layer 101 can be deposited on the first source doping region 21, and the second insulating layer 62 can be deposited on the groove wall of the second groove 61, and the first insulating layer 101 and the second insulating layer 62 are connected; then, the first gate doping region 41 is deposited through the notch of the second groove 61, so that the first gate doping region 41 extends outward from the second groove 61; then, the first gate connection region 42 is deposited on the first gate doping region 41 and the first insulating layer 101; finally, the first source connection region 22 can be deposited to complete the production of one unit.

[0054] A third trench 71 is provided on one side of the second epitaxial layer 70 facing the second source region 30, a third insulating layer 72 may be provided on the groove wall of the third trench 71, and a portion of the second gate region 50 is embedded in the third trench 71 and connected to the third insulating layer 72. Specifically, a portion of the second gate doping region 51 may extend from the second source connection region 32, a portion of the second gate doping region 51 may be embedded in the first trench 23, and another portion of the second gate doping region 51 may be embedded in the third trench 71. Since the third insulating layer 72 is provided in the third trench 71, the second gate doping region 51 and the substrate 10 may be isolated by the third insulating layer 72, thereby playing a role in protecting and controlling the current.

[0055] It should be noted that the deposition method of the second source region 30, the second gate region 50, the second epitaxial layer 70 and the third insulating layer 72 can refer to the above description of the deposition method of the first source region 20, the first gate region 40, the first epitaxial layer 60 and the second insulating layer 62, and the embodiment of the utility model is not specifically limited here.

[0056] It should also be noted that the first insulating layer 101 and the second insulating layer 62 can be deposited using the same material and obtained in one deposition process. In the case where the second gate region 50 includes the second gate doping region 51 and the second gate connection region 52, and the second source region 30 includes the second source doping region 31 and the second source connection region 32, an insulating layer can also be provided between the second source doping region 31 and the second gate doping region 51 and the second gate connection region 52, and the insulating layer and the third insulating layer 72 can also be deposited using the same material and obtained in one deposition process.

[0057] In addition, in some embodiments, Figure 4 , Figure 5As shown, the first source region 20 may be provided with a first pad 24 connected to the side of the first source region 20 facing away from the substrate 10 ; and / or, the second source region 30 may be provided with a second pad 33 connected to the side of the second source region 30 facing away from the substrate 10 .

[0058] The first source region 20 is provided with a first pad 24, and the first pad 24 can provide a connection position for the first source region 20. When the power device 100 is connected, the first source region 20 can be connected through the first pad 24. The first source region 20 is located on the side of the substrate 10 away from the second source region 30. It can be considered that the first source region 20 is located on the surface of the power device 100. Since the first pad 24 is connected to the side of the first source region 20 away from the substrate 10, the first pad 24 can be exposed, which is convenient for connecting the first pad 24 with other devices.

[0059] The second source region 30 is provided with a second pad 33, and the second pad 33 can provide a connection position for the second source region 30. When the power device 100 is connected, the second source region 30 can be connected through the second pad 33. The second source region 30 is located on the side of the substrate 10 away from the first source region 20. It can be considered that the second source region 30 is located on the surface of the power device 100. Since the second pad 33 is connected to the side of the second source region 30 away from the substrate 10, the second pad 33 can be exposed, which is convenient for connecting the second pad 33 with other devices.

[0060] It should be noted that the number of the first pads 24 can be multiple, and the multiple first pads 24 are arranged at intervals on the side of the first source region 20 away from the substrate 10, and the multiple first pads 24 can provide multiple connection positions for the first source region 20; the number of the second pads 33 can be multiple, and the multiple second pads 33 are arranged at intervals on the side of the second source region 30 away from the substrate 10, and the multiple second pads 33 can provide multiple connection positions for the second source region 30. Among them, the number of the first pads 24 can be 2, 3, 4, 5, etc., the number of the second pads 33 can be 2, 3, 4, 5, etc., the number of the first pads 24 and the number of the second pads 33 can be different or the same, and the specific setting values ​​of the first pads 24 and the second pads 33 are not specifically limited in the embodiment of the utility model.

[0061] It should also be noted that when the substrate 10 is placed horizontally so that the first direction X is parallel to the vertical direction, the first source region 20 can be located above the power device 100, and the second source region 30 can be located below the power device 100, so that the first soldering pad 24 and the second soldering pad 33 are respectively arranged above and below the power device 100, so that the first soldering pad 24 and the second soldering pad 33 are convenient for connecting different devices or different terminals of the same device. Since there are multiple first soldering pads 24 and second soldering pads 33, misconnection of the first soldering pad 24 and the second soldering pad 33 can be avoided.

[0062] In addition, in some embodiments, Figure 4 , Figure 5 As shown, a first connecting hole 25 may be provided on the side of the first source region 20 facing away from the substrate 10, and the first connecting hole 25 is connected to the first gate region 40. The first gate region 40 may be provided with a third soldering pad 43, and the third soldering pad 43 is connected to the side of the first gate region 40 facing away from the substrate 10 and is embedded in the first connecting hole 25; and / or, a second connecting hole 35 may be provided on the side of the second source region 30 facing away from the substrate 10, and the second connecting hole 35 is connected to the second gate region 50, and the second gate region 50 may be provided with a fourth soldering pad 53, and the fourth soldering pad 53 is connected to the side of the second gate region 50 facing away from the substrate 10 and is embedded in the second connecting hole 35.

[0063] A first connecting hole 25 is provided on the side of the first source region 20 facing away from the substrate 10, and the first connecting hole 25 is connected to the first gate region 40. Therefore, the provision of the first connecting hole 25 can expose the first gate region 40 to facilitate connection with the first gate region 40. A third pad 43 is provided on the first gate region 40, and the third pad 43 can provide a connection position for the first gate region 40. When the power device 100 is connected, the first gate region 40 can be connected through the third pad 43. Since the third pad 43 is connected to the side of the first gate region 40 facing away from the substrate 10 and is embedded in the first connecting hole 25, the first pad 24 can be exposed through the first connecting hole 25, which facilitates the connection of the third pad 43 with other devices.

[0064] A second connecting hole 35 is provided on the side of the second source region 30 facing away from the substrate 10, and the second connecting hole 35 is connected to the second gate region 50. Therefore, the second connecting hole 35 can be provided to expose the second gate region 50 to facilitate connection with the second gate region 50. A fourth pad 53 is provided on the second gate region 50, and the fourth pad 53 can provide a connection position for the second gate region 50. When the power device 100 is connected, the second gate region 50 can be connected through the fourth pad 53. Since the fourth pad 53 is connected to the side of the second gate region 50 facing away from the substrate 10 and is embedded in the second connecting hole 35, the fourth pad 53 can be exposed through the second connecting hole 35, which facilitates the connection of the fourth pad 53 with other devices.

[0065] It should be noted that the number of the third pads 43 can be multiple, and the multiple third pads 43 are arranged at intervals on the side of the first gate region 40 away from the substrate 10, and the multiple third pads 43 can provide multiple connection positions for the first gate region 40; the number of the fourth pads 53 can be multiple, and the multiple fourth pads 53 are arranged at intervals on the side of the second gate region 50 away from the substrate 10, and the multiple fourth pads 53 can provide multiple connection positions for the second gate region 50. Among them, the number of the third pads 43 can be 2, 3, 4, 5, etc., the number of the fourth pads 53 can be 2, 3, 4, 5, etc., the number of the third pads 43 and the number of the fourth pads 53 can be different or the same, and the specific setting values ​​of the third pads 43 and the fourth pads 53 are not specifically limited in the embodiment of the utility model.

[0066] It should also be noted that when the substrate 10 is placed horizontally so that the third direction is parallel to the vertical direction, the first source region 20 can be located above the power device 100, and the second source region 30 can be located below the power device 100. Therefore, the first connecting hole 25 can be located above the power device 100, and the second connecting hole 35 can be located below the power device 100, so that the third soldering pad 43 and the fourth soldering pad 53 are respectively arranged above and below the power device 100, which is convenient for the third soldering pad 43 and the fourth soldering pad 53 to connect different devices or different terminals of the same three devices. Since there are multiple third soldering pads 43 and fourth soldering pads 53, misconnection of the third soldering pad 43 and the fourth soldering pad 53 can be avoided.

[0067] In the embodiment of the utility model, the power device 100 includes a substrate 10, a first gate region 40, a first source region 20, a second gate region 50, and a second source region 30. Since the first source region 20, the substrate 10, and the second source region 30 are sequentially stacked along the first direction X, the first source region 20 and the second source region 30 are located on opposite sides of the substrate 10 in the first direction X. The first gate region 40 is located between the first source region 20 and the substrate 10, and is connected to the first source region 20. The second gate region 50 is located between the second source region 30 and the substrate 10, and is connected to the second source region 30. Therefore, the first gate region 40 and the second gate region 50 are also located on opposite sides of the substrate 10 in the first direction X. The first gate region 40 can control the current to flow between the first source region 20 and the substrate 10, and the second gate region 50 can control the current to flow between the second source region 30 and the substrate 10. Since the first source region 20 and the second source region 30 are both connected to the substrate 10 , when the power device 100 is turned on, current can flow to the substrate 10 through the first source region 20 on one side of the substrate 10 , and then flow to the second source region 30 on the other side of the substrate 10 through the substrate 10 .

[0068] That is, in the power device 100 provided in the embodiment of the utility model, the on-state internal resistance of the power device 100 includes the resistance between the first source region 20 and the substrate 10, and the resistance between the second source region 30 and the substrate 10. Compared with the power device 100 in the related art, the total on-state internal resistance is less than the resistance of the back gold 203, so that the on-state internal resistance of the power device 100 is lower, thereby reducing its operating power.

[0069] It should be noted that, in order to make the purpose, technical solution and beneficial effects of the present invention clearer, the on-state internal resistance of the power device 100 provided in the embodiment of the present invention and the on-state internal resistance of the power device 100 in the related art are compared and described below to further describe the present invention. It should be understood that these embodiments are only used to illustrate the present invention and are not used to limit the scope of the present invention.

[0070] Assume that the on-resistance from the source of the first electrode unit 201 to the substrate 10 is consistent with the on-resistance from the source of the second unit 202 to the substrate 10, both of which are R1, which is 1mΩ, and the on-resistance of the back-gold 203 is R2. Since the back-gold 203 accounts for a large proportion of the overall internal resistance in the power device, R2 is set to 2mΩ. In the related art, the overall internal resistance of the power device is R1+R2+R1=4mΩ. In the embodiment of the utility model, since the setting of the back-gold 203 is cancelled, the on-resistance from the first source region 20 to the second source region 30 is the sum of the on-resistance from the first source region 20 to the substrate 10 and the on-resistance from the second source region 30 to the substrate 10. The corresponding total on-resistance of the power device 100 is R1+R1=2mΩ, and the internal resistance reduction ratio is (4-2) / 4×100%=50%. According to the power formula P=I^2×R, it can be seen that its heat generation is also reduced by 50%.

[0071] In addition, an embodiment of the utility model further provides a packaging module, which includes a circuit board and the power device 100 in any of the above embodiments, and the first gate region 40 and the second gate region 50 are both electrically connected to the circuit board.

[0072] In the package module provided with the above-mentioned power device 100, since the first source region 20, the substrate 10, and the second source region 30 are sequentially stacked along the first direction X, and the first source region 20 and the second source region 30 are both connected to the substrate 10, the two units in the power device 100 can form a similar "back-to-back" arrangement, avoiding the additional arrangement of the back gold 203 in the power device 100. When the power device 100 is turned on, the current can flow to the substrate 10 through the first source region 20 on one side of the substrate 10, and then flow to the second source region 30 on the other side of the substrate 10 through the substrate 10, which can make the on-state internal resistance of the power device 100 lower, thereby reducing its operating power.

[0073] It should be noted that the power device 100 may have two control terminals, one of which is electrically connected to the first gate region 40 , and the other is electrically connected to the second gate region 50 , so that the conduction of the two units can be controlled by the two gates, thereby controlling the conduction of the power device 100 .

[0074] It should also be noted that the packaging module can be provided in an electrical device, in which a battery cell and an electronic device are provided, the first source region 20 can be electrically connected to the battery cell, and the second source region 30 can be electrically connected to the electronic device. It should be noted that the various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments, and the same or similar parts between the various embodiments can be referred to each other.

[0075] Although the optional embodiments of the utility model embodiments have been described, those skilled in the art may make additional changes and modifications to these embodiments once they are aware of the basic creative concepts. Therefore, the attached claims are intended to be interpreted as including optional embodiments and all changes and modifications that fall within the scope of the utility model embodiments. Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity from another entity, and do not necessarily require or imply that there is any such actual relationship or order between these entities. Moreover, the terms "include", "comprise" or any other variant thereof are intended to cover non-exclusive inclusion, so that an article or terminal device including a series of elements includes not only those elements, but also other elements that are not explicitly listed, or also includes elements inherent to such articles or terminal devices. In the absence of more restrictions, the elements defined by the sentence "including one..." do not exclude the existence of other identical elements in the article or terminal device including the elements.

[0076] The technical solution provided by the present invention is introduced in detail above. Specific examples are used in this article to illustrate the principle and implementation method of the present invention. At the same time, for those skilled in the art, according to the principle and implementation method of the present invention, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims

1. A power device (100), characterized in that: The power device (100) has a first direction (X), and comprises a substrate (10), a first gate region (40), a first source region (20), a second gate region (50), and a second source region (30); the first source region (20), the substrate (10), and the second source region (30) are sequentially stacked along the first direction (X), and the first source region (20) and the second source region (30) are both connected to the substrate (10); the first gate region (40) is located between the first source region (20) and the substrate (10), and is connected to the first source region (20); the second gate region (50) is located between the second source region (30) and the substrate (10), and is connected to the second source region (30).

2. The power device (100) according to claim 1, characterized in that: The first gate region (40) comprises a first gate doping region (41) and a first gate connection region (42); the first gate doping region (41) and the first gate connection region (42) are stacked along the first direction (X); the first gate connection region (42) faces the first source region (20) and is connected to the first source region (20); the first gate doping region (41) is located between the first gate connection region (42) and the substrate (10), and is connected to the first gate connection region (42).

3. The power device (100) according to claim 2, characterized in that: The first source region (20) comprises a first source connection region (22) and a first source doping region (21); a first groove (23) is arranged on a side of the first source connection region (22) close to the substrate (10); the first gate connection region (42) is located in the first groove (23), and a portion of the first gate doping region (41) is embedded in the first groove (23); and the first source doping region (21) is located between a groove wall of the first groove (23) and the first source doping region (21).

4. The power device (100) according to claim 3, characterized in that: A first insulating layer (101) is provided between the first source doping region (21) and the first gate connection region (42), and between the first source doping region (21) and the first gate connection region (42).

5. The power device (100) according to claim 1, characterized in that: The first gate region (40) and the second source region (30) are symmetrical relative to the substrate (10), and the second source region (30) and the second gate region (50) are symmetrical relative to the substrate (10).

6. The power device (100) according to claim 1, characterized in that: A first epitaxial layer (60) is arranged between the first source region (20) and the substrate (10); the first epitaxial layer (60) is connected to the substrate (10) and the first source region (20); and the first gate region (40) is located between the first source region (20) and the first epitaxial layer (60); And / or, a second epitaxial layer (70) is arranged between the second source region (30) and the substrate (10), the second epitaxial layer (70) is connected to the substrate (10) and the second source region (30), and the second gate region (50) is located between the second source region (30) and the second epitaxial layer (70).

7. The power device (100) according to claim 6, characterized in that: A second trench (61) is provided on one side of the first epitaxial layer (60) facing the first source region (20); a second insulating layer (62) is provided on the trench wall of the second trench (61); a portion of the first gate region (40) is embedded in the second trench (61) and connected to the second insulating layer (62); And / or, a third trench (71) is provided on the side of the second epitaxial layer (70) facing the second source region (30), a third insulating layer (72) is provided on the groove wall of the third trench (71), and a portion of the second gate region (50) is embedded in the third trench (71) and connected to the third insulating layer (72).

8. The power device (100) according to claim 1, characterized in that: The first source region (20) is provided with a first pad (24), and the first pad (24) is connected to a side of the first source region (20) facing away from the substrate (10); And / or, the second source region (30) is provided with a second pad (33), and the second pad (33) is connected to a side of the second source region (30) facing away from the substrate (10).

9. The power device (100) according to claim 1, characterized in that: A first connecting hole (25) is provided on a side of the first source region (20) facing away from the substrate (10), the first connecting hole (25) is connected to the first gate region (40), the first gate region (40) is provided with a third pad (43), the third pad (43) is connected to a side of the first gate region (40) facing away from the substrate (10), and is embedded in the first connecting hole (25); And / or, a second connecting hole (35) is provided on a side of the second source region (30) facing away from the substrate (10), the second connecting hole (35) is connected to the second gate region (50), the second gate region (50) is provided with a fourth soldering pad (53), the fourth soldering pad (53) is connected to a side of the second gate region (50) facing away from the substrate (10), and is embedded in the second connecting hole (35).

10. A packaging module, characterized in that: The packaging module comprises a circuit board and the power device (100) according to any one of claims 1 to 9, and the first gate region (40) and the second gate region (50) are both electrically connected to the circuit board.

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