Inverted light emitting diode

Abstract

The utility model provides a flip light emitting diode, which comprises a substrate and an epitaxial wafer deposited on the substrate, the epitaxial wafer comprises a first conducting layer, a first insulating layer, a second conducting layer and a second insulating layer, the first insulating layer is internally provided with a first insulating layer through hole, the first conducting layer is partially arranged in the first insulating layer through hole, and the second insulating layer is partially arranged in the second insulating layer through hole. A second insulating layer through hole is formed in the second insulating layer, a bonding pad layer is deposited in the second insulating layer through hole, the width of the second insulating layer through hole is gradually reduced from the center to the two ends, and the length d of the second insulating layer through hole is larger than the minimum distance d1 from the end of the second insulating layer through hole to the first conductive layer; therefore, the current injected through the bonding pad layer is transversely spread after passing through the second conductive layer, and then is vertically transmitted into the first conductive layer through the first insulating layer through hole. According to the flip light emitting diode provided by the utility model, the EOS resistance of the diode can be effectively improved.

Description

Technical Field

[0001] The utility model relates to the field of optoelectronic technology, in particular to a flip-chip light emitting diode. Background Art

[0002] In recent years, light-emitting diode chips have become the focus of research due to their high efficiency, energy saving, environmental protection, and wide application. Flip-chip light-emitting diode chips have the advantages of back-emitting light, strong heat dissipation capacity, good weldability, large thrust, and strong reliability.

[0003] More and more manufacturers are applying flip-chip LED chips to the preparation of TV backlight lamp beads. However, TV backlight applications have strict requirements on the ability of flip-chip LED chips to resist EOS (Electrical Over Stress). At present, the current injected from the welding pad of the flip-chip LED chip directly enters the chip through the current layer. The injected current lacks buffering, which can easily lead to electrical stress overload and damage the chip. Utility Model Content

[0004] Based on this, the purpose of the utility model is to provide a flip-chip light emitting diode to solve the technical problems existing in the prior art.

[0005] The utility model provides a flip-chip light-emitting diode, comprising a substrate, an epitaxial wafer deposited on the substrate, the epitaxial wafer comprising a first conductive layer, a first insulating layer, a second conductive layer, and a second insulating layer, a first insulating layer through hole is opened in the first insulating layer, a portion of the first conductive layer is arranged in the first insulating layer through hole, the first conductive layer and the second conductive layer are partially isolated by the first insulating layer, a second insulating layer through hole is arranged on the second insulating layer, a pad layer is deposited in the second insulating layer through hole, a portion of the second conductive layer is located below the pad layer and is electrically connected thereto, the center lines of the first insulating layer through hole and the second insulating layer through hole do not overlap, the width of the second insulating layer through hole gradually decreases from the center to both ends, and the length d of the second insulating layer through hole is greater than the minimum distance d1 between the end of the second insulating layer through hole and the first conductive layer, so that the current injected through the pad layer propagates laterally after passing through the second conductive layer, and then is vertically transmitted to the first conductive layer through the first insulating layer through hole.

[0006] Preferably, the epitaxial wafer also includes an N-type semiconductor layer, an active light-emitting layer, and a P-type semiconductor layer sequentially deposited on the substrate, the epitaxial wafer includes an N-type conductive region and a P-type conductive region that are electrically connected, a plurality of N-type semiconductor layer conductive steps are discontinuously etched on the N-type conductive region, the bottom of the N-type semiconductor layer conductive steps is connected to the N-type semiconductor layer, a plurality of current blocking layers are discontinuously provided on the P-type conductive region, and the current blocking layers are deposited on the P-type semiconductor layer.

[0007] Preferably, the first conductive layer includes an N-type first conductive layer, the second conductive layer includes an N-type second conductive layer, the first insulating layer through hole includes an N-type first insulating layer through hole, the N-type first conductive layer is arranged in the N-type first insulating layer through hole, the top of the N-type first conductive layer is connected to the N-type second conductive layer, and the other areas of the N-type conductive area protruding from the N-type first insulating layer through hole are sequentially deposited with the first insulating layer, the N-type second conductive layer, and the second insulating layer.

[0008] Preferably, the second insulating layer through hole comprises an N-type second insulating layer through hole, the pad layer comprises an N-type pad layer, the N-type second insulating layer through hole is located above the N-type second conductive layer, and an N-type pad layer is disposed in the N-type second insulating layer through hole.

[0009] Preferably, the first conductive layer also includes a P-type first conductive layer, the second conductive layer also includes a P-type second conductive layer, the first insulating layer through hole also includes a P-type first insulating layer through hole, the P-type first conductive layer is arranged in the P-type first insulating layer through hole, the top of the P-type first conductive layer is connected to the P-type second conductive layer, and the other areas of the P-type conductive area protruding out of the P-type first insulating layer through hole are sequentially deposited with the first insulating layer, the P-type second conductive layer, and the second insulating layer.

[0010] Preferably, the second insulating layer through hole comprises a P-type second insulating layer through hole, the pad layer comprises a P-type pad layer, the P-type second insulating layer through hole is located above the P-type second conductive layer, and a P-type pad layer is provided in the P-type second insulating layer through hole.

[0011] Preferably, a current spreading layer is provided between the current blocking layer and the P-type first conductive layer.

[0012] Preferably, an isolation groove is etched at the edge of the epitaxial wafer and extends to the substrate.

[0013] Preferably, d1≤d≤2d1, wherein d1≥0.15um, the center width of the through hole of the second insulating layer is L, and the end width is L1, wherein 0.1L≤L1≤0.5L.

[0014] Compared with the prior art, the utility model has the following beneficial effects: it includes a substrate, an epitaxial wafer deposited on the substrate, the epitaxial wafer includes an N-type semiconductor layer, a first conductive layer, a first insulating layer, a second conductive layer, and a second insulating layer, by arranging a second insulating through hole on the second insulating layer, the second insulating through hole is not in a pad layer, the first conductive layer and part of the second conductive layer are separated by the first insulating layer in a partial lateral portion, the width of the second insulating layer through hole gradually decreases from the center to both ends, the length d of the second insulating layer through hole is greater than the minimum distance d1 between the end of the second insulating layer through hole and the first conductive layer, so that the large current injected through the pad layer propagates laterally after passing through the second conductive layer, and then is transmitted to the first conductive layer through the first insulating layer through hole; the EOS resistance capability of the flip-chip LED chip is improved, and it is suitable for large-scale promotion.

[0015] Additional aspects and advantages of the present invention will be given in part in the following description, and in part will become apparent from the following description, or will be learned through the practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 A schematic diagram of the structure of the flip-chip light-emitting diode provided by the utility model;

[0017] Figure 2 for Figure 1 Schematic diagram of the structure of the middle AA section;

[0018] Figure 3 for Figure 1 A schematic diagram of the partially enlarged structure at B in the middle;

[0019] Figure 4 for Figure 1 Schematic diagram of the partial enlarged structure at point C in the middle.

[0020] Description of main component symbols:

[0021] 10. Substrate; 111. N-type semiconductor layer; 112. Active light-emitting layer; 113. P-type semiconductor layer; 114. N-type semiconductor layer conductive step; 115. Isolation groove; 12. Current blocking layer; 13. Current spreading layer; 14. First conductive layer; 141. P-type first conductive layer; 142. N-type first conductive layer; 15. First insulating layer; 151. P-type first insulating layer through hole; 152. N-type first insulating layer through hole; 16. Second conductive layer; 161. P-type second conductive layer; 162. N-type second conductive layer; 17. Second insulating layer; 171. P-type second insulating layer through hole; 172. N-type second insulating layer through hole; 18. Pad layer; 181. P-type pad layer; 182. N-type pad layer.

[0022] The following specific implementation manner will further illustrate the present invention in conjunction with the above-mentioned drawings. DETAILED DESCRIPTION

[0023] In order to facilitate the understanding of the present invention, the present invention will be described more fully below with reference to the relevant drawings. Several embodiments of the present invention are given in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present invention more thorough and comprehensive.

[0024] It should be noted that when an element is referred to as being "fixed to" another element, it may be directly on the other element or there may be a central element. When an element is considered to be "connected to" another element, it may be directly connected to the other element or there may be a central element at the same time. The terms "vertical", "horizontal", "left", "right" and similar expressions used herein are for illustrative purposes only.

[0025] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art in the technical field of the present invention. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more related listed items.

[0026] Specifically, Figures 1 to 4 As shown, the flip-chip light-emitting diode provided by the utility model includes a substrate and an epitaxial wafer deposited on the substrate; the epitaxial wafer includes an N-type semiconductor layer, a first conductive layer, a first insulating layer, a second conductive layer, and a second insulating layer, a first insulating layer through hole is opened in the first insulating layer, a portion of the first conductive layer is arranged in the first insulating layer through hole, portions of the first conductive layer and the second conductive layer are isolated by the first insulating layer, a second insulating layer through hole is arranged on the second insulating layer, a pad layer is deposited in the second insulating layer through hole, a portion of the second conductive layer is located below the pad layer and is electrically connected thereto, center lines of the first insulating layer through hole and the second insulating layer through hole do not overlap, a width of the second insulating layer through hole gradually decreases from the center to both ends, a length d of the second insulating layer through hole is greater than a minimum distance d1 between the end of the second insulating layer through hole and the first conductive layer, so that the current injected through the pad layer propagates laterally after passing through the second conductive layer, and then is transmitted to the first conductive layer through the first insulating layer through hole, thereby improving the EOS resistance capability of the flip-chip LED chip.

[0027] Specifically, the steps of preparing the flip-chip light-emitting diode include:

[0028] Step 1: first provide a substrate 10, and then sequentially deposit an N-type semiconductor layer 111, an active light-emitting layer 112, and a P-type semiconductor layer 113 on the substrate by using a MOCVD process. The substrate may be one of GaN, Al2O3, and Si;

[0029] Step 2: Next, a photoresist is coated on the surface of the P-type semiconductor layer, and then a part of the photoresist is removed by exposure and development process to expose a part of the P-type semiconductor layer 113, and then an inductively coupled plasma etching process is used to remove the exposed P-type semiconductor layer and the active light-emitting layer 112 under the part of the P-type semiconductor to form an N-type semiconductor layer conductive step 114, and then the photoresist is removed;

[0030] Step 3: Then, a photoresist is coated on the surface of the P-type semiconductor layer 113 and the surface of the N-type semiconductor layer conductive step 114, and then a portion of the photoresist is removed by exposure and development to expose a portion of the N-type semiconductor layer 111 conductive step located at the edge of the chip, and then the exposed N-type semiconductor layer 111 conductive step is removed by an inductively coupled plasma etching process to form an isolation groove 115, and then the photoresist is removed;

[0031] Step 4: Next, SiO2 or SiN is deposited on the surface of the P-type semiconductor layer 113, the N-type semiconductor layer conductive step 114 and the isolation groove 115 by using a PECVD (plasma chemical vapor deposition) process, and then a photoresist is coated on the surface of the SiO2 or SiN, and then a part of the photoresist is removed by an exposure and development process to expose a part of the SiO2 or SiN, and then a BOE etching solution is used to remove the exposed SiO2 or SiN, and then the remaining photoresist is removed to form a current blocking layer 12;

[0032] Step 5: Next, indium tin oxide is deposited on the surface of the P-type semiconductor layer 113, the N-type semiconductor layer conductive step 114, the isolation groove 115 and the current blocking layer 12 by using a magnetron sputtering process; then, photoresist is coated on the surface of the indium tin oxide, and then part of the photoresist is removed by exposure and development to expose part of the indium tin oxide, and then the exposed indium tin oxide is removed by an indium tin oxide etching solution, and then the photoresist is removed to form the current spreading layer 13;

[0033] Step 6: Then, photoresist is coated on the current spreading layer 13 and the area not covered by the current spreading layer 13, and then part of the photoresist is removed by exposure and development, and then Cr / Al / Ti / Pt / Ti / Pt / Au / Pt / Ti metals are sequentially evaporated by electron beam evaporation process, and then the metal located on the photoresist is removed by blue film stripping process, and then the photoresist is removed to form a first conductive layer 14, wherein the first conductive layer includes a plurality of conductive disks, wherein some of the conductive disks are N-type first conductive layers 142, and some are P-type first conductive layers 141; the plurality of N-type first conductive layers 142 are all located on the N-type semiconductor layer conductive step 114, and the plurality of P-type first conductive layers are all located on the current spreading layer 13;

[0034] Step 7: Then, 20-40 groups of SiO2 and TiO2 stacks are sequentially deposited on the P-type first conductive layer 141, the N-type first conductive layer 142, the current spreading layer 13 and the area covered by the current spreading layer by electron beam evaporation process to form a first insulating layer 15, which also acts as a Bragg reflection layer to reflect the light emitted from the epitaxial layer and emit it from the substrate surface, thereby improving the luminous efficiency of the flip-chip light-emitting diode chip; then, photoresist is coated on the surface of the first insulating layer 15, and then part of the photoresist is removed by exposure and development to expose part of the first insulating layer, and then the exposed first insulating layer is removed by inductively coupled plasma etching process, and then the photoresist is removed to form first insulating layer through holes, wherein the first insulating layer through holes include a plurality of N-type first insulating layer through holes 152 and a plurality of P-type first insulating layer through holes 151, and the P-type first insulating layer through holes 151 are all placed on the P-type first conductive layer 141;

[0035] Step eight: Next, a photoresist is coated on the surface of the first insulating layer, and then a part of the photoresist is removed by exposure and development, and then Al / Ti / Al / Ti / Pt / Ti / Pt / Ti metals are sequentially evaporated by electron beam evaporation process, and then the metal on the photoresist is removed by blue film stripping process, and then the photoresist is removed to form a second conductive layer 16, wherein the second conductive layer 16 includes an N-type second conductive layer 162 and a P-type second conductive layer 161; the N-type second conductive layer 162 is electrically connected to the multiple N-type first conductive layers 142 through the multiple N-type first insulating layer through holes 152; the P-type second conductive layer 161 is electrically connected to the multiple P-type first conductive layers 141 through the multiple P-type first insulating layer through holes 151;

[0036] Step nine: Next, SiO2 is deposited as the second insulating layer 17 on the surface of the second conductive layer 16 and the area not covered by the second conductive layer 16 by using a PECVD process, and then a photoresist is coated on the surface of the second insulating layer 17, and then a part of the photoresist is removed by exposure and development to expose a part of the second insulating layer, and then the exposed second insulating layer is removed by an inductively coupled plasma etching process, and then the photoresist is removed to form a second insulating layer through hole, wherein the second insulating layer through hole includes an N-type second insulating layer through hole 172 and a P-type second insulating layer through hole 171;

[0037] Step 10: Next, a photoresist is coated on the surface of the second insulating layer and the through hole of the second insulating layer, and then a part of the photoresist is removed by exposure and development, and then Al / Ti / Pt / Ti / Ni / Au metals are sequentially evaporated by electron beam evaporation process, and then the metal on the photoresist is removed by blue film stripping process, and then the photoresist is removed to form a pad layer, wherein the pad layer includes a P-type pad layer 181 and an N-type pad layer 182; the P-type pad layer 181 is electrically connected to the P-type second conductive layer through the through hole of the P-type second insulating layer; the N-type pad layer 182 is electrically connected to the N-type second conductive layer through the through hole of the N-type second insulating layer;

[0038] In this embodiment, if Figure 2 As shown, the projection center of any second insulating layer through hole coincides with the center of the line connecting two adjacent conductive disks, that is, the N-type second insulating layer through hole 172 is located between the two disk-shaped N-type first conductive layers 142, and the P-type second insulating layer through hole 171 is located between the two disk-shaped P-type first conductive layers 141; further, as Figure 3 and Figure 4 As shown, schematically, the second insulating layer through hole is described by taking the N-type second insulating layer through hole 172 as an example; the center width of the second insulating layer through hole is L, and the end width is L1, wherein 0.1L≤L1≤0.5L. The length of the second insulating layer through hole is d, and the minimum distance d1 between the end of the second insulating layer through hole and the first conductive layer is d1, d1≤d≤2d1, wherein d1≥0.15um; further, the second conductive layer includes an N-type second conductive layer 162 and a P-type second conductive layer 161, and the distance between the N-type second conductive layer 162 and the P-type second conductive layer 161 is L3, and the distance from the edge of the second insulating layer through hole closest to the N-type second conductive layer 162 to the edge of the N-type second conductive layer is L2, wherein L3≤L2≤L, wherein L3>10um.

[0039] In summary, the flip-chip light-emitting diode provided in this embodiment includes a substrate, an epitaxial wafer deposited on the substrate, the epitaxial wafer includes an N-type semiconductor layer, a first conductive layer, a first insulating layer, a second conductive layer, and a second insulating layer. A second insulating through hole is arranged on the second insulating layer, the second insulating through hole is not in the pad layer, the first conductive layer and part of the lateral part of the second conductive layer are separated by the first insulating layer, the width of the second insulating layer through hole gradually decreases from the center to both ends, and the length d of the second insulating layer through hole is greater than the minimum distance d1 between the end of the second insulating layer through hole and the first conductive layer, so that the large current injected through the pad layer propagates laterally after passing through the second conductive layer, and then is transmitted to the first conductive layer through the first insulating layer through hole; the EOS resistance ability of the flip-chip LED chip is improved, and it is suitable for large-scale promotion.

[0040] It should be noted that the above implementation process is only to illustrate the feasibility of the present application, but this does not mean that the flip-chip light emitting diode of the present application is only implemented as above. On the contrary, as long as the flip-chip light emitting diode of the present application can be implemented, it can be included in the feasible implementation scheme of the present application.

[0041] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, mechanisms, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the utility model. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, mechanisms, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0042] The above embodiments only express several implementation methods of the utility model, and the descriptions are relatively specific and detailed, but they cannot be understood as limiting the scope of the utility model patent. It should be pointed out that for ordinary technicians in this field, several modifications and improvements can be made without departing from the concept of the utility model, which all belong to the protection scope of the utility model. Therefore, the protection scope of the utility model patent shall be based on the attached claims.

Claims

1. A flip-chip light emitting diode, characterized in that: The invention comprises a substrate and an epitaxial wafer deposited on the substrate, wherein the epitaxial wafer comprises a first conductive layer, a first insulating layer, a second conductive layer and a second insulating layer, wherein a first insulating layer through hole is opened in the first insulating layer, a portion of the first conductive layer is arranged in the first insulating layer through hole, the first conductive layer and a portion of the second conductive layer are isolated by the first insulating layer, a second insulating layer through hole is arranged on the second insulating layer, a pad layer is deposited in the second insulating layer through hole, a portion of the second conductive layer is located below the pad layer and is electrically connected thereto, the center lines of the first insulating layer through hole and the second insulating layer through hole do not coincide, the width of the second insulating layer through hole gradually decreases from the center to both ends, the length d of the second insulating layer through hole is greater than the minimum distance d1 between the end of the second insulating layer through hole and the first conductive layer, so that the current injected through the pad layer propagates laterally after passing through the second conductive layer, and then is vertically transmitted into the first conductive layer through the first insulating layer through hole.

2. The flip-chip light emitting diode according to claim 1, characterized in that: The epitaxial wafer also includes an N-type semiconductor layer, an active light-emitting layer, and a P-type semiconductor layer sequentially deposited on the substrate. The epitaxial wafer includes an N-type conductive region and a P-type conductive region that are electrically connected. A plurality of N-type semiconductor layer conductive steps are discontinuously etched on the N-type conductive region. The bottom of the N-type semiconductor layer conductive steps is connected to the N-type semiconductor layer. A plurality of current blocking layers are discontinuously provided on the P-type conductive region. The current blocking layers are deposited on the P-type semiconductor layer.

3. The flip-chip light emitting diode according to claim 2, characterized in that: The first conductive layer includes an N-type first conductive layer, the second conductive layer includes an N-type second conductive layer, the first insulating layer through hole includes an N-type first insulating layer through hole, the N-type first conductive layer is arranged in the N-type first insulating layer through hole, the top of the N-type first conductive layer is connected to the N-type second conductive layer, and the other areas of the N-type conductive area protruding from the N-type first insulating layer through hole are sequentially deposited with the first insulating layer, the N-type second conductive layer, and the second insulating layer.

4. The flip-chip light emitting diode according to claim 3, characterized in that: The second insulating layer through hole comprises an N-type second insulating layer through hole, the pad layer comprises an N-type pad layer, the N-type second insulating layer through hole is located above the N-type second conductive layer, and an N-type pad layer is disposed in the N-type second insulating layer through hole.

5. The flip-chip light emitting diode according to claim 2, characterized in that: The first conductive layer also includes a P-type first conductive layer, the second conductive layer also includes a P-type second conductive layer, the first insulating layer through hole also includes a P-type first insulating layer through hole, the P-type first conductive layer is arranged in the P-type first insulating layer through hole, the top of the P-type first conductive layer is connected to the P-type second conductive layer, and the other areas of the P-type conductive area protruding out of the P-type first insulating layer through hole are sequentially deposited with a first insulating layer, a P-type second conductive layer, and a second insulating layer.

6. The flip-chip light emitting diode according to claim 5, characterized in that: The second insulating layer through hole includes a P-type second insulating layer through hole, the pad layer includes a P-type pad layer, the P-type second insulating layer through hole is located above the P-type second conductive layer, and a P-type pad layer is disposed in the P-type second insulating layer through hole.

7. The flip-chip light emitting diode according to claim 5, characterized in that: A current spreading layer is provided between the current blocking layer and the P-type first conductive layer.

8. The flip-chip light emitting diode according to claim 1, characterized in that: An isolation groove extending to the substrate is etched at the edge of the epitaxial wafer.

9. The flip-chip light emitting diode according to claim 1, characterized in that: d1≤d≤2d1, wherein d1≥0.15um, the center width of the through hole of the second insulating layer is L, and the end width is L1, wherein 0.1L≤L1≤0.5L.

Images