Integrated chip

Abstract

The utility model provides an integrated chip. The integrated chip comprises a semiconductor substrate having a first side and a second side opposite to the first side. The first transistor and the second transistor are along a first side of the semiconductor substrate. A dielectric structure including a plurality of dielectric layers is under the first side of the semiconductor substrate. The first metal line is within the dielectric structure. The second metal line is within the dielectric structure and underneath the first metal line. A first metal via extends between the first metal line and the second metal line. A through-substrate via extends from the second side of the semiconductor substrate through the semiconductor substrate between the first transistor and the second transistor to the first metal line and the second metal line.

Description

Technical Field

[0001] The embodiment of the utility model relates to an integrated chip. Background Art

[0002] Modern integrated chips contain billions or trillions of semiconductor devices. The semiconductor devices are electrically interconnected through back-end process metal interconnect layers formed on the lines above the devices on the integrated chip. A typical integrated chip includes multiple back-end process metal interconnect layers embedded in a dielectric material. The metal interconnect layers contain corresponding multi-layer metal lines vertically coupled together by metal vias. The size of the metal interconnect layers increases from fine metal lines connected to the devices to thick metal lines connected to the external components of the chip. Utility Model Content

[0003] In some embodiments, the utility model relates to an integrated chip, which includes a semiconductor substrate having a first side and a second side opposite to the first side. A first transistor and a second transistor are along the first side of the semiconductor substrate. A dielectric structure including a plurality of dielectric layers is below the first side of the semiconductor substrate. A first metal line is within the dielectric structure. A second metal line is within the dielectric structure and below the first metal line. A first metal via extends between the first metal line and the second metal line. A through substrate via (TSV) extends from the second side of the semiconductor substrate, through the semiconductor substrate between the first transistor and the second transistor, and reaches the first metal line and the second metal line.

[0004] In another embodiment, the utility model relates to an integrated chip, which includes a semiconductor substrate having a first side and a second side opposite to the first side. A first transistor and a second transistor are arranged along the first side of the semiconductor substrate. A shallow trench isolation (STI) layer is between the first transistor and the second transistor. The STI layer extends into the semiconductor substrate along the first side of the semiconductor substrate. A dielectric structure including a plurality of dielectric layers is below the first side of the semiconductor substrate. A subsequent structure is within the dielectric structure. The subsequent structure includes a first metal line within the dielectric structure. The first metal line extends along a first direction. The subsequent structure includes a second metal line within the dielectric structure and laterally separated from the first metal line. The second metal line extends along the first direction. The subsequent structure includes a third metal line within the dielectric structure and below the first metal line and the second metal line. The third metal line extends along a second direction different from the first direction. A first metal via is within the dielectric structure and extends from the first metal line to the third metal line. A second metal via is within the dielectric structure and extends from the second metal line to the third metal line. A through substrate via (TSV) extends laterally from the first metal line to the second metal line, vertically between the first metal line and the second metal line to the third metal line, and extends from the first metal line, the second metal line, and the third metal line, through the semiconductor substrate and the STI layer, to the second side of the semiconductor substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] When the following detailed description is read in conjunction with the attached drawings, aspects of the present invention will be best understood. It is worth noting that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, for the sake of clarity of discussion, the size of the various features may be arbitrarily increased or decreased.

[0006] Figure 1 Some embodiments of an integrated chip including a multi-layer bonding structure and a through-substrate via (TSV) on the bonding structure are shown in cross-sectional views.

[0007] Figure 2 Shows Figure 1 A top view of some embodiments of the subsequent structure of the integrated chip.

[0008] Figure 3 and Figure 4 Shows Figure 1 and Figure 2 Top views of some embodiments of the bonding structure.

[0009] Figures 5 to 8 Shows Figure 3 and Figure 4 Cross-sectional views of some embodiments of an integrated chip including a subsequent structure.

[0010] Fig. 9 Shows Figure 4 Top views of some other embodiments of the following structure.

[0011] Fig.10 Shows Figure 5 The following structure and cross-sectional views of some other embodiments of TSV.

[0012] Fig.11 Shows Figure 1 and Figure 2 Top views of some embodiments of the bonding structure.

[0013] Figures 12 to 16 Shows Fig.11 Cross-sectional views of some embodiments of integrated chips including subsequent structures.

[0014] Fig.17 Shows Fig.16 The following structure and cross-sectional views of some other embodiments of TSV.

[0015] Figures 18 to 26 Cross-sectional views of some embodiments of methods for forming an integrated chip including a multi-layer bonding structure and TSVs on the bonding structure are shown.

[0016] Figures 27 to 35 Cross-sectional views of some other embodiments of methods for forming an integrated chip including a multi-layer bonding structure and TSVs on the bonding structure are shown.

[0017] Fig.36 A flow chart illustrating some embodiments of a method for forming an integrated chip including a bonding structure and TSVs on the bonding structure. DETAILED DESCRIPTION

[0018] The following disclosure provides several different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not restrictive. For example, the formation of a first feature on or above a second feature in the following description may include an embodiment in which the first and second features are formed in direct contact, and may also include an embodiment in which additional features may be formed between the first and second features so that the first and second features may not be in direct contact. In addition, the present invention may repeat reference numbers or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not itself dictate the relationship between the various embodiments or architectures discussed.

[0019] Additionally, for ease of description, spatially relative terms, such as "below," "under," "beneath," "above," "over," and the like, may be used herein to describe the relationship of one element or feature to another element or feature, as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptive terms used herein may likewise be interpreted accordingly.

[0020] The integrated chip includes a transistor device arranged along a first side of a semiconductor substrate. A dielectric structure is below the first side of the semiconductor substrate. A metal bonding pad is within the dielectric structure. A metal line is below the metal bonding pad. A metal through hole extends from the metal bonding pad to the metal line. A through substrate via (TSV) extends from a second side of the semiconductor substrate opposite to the first side through the semiconductor substrate to the metal bonding pad. The TSV contacts the metal bonding pad and is separated from the second metal line.

[0021] As technology advances, metal interconnects (e.g., metal lines and metal pads) are becoming thinner. Therefore, in some chips, the metal pads have a reduced thickness. In such devices, it may be challenging to form TSVs on the metal pads without damaging and / or deforming the metal pads. For example, forming TSVs on the metal pads may apply stress to the metal pads. When the metal pads have a reduced thickness, the likelihood that the metal pads will be damaged (e.g., cracked, etc.) due to stress increases.

[0022] In addition, as technology advances, dielectric structures are increasingly formed of dielectrics with lower dielectric constants, such as extra low k (ELK) dielectrics. Therefore, in some chips, dielectric structures and TSVs surrounding metal pads include ELK dielectrics. These ELK dielectrics may be more fragile and more susceptible to moisture absorption than other dielectrics. Therefore, when the dielectric structure includes ELK dielectrics, the reliability of the dielectric structure and TSVs around the pads may be a concern.

[0023] In various embodiments of the present invention, the integrated chip includes a multi-layer mesh connection structure for TSV. The integrated chip includes a first metal line and a second metal line in a dielectric structure. The second metal line is located below the first metal line. In the mesh arrangement, the first metal line extends in a first direction, and the second metal line extends in a second direction (e.g., perpendicular to the first direction). The first metal line and the second metal line form a multi-layer mesh connection structure. The TSV extends from the second side through the semiconductor substrate to the first metal line and the second metal line.

[0024] Because the connecting structure includes a plurality of connecting layers (e.g., a first metal line and a second metal line below the first metal line) arranged in a mesh manner (e.g., a first metal line extending in a first direction and a second metal line extending in a second direction), the stress applied to the connecting structure by the TSV can be dispersed over the plurality of layers. Therefore, the stress acting on the individual layers can be reduced. In this way, the possibility of the connecting structure being damaged due to the formation of the TSV can be reduced.

[0025] In some embodiments, the integrated chip also includes a metal guard ring structure surrounding the TSV and the subsequent structure to alleviate concerns about the reliability of the dielectric surrounding the TSV and the subsequent structure. For example, a plurality of interconnected metal lines, metal vias, and metal gates surround the TSV and the subsequent structure in a closed path surrounding the periphery of the subsequent structure. The guard ring structure can protect the dielectric around the TSV and the subsequent structure from potential harmful elements such as moisture. Therefore, the reliability of the dielectric can be improved.

[0026] Figure 1A cross-sectional view 100 of some embodiments of an integrated chip including a multi-layer bonding structure 180 and TSVs 172 on the bonding structure 180 is shown. Figure 2 Shows Figure 1 A top view 200 of some embodiments of the integrated chip structure 180 is shown.

[0027] The integrated chip includes a semiconductor substrate 102 having a front side 102a and a back side 102b. A first transistor device 104 is arranged along the front side 102a of the substrate 102. A second transistor device 106 is arranged along the front side 102a of the substrate 102 and is laterally separated from the first transistor device 104. In some embodiments, the transistor devices 104, 106 include a pair of source / drain electrodes (e.g., source / drain electrodes 108) and a gate electrode (e.g., gate electrode 110) extending between the source / drain electrodes. Depending on the context, the source / drain electrodes may be considered as a source or a drain electrode alone or together. In some embodiments, the gate electrodes (e.g., gate electrode 110) of the transistor devices 104, 106 include metal.

[0028] A shallow trench isolation (STI) layer 112 is between the first transistor device 104 and the second transistor device 106. The STI layer 112 extends into the substrate 102 along the front side 102a of the substrate 102. A dielectric structure 114 is located below the substrate 102 (eg, on the front side 102a of the substrate 102). The dielectric structure 114 includes a plurality of dielectric layers.

[0029] A plurality of metal lines are within the dielectric structure 114. For example, a plurality of metal lines 182 (e.g., metal lines 116, 118, 120, 122, 124, 126, 202, 204, 206, 208) are within the dielectric structure 114 and are laterally spaced apart along the front side 102a of the substrate 102. Some of the first plurality of metal lines 182 contact the transistor devices 104, 106, and some of the first plurality of metal lines 182 are laterally arranged between the transistor devices 104, 106. For example, the metal line 124 contacts the first transistor device 104, and the metal line 126 contacts the second transistor device 106. The metal lines 116, 118, 120, 122 are directly between the gates of the transistor devices 104, 106.

[0030] A second plurality of metal lines 186 (e.g., metal lines 130, 132, 134, 210) are below the first plurality of metal lines 182. The second plurality of metal lines 186 are disposed at a first height 128 from the front side 102a of the substrate 102. A third plurality of metal lines 190 (e.g., metal lines 138, 140, 142, 212) are below the second plurality of metal lines 186. The third plurality of metal lines 190 are disposed at a second height 136 from the front side 102a of the substrate 102, the second height 136 being greater than the first height 128. A fourth plurality of metal lines 194 (e.g., metal lines 146, 148, 150, 214) are below the third plurality of metal lines 190. The fourth plurality of metal lines 194 are disposed at a third height 144 from the front side 102a of the substrate 102, the third height 144 being greater than the second height 136.

[0031] The metal vias extend vertically between the metal lines. For example, a first plurality of metal vias 184 (e.g., metal vias 152, 154, 156) extend from the first plurality of metal lines 182 to the second plurality of metal lines 186. A second plurality of metal vias 188 (e.g., metal vias 158, 160, 162) extend from the second plurality of metal lines 186 to the third plurality of metal lines 190. A third plurality of metal vias 192 (e.g., metal vias 164, 166, 168) extend from the third plurality of metal lines 190 to the fourth plurality of metal lines 194.

[0032] The dielectric liner 170 extends through the substrate along the sidewalls 112a of the STI layer 112 and the sidewalls 102c of the substrate 102. The dielectric liner 170 further extends along the backside 102b of the substrate 102. The TSV 172 extends along the sidewalls 170a of the dielectric liner 170, through the substrate 102 and through the STI layer 112, from the backside 102b through the frontside 102a.

[0033] The metal lines (e.g., metal lines 116, 118, 120, 122, 130, 138, 146) directly below the TSV 172 form a multi-layer mesh structure 180 of the TSV 172. For example, the metal lines 116, 118, 120, 122, 202, 204, 206, 208 extend in a first direction 101y. The metal lines 130, 210 extend in a second direction 101x that is different from (e.g., perpendicular to) the first direction 101y. The metal lines 138, 212 extend in the first direction 101y and are laterally offset from (e.g., laterally between) the metal lines 116, 118, 120, 122, 202, 204, 206. The metal lines 146, 214 extend in the second direction 101x and are laterally offset from (e.g., laterally between) the metal lines 130, 210.

[0034] Metal line 130 extends from directly under metal line 116 to directly under metal line 118. Metal line 138 extends directly under metal line 130 and laterally between metal line 116 and metal line 118. Metal line 146 extends directly under metal line 138, extends parallel to metal line 130, and extends from directly under metal line 116 to directly under metal line 118.

[0035] TSV 172 is located on a metal line following structure 180. For example, in some embodiments, TSV 172 is on metal line 116 and metal line 118. TSV 172 extends directly between the sidewalls of metal line 116 and metal line 118 to metal line 126. In some embodiments, TSV 172 is on metal line 130, metal line 138, and metal line 146. From a cross-sectional view, TSV 172 has a multi-stage profile.

[0036] Since the connection structure 180 includes a plurality of connection layers (e.g., a first plurality of metal lines 182, a second plurality of metal lines 186, a third plurality of metal lines 190, and a fourth plurality of metal lines 194) arranged in a mesh manner, the stress applied to the connection structure 180 by the TSV 172 can be dispersed over the plurality of layers and in a plurality of directions. Therefore, the stress acting on the respective layers of the connection structure 180 can be mitigated. In this way, the possibility of the connection structure 180 being damaged due to the stress generated by the TSV 172 can be reduced.

[0037] In some embodiments, TSV 172 defines a trench 174 filled with air or the like. For example, sidewalls 172 a of TSV 172 and upper surface 172 b of TSV 172 define trench 174. In some other embodiments, a dielectric layer, a passivation layer, or some other suitable layer is directly above upper surface 172 b and directly between sidewalls 172 a of TSV 172 and fills trench 174. Metal bumps 176 (e.g., solder bumps, etc.) are located on the top surface of TSV 172.

[0038] The guard ring structure 178 surrounds the TSV 172 and the subsequent structure 180. The guard ring structure 178 is formed by the metal gate (e.g., gate 110) of the transistor device (e.g., the first transistor device 104 and the second transistor device 106) surrounding the TSV 172, the metal line (e.g., metal line 124, 126, 132, 134, 140, 142, 148, 150) surrounding the TSV, and the metal via (e.g., metal via 154, 156, 160, 162, 166, 168) surrounding the TSV 172. The metal gate, metal line, and metal via of the guard ring structure 178 collectively surround the subsequent structure 180 and the TSV 172 in a closed path. The guard ring structure 178 can protect the portion of the dielectric structure 114 surrounding the TSV 172 and the subsequent structure 180. Therefore, the reliability of the dielectric structure 114 around the TSV 172 and the subsequent structure 180 can be improved.

[0039] Figure 3 and Figure 4 Shows Figure 1 and Figure 2 The top view 300 and the top view 400 of some embodiments of the bonding structure 180 are shown, wherein the metal lines in the first plurality of metal lines 182 and the metal lines 130 in the second plurality of metal lines 186 form a multi-layer mesh bonding structure 180. More specifically, Figure 3 Metal line 130 is shown following structure 180, and Figure 4 Metal lines 116 , 118 , 120 , 122 are also shown following structure 180 .

[0040] Figures 5 to 8 Shows Figure 3 and Figure 4 500 to 800 of some embodiments of an integrated chip including the structure 180. In some embodiments, Figure 5 The cross-sectional view 500 can be taken, for example, from across Figure 4 In some embodiments, Figure 6 The cross-sectional view 600 can be taken, for example, from across Figure 4 In some embodiments, Figure 7 The cross-sectional view 700 can be taken, for example, from across Figure 4 In some embodiments, Figure 8 The cross-sectional view 800 can be taken, for example, from across Figure 4 The line D-D'.

[0041] refer to Figures 3 to 8, then the structure 180 is formed by the metal lines 116, 118, 120, 122, 408, 410, 412, 414 in the first plurality of metal lines 182 and the metal line 130 in the second plurality of metal lines 186. The metal line 130 extends in the first direction 101y and the second direction 101x. For example, the metal line 130 includes a first segment 302 extending in the first direction 101y and a second segment 304 extending in the second direction 101x. The first segment 302 intersects with the second segment 304 to form a mesh arrangement. The metal line 130 is directly below the metal lines 116, 118, 120, 122, 408, 410, 412, 414.

[0042] The metal lines 116, 118, 120, 122, 408, 410, 412, 414 extend in a first direction and are laterally offset from (e.g., laterally between) the first segment 302 of the metal line 130. The metal vias 152, 402, 404, 406 extend between the metal lines 116, 118, 120, 122 and the metal line 130. The TSVs 172 are on the metal lines 116, 118, 120, 122 and the metal line 130. The TSVs extend between the metal lines 116, 118, 120, 122, 408, 410, 412, 414 and the metal line 130. The bottommost surface of the TSVs 172 is located on the top surface of the metal line 130.

[0043] In some embodiments, first plurality of metal lines 182 is thicker and includes a harder metal than metal lines in second plurality of metal lines 186, third plurality of metal lines 190, or fourth plurality of metal lines 194. For example, in some embodiments, first plurality of metal lines 182 includes a first metal (e.g., tungsten or some other suitable material), and second plurality of metal lines 186, third plurality of metal lines 190, and fourth plurality of metal lines 194 include a second metal (e.g., copper or some other suitable material) that is softer than the first metal. Because first plurality of metal lines 182 is thicker and includes a harder metal, the first plurality of metal lines can better withstand stress from TSVs 172. Thus, by including metal lines of first plurality of metal lines 182 (e.g., metal lines 116, 118, 120, 122) in follow-up structure 180, follow-up structure 180 can be improved.

[0044] Dielectric structure 114 includes a plurality of dielectric layers 502, 504, 506, 508, 510. Metal line 512 is below fourth plurality of metal lines 194. Metal via 514 extends from metal line 146 to metal line 512. In some embodiments, TSV 172 is coupled to metal line 512. In some embodiments, dielectric layers 504, 506, 508 include ELK dielectric (e.g., Si-OCH dielectric, etc.) or some other suitable material. Figures 5 to 8 As shown, the guard ring structure 178 surrounds the portion of the dielectric layers 504, 506, 508 around the TSV 172 and the subsequent structure 180 to protect the dielectric layers 504, 506, 508 around the TSV 172 and the subsequent structure 180. Figure 3 and Figure 4 The guard ring structure 178 is not shown in the figure, but it should be understood that the guard ring structure 178 surrounds Figure 3 and Figure 4 The next structure 180 shown in FIG. Figure 1 ).

[0045] Fig. 9 Shows Figure 4 A top view 900 of some and embodiments of the structure 180 is shown.

[0046] The metal lines 116, 118, 120, 122 are offset from each other in an alternating manner in the first direction 101y. In addition, the metal line 130 has a mesh pattern extending between the metal lines 116, 118, 120, 122. Fig. 9 1 is shown as partially transparent so that the metal line 130 can be seen.

[0047] Fig.10 Shows Figure 5 A cross-sectional view 1000 of some other embodiments of the structure 180 and TSV 172 is shown.

[0048] In some embodiments, the dielectric liner 170 extends laterally on the top surface of the metal line 130. The sidewall 170b of the dielectric liner 170 is directly above the metal line 130. The upper surface 170c of the dielectric liner 170 is directly above the metal line 130.

[0049] In some embodiments, dielectric liner 170 extends below top surfaces 116a, 118a, 120a, 122a of metal lines 116, 118, 120, 122, and below top surface 502a of dielectric layer 502. Dielectric liner 170 is on sidewalls 122b of metal line 122, on sidewalls 502b of dielectric layer 502, and on upper surface 502c of dielectric layer 502. In some embodiments, TSV 172 extends directly between sidewalls 116c of metal line 116 and sidewalls 170d of dielectric liner 170.

[0050] Dielectric layer 502 is directly between the sidewalls of TSV 172 and the sidewalls of metal vias 152, 402, 404, 406. In some embodiments, the width of TSV 172 decreases with the depth of TSV 172. Dielectric layer 502 is directly between sidewall 172c of TSV 172 and sidewall 116b of metal line 116.

[0051] Fig.11 Shows Figure 1 and Figure 2 A top view 1100 of some embodiments of the bonding structure 180 is shown, wherein the metal lines of the second plurality of metal lines 186 , the third plurality of metal lines 190 , and the fourth plurality of metal lines 194 form a multi-layer mesh bonding structure 180 . Figures 12 to 16 Shows Fig.11 1200 to 1600 of some embodiments of an integrated chip including the following structure. In some embodiments, Fig.12 The cross-sectional view 1200 can be taken, for example, from across Fig.11 In some embodiments, Fig.13 The cross-sectional view 1300 can be taken, for example, from across Fig.11 In some embodiments, Fig.14 The cross-sectional view 1400 can be taken, for example, from across Fig.11 In some embodiments, Fig.15 The cross-sectional view 1500 can be taken, for example, from across Fig.11 In some embodiments, Fig.16 The cross-sectional view 1600 can be taken, for example, from across Fig.11 The line J-J'.

[0052] refer to Figures 11 to 16, then structure 180 is formed by metal lines of a second plurality of metal lines 186 (e.g., metal lines 130, 1102, 1104), metal lines of a third plurality of metal lines 190 (e.g., metal lines 138, 1106, 1108), and metal lines of a fourth plurality of metal lines 194 (e.g., metal lines 146, 1110). Metal lines 130, 1102, 1104 extend along a first direction 101y. Metal lines 138, 1106, 1108 extend along a second direction 101x. Metal lines 146, 1110 extend along the first direction and are laterally offset from (e.g., laterally between) metal lines 130, 1102, 1104. TSVs 172 are on metal lines 130, 1102, 1104, 138, 1106, 1108, 146, 1110. TSV 172 extends between metal lines 130, 1102, 1104 to metal lines 138, 1106, 1108, and between metal lines 138, 1106, 1108 to metal lines 146, 1110. Since the bonding structure 180 has an increased number of layers, the stress applied by the TSV on the bonding structure 180 can be more dispersed. Therefore, the bonding structure 180 can be improved.

[0053] The upper surface 172b of the TSV 172 defining the trench 174 is below the dielectric layer 502 and below the top surface of the dielectric layer 504. The dielectric liner 170 extends below the dielectric layer 502 and below the top surface of the dielectric layer 504.

[0054] Although the guard ring structure 178 is not Fig.11 However, it should be understood that the guard ring structure 178 surrounds Fig.11 The next structure 180 shown in FIG. Figure 1 ).

[0055] Fig.17 Shows Fig.16 A cross-sectional view 1700 of some other embodiments of TSV 172 and subsequent structure 180 is shown.

[0056] In some embodiments, dielectric liner 170 extends laterally over top surface 130a of metal line 130. Sidewall 170e and upper surface 170f of dielectric liner 170 are directly above metal line 130. In some embodiments, dielectric liner 170 extends below top surface 130a of metal line 130. Dielectric liner 170 is located on sidewall 130b of metal line 130. In some embodiments, dielectric layer 502 is directly between sidewall 130c of metal line 130 and sidewall 172d of TSV 172.

[0057] Figures 18 to 26Some embodiments of a method for forming an integrated chip including a multi-layered bonding structure 180 and TSVs 172 on the bonding structure 180 are illustrated in cross-sectional views 1800 to 2600 .

[0058] Figures 27 to 35 Some other embodiments of methods for forming an integrated chip including a multi-layer bonding structure 180 and TSVs 172 on the bonding structure 180 are shown in cross-sectional views 2700 to 3500 .

[0059] although Figures 18 to 26 and Figures 27 to 35 is described with respect to a method, but it should be understood that Figures 18 to 26 and Figures 27 to 35 The structure disclosed in is not limited to such a method, but can stand alone as a structure independent of the method.

[0060] like Fig.18 Sectional view 1800 and Fig. 27 As shown in the cross-sectional view 2700 of FIG. 1 , transistor devices 104, 106 and STI layer 112 are formed along the front side 102a of semiconductor substrate 102. In some embodiments, semiconductor substrate 102 includes silicon, silicon germanium, or some other suitable material. In some embodiments, transistor devices 104, 106 are or include bipolar junction transistors (BJT), metal-oxide-semiconductor field-effect transistors (MOSFET), junction field-effect transistors (JFET), fin field-effect transistors (FinFET), gate-all-around field-effect transistors (GAAFET), etc. In some embodiments, STI layer 112 includes silicon dioxide or some other suitable material.

[0061] like Fig.19 Sectional view 1900 and Fig.28 As shown in cross-sectional view 2800 of , a dielectric layer 502 and a first plurality of metal lines 182 are formed along the front side 102 a of the substrate 102 to partially form the follow structure 180 and the guard ring structure 178 .

[0062] Metal lines 124, 126 of first plurality of metal lines 182 are formed on (e.g., contacting) transistor devices 104, 106. In some embodiments, metal lines 116, 118, 120, 122 of first plurality of metal lines 182 are formed between transistor devices 104, 106 and directly above STI layer 112, such as Fig.19 as displayed.

[0063] In some embodiments, dielectric layer 502 includes silicon dioxide or some other suitable material. In some embodiments, dielectric layer 502 can be deposited by a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, or some other suitable process.

[0064] In some embodiments, the first plurality of metal lines 182 includes tungsten or some other suitable material. In some embodiments, the first plurality of metal lines 182 is formed by depositing a dielectric layer 502 over the front side 102a of the substrate 102, patterning the dielectric layer 502, and depositing (e.g., by a CVD process, a PVD process, an ALD process, or some other suitable process) a metal (e.g., tungsten or some other suitable material) over the patterned dielectric layer 502 to form the first plurality of metal lines 182. In some other embodiments, the first plurality of metal lines 182 is formed by depositing a metal over the front side 102a of the substrate 102, patterning the metal to form the first plurality of metal lines 182, and depositing a dielectric layer 502 over and between the first plurality of metal lines 182.

[0065] like Fig. 20 Sectional view 2000 and Fig.29 As shown in the cross-sectional view 2900, dielectric layers 504, 506, 508, 510, a second plurality of metal lines 186, a third plurality of metal lines 190, a fourth plurality of metal lines 194, a first plurality of metal vias 184, a second plurality of metal vias 188, a third plurality of metal vias 192, metal vias 514 and metal lines 512 are formed above the dielectric layer 502 and above the first plurality of metal lines 182 to further form a follower structure 180 and a guard ring structure 178.

[0066] In some embodiments, dielectric layers 504, 506, 508 include ELK dielectrics (e.g., Si-OCH dielectrics, etc.) or some other suitable materials deposited by a CVD process, a PVD process, an ALD process, or some other suitable process. In some embodiments, dielectric layer 510 includes a low-k dielectric (e.g., carbon-doped oxide, etc.) or some other suitable materials deposited by a CVD process, a PVD process, an ALD process, or some other suitable process.

[0067] In some embodiments, the second plurality of metal lines 186, the third plurality of metal lines 190, the fourth plurality of metal lines 194, the first plurality of metal vias 184, the second plurality of metal vias 188, the third plurality of metal vias 192, the metal vias 514 and / or the metal lines 512 include copper or some other suitable material deposited by a CVD process, a PVD process, an ALD process, or some other suitable process.

[0068] like Fig.21 Sectional view 2100 and Fig.30 As shown in the cross-sectional view 3000 of FIG. 3 , the back side 102 b of the substrate 102 opposite to the front side 102 a and the STI layer 112 are etched to form trenches (eg, Fig.21 The ditch 2102 or Fig.30 The etch (and trenches 2102, 3002) extends from the back side 102b through the substrate 102 to the front side 102a. In some embodiments, the etch extends to the dielectric layer 502, such as Fig.21 and Fig.30 In some embodiments, the extension further extends through dielectric layer 502 and into dielectric layer 504, as shown in FIG. Fig.30 as displayed.

[0069] In some embodiments, trench 2102 is defined by sidewalls of substrate 102, sidewalls in STI layer 112, sidewalls and upper surface of dielectric layer 502, and sidewalls and upper surface of metal lines of first plurality of metal lines 182. Fig.21 In some embodiments, trench 3002 is defined by sidewalls of substrate 102, sidewalls of STI layer 112, sidewalls of dielectric layer 502, and sidewalls and upper surfaces of metal lines of second plurality of metal lines 186, as shown in FIG. Fig.30 as displayed.

[0070] In some embodiments, etching includes a dry etching process (eg, a reactive ion etching process, a plasma etching process, an ion beam etching process, etc.) or some other suitable process. In some embodiments, a mask layer (eg, Fig.21 The mask layer 2104 or Fig.30 The mask layer 3004 is formed by etching the mask layers 2104 and 3004. In some embodiments, the mask layers 2104 and 3004 include a photoresist layer, a hard mask layer, or some other suitable layer.

[0071] like Fig. 22 Sectional view 2200 and Fig.31 As shown in the cross-sectional view 3100 of FIG. 31 , the dielectric liner 170 is deposited on the back side 102 b of the substrate 102 and the trenches 2102 and 3002, so that the dielectric liner 170 lines the back side 102 b of the substrate 102, the substrate 102 defines the sidewalls of the trenches 2102 and 3002, and the STI layer 112 defines the sidewalls of the trenches 2102 and 3002. In embodiments where the trenches 2102 and 3002 extend into the dielectric layer 502 or the dielectric layer 504, the dielectric liner 170 is further deposited on these layers.

[0072] In some embodiments, the dielectric liner 170 includes silicon dioxide, silicon nitride, or some other suitable material, and is deposited by a CVD process, a PVD process, an ALD process, or some other suitable process.

[0073] like Fig.23 Sectional view 2300 and Fig.32 As shown in the cross-sectional view 3200 of FIG. 3 , the dielectric liner 170 and the dielectric structure 114 (e.g., the dielectric layer 502 and / or the dielectric layer 504) are etched at the bottom of the trench 2102, 3002 to remove the dielectric liner 170 from the upper surface of the dielectric structure (e.g., the upper surface of the dielectric layer 502 or the upper surface of the dielectric layer 504), and the trench 2102, 3002 is extended. In some embodiments, the trench 2102 is extended to expose the metal line 130, such as Fig.23 In some embodiments, the extended trench 3002 exposes the metal lines of the third plurality of metal lines 190 and the fourth plurality of metal lines 194, such as Fig.32 as shown in the .

[0074] In some embodiments, the etch (and trench 2102) extends to a first depth (e.g., to metal line 130) below the front side 102a of the substrate 102. In some other embodiments, the etch (and trench 3002) extends to a second depth (e.g., to metal line 138) and a third depth (e.g., to metal line 146) below the front side 102a of the substrate 102.

[0075] In some embodiments, etching includes a dry etching process or some other suitable process. In some embodiments, a mask layer (e.g., Fig.23 The mask layer 2302 or Fig.32, and etching is performed according to the mask layers 2302 and 3202.

[0076] like Fig.24 Sectional view 2400 and Fig.33 As shown in the cross-sectional view 3300 of FIG. 1 , TSV 172 is formed over the back side 102 b of substrate 102 and in trenches 2102, 3002. TSV 172 partially fills trenches 2102, 3002. In some embodiments, TSV 172 is formed on metal lines of the first plurality of metal lines 182\ and metal lines 130 of the second plurality of metal lines 186. In some other embodiments, TSV 172 is formed on metal lines of the first plurality of metal lines 186, the second plurality of metal lines 190, and the third plurality of metal lines 194.

[0077] In some embodiments, forming the TSV 172 includes depositing a metal (e.g., copper or some other suitable material) or some other suitable material over the back side 102 b of the substrate 102 and over the trenches 2102, 3002 by a CVD process, a PVD process, an ALD process, or some other suitable process. In some embodiments, the remaining portion of the trenches 2102, 3002 is filled with air, etc. In some embodiments, a dielectric layer, a passivation layer, etc. are deposited over the TSV 172 to fill the remaining portion of the trenches 2102, 3002.

[0078] like Fig.25 Sectional view 2500 and Fig.34 As shown in the cross-sectional view 3400 of FIG. 1 , TSV 172 is etched to remove a portion of TSV 172 from above the back side 102b of substrate 102. The etching further defines TSV 172. In some embodiments, the etching includes a dry etching process or some other suitable process. In some embodiments, a mask layer (e.g., Fig.25 The mask layer 2502 or Fig.34 The mask layer 3402 is formed, and etching is performed according to the mask layers 2502 and 3402.

[0079] like Fig.26 Sectional view 2600 and Fig.35 As shown in cross-sectional view 3500 of FIG. 1 , metal bumps 176 are formed over TSV 172. In some embodiments, metal bumps 176 include solder, gold, or some other suitable material.

[0080] Fig.36A flow chart of some embodiments of a method 3600 for forming an integrated chip including a TSV on a structure and a structure is shown. Although method 3600 is shown and described below as a series of actions or events, it should be understood that the order in which these actions or events are shown should not be interpreted as limiting. For example, some actions may occur in a different order and / or occur simultaneously with other actions or events other than those shown and / or described herein. In addition, not all of the actions shown are necessary to implement one or more aspects or embodiments described herein. In addition, one or more actions described herein may be performed in one or more separate actions and / or stages.

[0081] At block 3602, a transistor is formed along a front side of a substrate. Some embodiments corresponding to block 3602, Fig.18 A cross-sectional view 1800 is shown, and Fig. 27 A cross-sectional view 2700 is shown.

[0082] At block 3604, a dielectric structure is formed over the front side of the substrate. Some embodiments corresponding to block 3604, Fig.19 A cross-sectional view 1900 is shown, and Fig.28 A cross-sectional view 2800 is shown.

[0083] At block 3606, a first metal line is formed within the dielectric structure. Some embodiments corresponding to block 3606, Fig. 20 A cross-sectional view 2000 is shown, and Fig.29 A cross-sectional view 2900 is shown.

[0084] At block 3608, a second metal line is formed within the dielectric structure and over the first metal line. The first metal line and the second metal line form a connection structure. Some embodiments corresponding to block 3608, Fig. 20 A cross-sectional view 2000 is shown, and Fig.29 A cross-sectional view 2900 is shown.

[0085] At block 3610, a guard ring structure including a plurality of metal lines, metal vias, and metal gates that surround the first metal line and the second metal line is formed. In some embodiments corresponding to block 3610, Fig. 20 A cross-sectional view 2000 is shown, and Fig.29 A cross-sectional view 2900 is shown.

[0086] At block 3612, the back side of the substrate is etched to form a trench in the substrate extending through the substrate. Some embodiments corresponding to block 3612, Fig.21 A cross-sectional view 2100 is shown, and Fig.30 A cross-sectional view 3000 is shown.

[0087] At block 3614, a dielectric liner is deposited over the back side of the substrate and in the trench. Some embodiments corresponding to block 3614, Fig. 22 A cross-sectional view 2200 is shown, and Fig.31 A cross-sectional view 3100 is shown.

[0088] At block 3616, the dielectric liner and dielectric structure at the bottom of the trench are etched to extend the trench into the dielectric structure to the first metal line and the second metal line. Some embodiments corresponding to block 3616, Fig.23 A cross-sectional view 2300 is shown, and Fig.32 A cross-sectional view 3200 is shown.

[0089] At block 3618, a through substrate via (TSV) is formed over the back side of the substrate and in the trench on the first metal line and the second metal line. Some embodiments corresponding to block 3618, Fig.24 A cross-sectional view 2400 is shown, and Fig.33 A cross-sectional view 3300 is shown.

[0090] At block 3620, the TSV is etched to remove a portion of the TSV from above the back side of the substrate. Some embodiments corresponding to block 3620, Fig.25 A cross-sectional view 2500 is shown, and Fig.34 A cross-sectional view 3400 is shown.

[0091] At block 3622, a metal bump is formed on the TSV. Some embodiments corresponding to block 3622, Fig.26 A cross-sectional view 2600 is shown, and Fig.35 A cross-sectional view 3500 is shown.

[0092] Therefore, the present invention relates to an integrated chip and a method for forming the integrated chip, wherein the integrated chip includes a multi-layer mesh bonding structure and TSVs on the bonding structure.

[0093] Therefore, in some embodiments, the utility model relates to an integrated chip, which includes a semiconductor substrate having a first side and a second side opposite to the first side. The first transistor and the second transistor are along the first side of the semiconductor substrate. A dielectric structure including a plurality of dielectric layers is below the first side of the semiconductor substrate. The first metal line is within the dielectric structure. The second metal line is within the dielectric structure and below the first metal line. The first metal via extends between the first metal line and the second metal line. A through substrate via (TSV) extends from the second side of the semiconductor substrate, through the semiconductor substrate between the first transistor and the second transistor, and reaches the first metal line and the second metal line. In some embodiments, the integrated chip also includes a metal guard ring structure, at least partially surrounding the first metal line, the second metal line and the substrate via. In some embodiments, the metal guard ring structure includes a plurality of metal lines, a plurality of metal vias and a plurality of metal gates within the dielectric structure, and the plurality of metal lines, the plurality of metal vias and the plurality of metal gates jointly surround the first metal line, the second metal line and the substrate via in a closed path. In some embodiments, the first metal line is directly located between the gate of the first transistor and the gate of the second transistor. In some embodiments, the integrated chip further comprises a third metal line within the dielectric structure and laterally separated from the first metal line, wherein the first metal line and the third metal line extend along a first direction, wherein the second metal line extends along the first direction and a second direction different from the first direction, wherein the second metal line is between the first metal line and the third metal line, and wherein the substrate via extends between the first metal line and the third metal line to the second metal line. In some embodiments, the first metal line and the third metal line comprise a first metal, and wherein the second metal line comprises a second metal different from the first metal. In some embodiments, the first metal line is separated from the first side of the semiconductor substrate, and the integrated chip further comprises: a third metal line within the dielectric structure and below the second metal line; and a second metal via extending between the second metal line and the third metal line, wherein the substrate via also extends to the third metal line. In some embodiments, the first metal line extends along the first direction, the second metal line extends along the second direction different from the first direction, and the third metal line extends along the first direction, and wherein the third metal line is laterally offset from the first metal line. In some embodiments, the integrated chip further includes a dielectric liner between the through substrate via and the semiconductor substrate, wherein the dielectric liner is on a top surface and a sidewall of the first metal line.

[0094] In another embodiment, the utility model relates to an integrated chip, which includes a semiconductor substrate having a first side and a second side opposite to the first side. A first transistor and a second transistor are arranged along the first side of the semiconductor substrate. A shallow trench isolation (STI) layer is between the first transistor and the second transistor. The STI layer extends into the semiconductor substrate along the first side of the semiconductor substrate. A dielectric structure including a plurality of dielectric layers is below the first side of the semiconductor substrate. A subsequent structure is within the dielectric structure. The subsequent structure includes a first metal line within the dielectric structure. The first metal line extends along a first direction. The subsequent structure includes a second metal line within the dielectric structure and laterally separated from the first metal line. The second metal line extends along the first direction. The subsequent structure includes a third metal line within the dielectric structure and below the first metal line and the second metal line. The third metal line extends along a second direction different from the first direction. A first metal via is within the dielectric structure and extends from the first metal line to the third metal line. A second metal via is within the dielectric structure and extends from the second metal line to the third metal line. A through substrate via (TSV) extends laterally from the first metal line to the second metal line, vertically between the first metal line and the second metal line to the third metal line, and extends from the first metal line, the second metal line, and the third metal line, through the semiconductor substrate and the STI layer, to the second side of the semiconductor substrate. In some embodiments, the integrated chip further includes a fourth metal line contacting the first transistor; and a fifth metal line contacting the second transistor, wherein the first metal line and the second metal line are directly between the fourth metal line and the fifth metal line. In some embodiments, the third metal line includes a first segment extending along the first direction and a second segment extending along the second direction, wherein the first segment intersects the second segment, and wherein the bottommost surface of the through substrate via is on the top surface of the third metal line. In some embodiments, the integrated chip further includes a fourth metal line, below the first metal line and the second metal line, and laterally separated from the third metal line, the fourth metal line extending along the second direction; and a fifth metal line, below the third metal line and the fourth metal line, the fifth metal line extending along the first direction, wherein the fifth metal line is laterally offset between the first metal line and the second metal line, wherein the substrate via extends vertically to the fifth metal line between the third metal line and the fourth metal line. In some embodiments, the integrated chip further includes: a guard ring structure, within the dielectric structure, the guard ring structure including a plurality of metal lines, a plurality of metal vias, and a plurality of metal gates that collectively surround the next structure and the substrate via in a closed path.

[0095] In yet another embodiment, the utility model relates to a method for forming an integrated chip. A first transistor and a second transistor are formed along a first side of a semiconductor substrate. A dielectric structure including a plurality of dielectric layers is formed above the first side of the semiconductor substrate. A first metal line is formed in the dielectric structure. A first metal via is formed in the dielectric structure line and above the first metal line. A second metal line is formed in the dielectric structure and above the first metal via. The first metal line and the second metal line form a connecting structure. A first etching process is performed on a second side of the semiconductor substrate opposite to the first side to form a trench in the semiconductor substrate. The trench extends from the second side through the semiconductor substrate to the first side. The trench is formed by a pair of sidewalls of the semiconductor substrate. A second etching process is performed on the dielectric structure directly below the trench to extend the trench, thereby further forming a trench by the dielectric structure, the first metal line, and the second metal line. A substrate through hole (TSV) is formed above the second side of the semiconductor substrate, along a pair of sidewalls of the semiconductor substrate, on the first metal line, and on the second metal line. In some embodiments, the first metal line is directly formed between the gate of the first transistor and the gate of the second transistor. In some embodiments, the method further includes forming a third metal line within the dielectric structure and above the second metal line, wherein the third metal line also forms the follow-up structure, wherein the second etching process further extends the trench to the third metal line, and wherein the substrate through hole is formed on the third metal line. In some embodiments, the method further includes forming a guard ring structure including a plurality of metal gates, a plurality of metal lines, and a plurality of metal through holes in the dielectric structure, and collectively surrounding the follow-up structure and the substrate through hole in a closed path. In some embodiments, the method further includes depositing a dielectric liner over the second side of the semiconductor substrate, in the trench, and over the first metal line, wherein the second etching process extends through the dielectric liner directly above the first metal line. In some embodiments, the first metal line extends along a first direction, and wherein the second metal line extends along a second direction different from the first direction.

[0096] The features of several embodiments are summarized above so that those skilled in the art can better understand various aspects of the present invention. Those skilled in the art should understand that they can easily use the present invention as a basis for designing or modifying other processes and structures to achieve the same purposes and / or achieve the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present invention, and they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present invention.

Claims

1. An integrated chip, characterized in that: include: a semiconductor substrate having a first side and a second side opposite to the first side; A first transistor and a second transistor are disposed along the first side of the semiconductor substrate; a dielectric structure comprising a plurality of dielectric layers beneath the first side of the semiconductor substrate; a first metal line within the dielectric structure; a second metal line within the dielectric structure and below the first metal line; a first metal via extending between the first metal line and the second metal line; as well as A through substrate via extends from the second side of the semiconductor substrate, passes through the semiconductor substrate between the first transistor and the second transistor, and reaches the first metal line and the second metal line.

2. The integrated chip according to claim 1, characterized in that: Also includes: A metal guard ring structure at least partially surrounds the first metal line, the second metal line and the substrate through hole.

3. The integrated chip according to claim 1, characterized in that: The first metal line is directly located between the gate of the first transistor and the gate of the second transistor.

4. The integrated chip according to claim 1, characterized in that: The first metal line is separated from the first side of the semiconductor substrate, and the integrated chip further includes: a third metal line within the dielectric structure and below the second metal line; and a second metal via extending between the second metal line and the third metal line, The substrate through via further extends to the third metal line.

5. The integrated chip according to claim 1, characterized in that: Also includes: A dielectric liner is between the through substrate via and the semiconductor substrate, wherein the dielectric liner is on a top surface and a sidewall of the first metal line.

6. An integrated chip, characterized in that: include: a semiconductor substrate having a first side and a second side opposite to the first side; a first transistor and a second transistor arranged along the first side of the semiconductor substrate; a shallow trench isolation layer, between the first transistor and the second transistor, the shallow trench isolation layer extending into the semiconductor substrate along the first side of the semiconductor substrate; a dielectric structure comprising a plurality of dielectric layers beneath the first side of the semiconductor substrate; A bonding structure, within the dielectric structure, comprising: a first metal line, within the dielectric structure, the first metal line extending along a first direction; a second metal line within the dielectric structure and laterally separated from the first metal line, the second metal line extending along the first direction; and a third metal line, within the dielectric structure and below the first metal line and the second metal line, the third metal line extending along a second direction different from the first direction; a first metal via within the dielectric structure and extending from the first metal line to the third metal line; a second metal via within the dielectric structure and extending from the second metal line to the third metal line; and A substrate through via extends laterally from the first metal line to the second metal line, vertically between the first metal line and the second metal line to the third metal line, and extends from the first metal line, the second metal line and the third metal line, through the semiconductor substrate and the shallow trench isolation layer to the second side of the semiconductor substrate.

7. The integrated chip according to claim 6, characterized in that: Also includes: a fourth metal line contacting the first transistor; as well as a fifth metal line contacting the second transistor, The first metal line and the second metal line are directly between the fourth metal line and the fifth metal line.

8. The integrated chip according to claim 7, characterized in that: The third metal line includes a first segment extending along the first direction and a second segment extending along the second direction, wherein the first segment intersects the second segment, and wherein the bottommost surface of the through substrate via is on a top surface of the third metal line.

9. The integrated chip according to claim 6, characterized in that: Also includes: a fourth metal line, below the first metal line and the second metal line and laterally separated from the third metal line, the fourth metal line extending along the second direction; as well as a fifth metal line, below the third metal line and the fourth metal line, the fifth metal line extending along the first direction, wherein the fifth metal line is laterally offset between the first metal line and the second metal line, The through substrate via vertically extends between the third metal line and the fourth metal line to the fifth metal line.

10. The integrated chip according to claim 6, characterized in that: Also includes: A guard ring structure is provided within the dielectric structure, the guard ring structure comprising a plurality of metal lines, a plurality of metal vias and a plurality of metal gates which collectively surround the adjacent structure and the substrate via in a closed path.

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