Semiconductor three-dimensional integrated structure based on rewiring layer and silicon through hole interconnection

Abstract

The utility model relates to the field of semiconductors, and particularly provides a semiconductor three-dimensional integrated structure. The semiconductor three-dimensional integrated structure disclosed by the utility model comprises a wafer, a front device and a rewiring lamination layer, wherein the rewiring lamination layer comprises a first transmission channel and a second transmission channel; the rewiring layer in the first transmission channel is electrically connected with the input end of the front device; the re-wiring layer closest to the wafer in the second transmission channel is connected with the output end of the previous device; the first silicon through hole is located in the rewiring lamination layer and filled with a first metal column, one end of the first metal column is located on the first surface of the wafer, and the other end is in contact with the rewiring layer of the first transmission channel; the second silicon through hole is filled with a second metal column, one end is communicated with the first silicon through hole, and the other end extends to the second surface of the wafer. The number of the rewiring layers included in the first transmission channel is one, the power supply path of the first transmission channel is the shortest, and the transmission loss is reduced; the rewiring layer above the first transmission channel can also be used for wiring of other circuits.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor integration technology, and specifically provides a semiconductor three-dimensional integrated structure based on redistribution layers and through silicon via interconnections. Background Art

[0002] With the development of advanced processes in the semiconductor industry, Moore's Law has gradually come to an end. However, the market demand for low power consumption, high performance, high integration, and miniaturization of electronic products has not stopped. Along with it, TSV (Through Silicon Via) technology, combined with RDL (ReDistribution Layer) technology, can realize vertical interconnection between chips and between chips and external circuits. It is regarded as the core technology of three-dimensional integration with short interconnection distance, low power consumption, high integration, and fast speed. It is also a representative of breaking the limitations of Moore's Law. TSV is filled by Cu electroplating process, and RDL can be prepared by Al process or Cu process. Since Cu process belongs to high-end process, the cost of building Cu process platform is much greater than that of Al process platform, so some wafer foundries currently only have Al process. In addition, considering that Cu RDL tape-out cost is higher, in order to reduce costs, some designers and wafer foundries prefer to choose Al process instead. However, since Cu will cause pollution to Al process equipment, TSV can only be prepared after the multi-layer Al RDL process is completed when Al RDL is used. Therefore, in the case where the power supply on the back of the silicon substrate supplies power to the chip on the front, the current generally needs to be processed by the front-end device first, such as filtering through a bypass capacitor. In this regard, the method adopted by the prior art power supply is that the power supply is led out from the back of the silicon substrate through TSV to the front of the silicon substrate, and then through the topmost Cu RDL, and then through the following layers of Al RDL, layer by layer toward the back of the silicon substrate until it is electrically connected to the front-end device, and then, the power supply to the front chip is realized through each layer of Al RDL in the opposite direction. In the case of a large number of Al RDL layers, this undoubtedly greatly increases the power supply distance between the power supply on the back of the silicon substrate and the front-end devices and chips, and greatly increases the transmission loss. Moreover, in this case, since it is used for electrical connection with the front-end devices, the wiring resources on the same layer that can be used for the lead-out and interconnection of chip pins are bound to be in short supply.

[0003] In order to power the front-end devices through the TSV on the back of the silicon substrate and then through the first layer of RDL closest to the back of the silicon substrate, although the silicon substrate can be thinned after the Al RDL is prepared, and then TSV is made by drilling from the back, but the method of thinning first and then drilling from the back to form TSV requires etching silicon oxide after etching silicon, which is difficult and prone to fragmentation. Therefore, the industry still generally adopts the method of drilling from the front first and then thinning, but the above-mentioned shortcomings of this method are still problems that technicians in this field need to solve urgently. Utility Model Content

[0004] The present disclosure aims to solve the problems of the prior art and provide a semiconductor three-dimensional integrated structure based on redistribution layers and through silicon via interconnections.

[0005] In a first aspect, the present disclosure provides a semiconductor three-dimensional integrated structure based on redistribution layers and through silicon via interconnections, comprising: a wafer, comprising a first surface and a second surface opposite to the first surface; a front-end device, arranged in the wafer and close to the first surface of the wafer; a redistribution stack, located on one side of the first surface of the wafer, comprising dielectric layers and redistribution layers stacked and alternately arranged in sequence, in a direction perpendicular to the wafer surface, the redistribution stack comprises a first transmission channel and a second transmission channel, the first transmission channel comprises at least one redistribution layer, the second transmission channel comprises multiple redistribution layers, the first transmission channel and / or the second transmission channel Two adjacent redistribution layers in the channel are electrically connected; a redistribution layer closest to the wafer in the first transmission channel is electrically connected to the input end of the front-end device through a via; a redistribution layer closest to the wafer in the second transmission channel is electrically connected to the output end of the front-end device through a via; a first through silicon via is located in the redistribution stack and is filled with a first metal column, one end of the first metal column is located on the first surface of the wafer, and the other end is in contact with the redistribution layer closest to the wafer in the first transmission channel; a second through silicon via is connected to the first through silicon via at one end and extends to the second surface of the wafer at the other end, and is filled with a second metal column.

[0006] In some embodiments, a diameter of the first through silicon via is greater than a diameter of the second through silicon via.

[0007] In some embodiments, a diameter of the first through silicon via is 5 μm to 100 μm, and a diameter of the second through silicon via is 0.5 μm to 2 μm.

[0008] In some embodiments, an orthographic projection of the second through silicon via on the wafer is located within an orthographic projection of the first through silicon via on the wafer.

[0009] In some embodiments, an isolation layer and a barrier layer are further disposed between the sidewall of the first through silicon via and the first metal column, and the barrier layer is close to the first metal column.

[0010] In some embodiments, the semiconductor three-dimensional integrated structure further includes a third redistribution layer located on a side of the redistribution stack away from the wafer and electrically connected to a redistribution layer in the second transmission channel farthest from the wafer through a via.

[0011] In some embodiments, the material of the first metal pillar and the second metal pillar is copper; and / or the material of the redistribution layer in the redistribution stack is aluminum; and / or the material of the third redistribution layer is copper.

[0012] In some embodiments, the semiconductor three-dimensional integrated structure further includes a chip, which is located on the first surface of the wafer and is electrically connected to a redistribution layer in the second transmission channel that is farthest from the wafer, or is electrically connected to a third redistribution layer.

[0013] In some embodiments, the semiconductor three-dimensional integrated structure further includes a fourth redistribution layer located on the second surface side of the wafer, and the fourth redistribution layer is electrically connected to the second metal pillar.

[0014] Compared with the prior art, the present invention has the following beneficial effects:

[0015] The number of layers of the redistribution layer included in the first transmission channel is one layer, and the power supply path of the first transmission channel is the shortest, and the transmission loss is reduced. In addition, the redistribution layer above the first transmission channel does not participate in the power supply to the input end of the previous device, so it can be used for the wiring of other circuits, which improves the utilization rate of the redistribution layer in the redistribution stack and reduces the difficulty of wiring in the redistribution stack. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figures 1A to 1E A cross-sectional view of a process for preparing a semiconductor three-dimensional integrated structure in a known technology;

[0017] Figure 1F A cross-sectional view of a semiconductor three-dimensional integrated structure in the known technology;

[0018] FIG. 2A to FIG. 2F A cross-sectional view during the process of preparing the first semiconductor three-dimensional integrated structure provided by the present disclosure;

[0019] Figure 2G A cross-sectional view of the first semiconductor three-dimensional integrated structure provided by the present disclosure;

[0020] Figure 2H A cross-sectional view of a second semiconductor three-dimensional integrated structure provided by the present disclosure.

[0021] Description of reference numerals:

[0022] 1. Wafer; 2. Front-end device; 3. Rewiring stack; 31. First transmission channel; 32. Second transmission channel; 33. Dielectric layer; 34. Rewiring layer; 4. First through silicon via; 5. Second through silicon via; 41. Isolation layer; 42. Barrier layer; 42′, seed layer; 43. First metal pillar; 51. Second metal pillar; 6. Third rewiring layer; 7. Fourth rewiring layer; 8. First insulating layer; 9. First pad; 10. Chip; 11. Packaging layer; 12. Second insulating layer; 13. Second pad. DETAILED DESCRIPTION

[0023] The preferred embodiments of the present disclosure are described below with reference to the accompanying drawings. It should be understood by those skilled in the art that these embodiments are only used to explain the technical principles of the present disclosure and are not intended to limit the protection scope of the present disclosure.

[0024] It should be noted that in the description of the present disclosure, the terms "upper", "lower", "left", "right", "inner", "outer" and the like indicating directions or positional relationships are based on the directions or positional relationships shown in the drawings, which are only for the convenience of description, and do not indicate or imply that the device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present disclosure. In addition, the terms "first" and "second" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.

[0025] Figures 1A to 1E A cross-sectional view of a process for preparing a semiconductor three-dimensional integrated structure in a known technology; Figure 1F It is a cross-sectional view of a semiconductor three-dimensional integrated structure in the known technology.

[0026] In the known technology, the method for preparing a semiconductor three-dimensional integrated structure based on a redistribution layer and through silicon via interconnection includes:

[0027] S1. Provide a wafer 1', wherein the wafer 1' is specifically a silicon wafer or a glass wafer. The wafer 1' comprises a first surface and a second surface opposite to the first surface.

[0028] S2, forming a front-end device 2' on the first surface of the wafer 1'. The front-end device 2' is pre-fabricated on the wafer 1' using a front-end process, and at least part of the structure is located inside the wafer 1', including an input terminal and an output terminal.

[0029] S3, forming a redistribution stack 3' on the first surface of the wafer 1', the redistribution stack 3' comprising dielectric layers 33' and redistribution layers 34' arranged alternately, such as Figure 1AAs shown. Part of the redistribution layers 34' in the redistribution stack 3' are electrically connected to form a first transmission channel 31' and a second transmission channel 32'. The redistribution layer 34' closest to the wafer 1' in the first transmission channel 31' is electrically connected to the input end of the front-end device 2', and the redistribution layer 34' closest to the wafer 1' in the second transmission channel 32' is electrically connected to the output end of the front-end device 2'.

[0030] There is a redistribution layer 34 ′ located on the same layer in the first transmission channel 31 ′ and the second transmission channel 32 ′.

[0031] The dielectric layer 33′ between two adjacent redistribution layers 34′ in the first transmission channel 31′ and / or the second transmission channel 32′ has a via hole, and the via hole is filled with metal (such as tungsten). The two adjacent redistribution layers 34′ in the first transmission channel 31′ and / or the second transmission channel 32′ are electrically connected through the metal filled in the via hole.

[0032] The dielectric layer 33′ closest to the wafer 1′ has a via hole, and the via hole is filled with metal (such as tungsten). The redistribution layer 34′ closest to the wafer 1′ in the first transmission channel 31′ and the input end of the front-end device 2′, as well as the redistribution layer 34′ closest to the wafer 1′ in the second transmission channel 32′ and the output end of the front-end device 2′ are electrically connected through the metal filled in the via hole.

[0033] S4, forming a through silicon via 4', such as Figure 1B As shown, the through silicon via 4' extends from the surface of the redistribution stack 3' to the inside of the wafer 1'.

[0034] S5, filling metal into the through silicon via 4' to form a metal column 41', such as Figure 1C shown.

[0035] S6, forming a third redistribution layer on the side of the redistribution stack 3' away from the wafer 1'. The third redistribution layer includes a first metal layer 61' and a second metal layer 62', such as Figure 1D As shown. The first metal layer 61' is electrically connected to a redistribution layer 34' in the first transmission channel 31' that is farthest from the wafer 1' through a via, and the first metal layer 61' is in direct contact with the metal pillar 41' to achieve electrical connection. The second metal layer 62' is electrically connected to a redistribution layer 34' in the second transmission channel 32' that is farthest from the wafer 1' through a via.

[0036] S7, thinning the second surface of the wafer 1' to expose the metal pillar 41', such as Figure 1E shown.

[0037] S8. Form a fourth redistribution layer 7' on the second surface of the wafer 1'. The fourth redistribution layer 7' is in direct contact with the metal pillar 41' to achieve electrical connection.

[0038] S9. Form a first insulating layer 8' and a first pad 9' on the side of the third redistribution layer 6' away from the wafer 1'. The first pad 9' is electrically connected to a redistribution layer 34' in the second transmission channel 32' that is farthest from the wafer 1' through a via.

[0039] S10, bonding the chip 10' so that the pins on the chip 10' are bonded to the first pads 9'.

[0040] S11, forming a packaging layer 11', such as Figure 1F shown.

[0041] In the above preparation method, the material of the redistribution layer 34' in the first transmission channel 31' and the second transmission channel 32' is aluminum, and the material of the metal column 41' is copper. If the copper metal column 41' is formed before the aluminum redistribution layer 34', it will cause pollution to the process equipment for forming the aluminum redistribution layer 34'. Therefore, the existing preparation method adopts the method of first forming the aluminum redistribution layer 34', and then forming the silicon through-hole 4' and the metal column 41'. Therefore, the metal column 41' is generally electrically connected to the redistribution layer 34' farthest from the wafer 1' in the first transmission channel 31' through the first metal layer 61'. At this time, the path for the semiconductor three-dimensional integrated structure to supply power to the chip 10' is: metal column 41'-all redistribution layers 34' in the first transmission channel 31'-front-end device 2'-all redistribution layers 34' in the second transmission channel 32'-third redistribution layer 6'-first pad 9'-chip 10', the power supply distance is long, and the transmission loss is large.

[0042] In addition, all the redistribution layers 34 ′ in the first transmission channel 31 ′ are used to supply power to the front-end device 2 and the chip 10 ′, occupying more wiring space in the redistribution stack 3 ′, thereby reducing the utilization rate of wiring resources.

[0043] Based on this, the present disclosure provides a method for preparing a semiconductor three-dimensional integrated structure based on a redistribution layer and through silicon via interconnections.

[0044] FIG. 2A to FIG. 2F A cross-sectional view during the process of preparing the first semiconductor three-dimensional integrated structure provided by the present disclosure; Figure 2G A cross-sectional view of the first semiconductor three-dimensional integrated structure provided in the present disclosure.

[0045] The method comprises the following steps.

[0046] S1. Provide a wafer 1, wherein the wafer 1 is a silicon wafer, a glass wafer or an organic wafer. The wafer 1 includes a first surface and a second surface opposite to the first surface.

[0047] S2, forming a front-end device 2 on the first surface of the wafer 1. The front-end device 2 is pre-fabricated on the wafer 1 using a front-end process, and at least part of the structure of the front-end device 2 is located inside the wafer 1. The front-end device 2 includes an input end and an output end.

[0048] S3, forming a redistribution stack 3 on the first surface of the wafer 1, the redistribution stack 3 comprising dielectric layers 33 and redistribution layers 34 arranged alternately, and the layer of the redistribution stack 3 farthest from the wafer 1 and the layer closest to the wafer 1 are both dielectric layers 33, such as Figure 2A As shown. In the direction perpendicular to the surface of the wafer 1, the redistribution stack 3 includes a first transmission channel 31 and a second transmission channel 32, the first transmission channel 31 includes at least one redistribution layer 34, the second transmission channel 32 includes multiple redistribution layers 34, and two adjacent redistribution layers 34 are electrically connected. The redistribution layer 34 closest to the wafer 1 in the first transmission channel 31 is electrically connected to the input end of the front-end device 2, and the redistribution layer 34 closest to the wafer 1 in the second transmission channel 32 is electrically connected to the output end of the front-end device 2.

[0049] There are redistribution layers 34 disposed on the same layer in the first transmission channel 31 and the second transmission channel 32 .

[0050] In the second transmission channel 32 , a via is provided in the dielectric layer 33 between two adjacent redistribution layers 34 . The via is filled with metal (eg tungsten). The two adjacent redistribution layers 34 are electrically connected through the metal filled in the via.

[0051] The dielectric layer 33 closest to the wafer 1 has a via, which is filled with metal (such as tungsten). The redistribution layer 34 closest to the wafer 1 in the first transmission channel 31 and the input end of the front-end device 2, as well as the redistribution layer 34 closest to the wafer 1 in the second transmission channel 32 and the output end of the front-end device 2 are electrically connected through the metal filled in the via.

[0052] The vias in the dielectric layer 33 and the redistribution layer 34 can be formed by a patterning process, which includes coating, exposure, development, etching and debonding. The dielectric layer 33 can be made of inorganic materials such as silicon nitride and silicon dioxide, and the redistribution layer 34 can be made of metal materials such as aluminum that can be patterned.

[0053] The thickness of the redistribution stack 3 depends on the number and thickness of the redistribution layer 34 and the thickness of the dielectric layer 33. For example, in the example disclosed herein, the thickness of the redistribution stack 3 is 1 μm to 20 μm, and the number of the redistribution layer 34 is three. Of course, in other examples, the number of the redistribution layer 34 can also be two, four or more layers.

[0054] S4, forming a second through silicon via 5, such as Figure 2B As shown. The second silicon via 5 is formed by a patterning process and extends from the surface of the redistribution stack 3 to the wafer 1, that is, the second silicon via 5 completely penetrates the wiring layer 3 along the thickness direction and extends into the wafer 1. The length of the silicon via is generally determined during circuit design based on factors such as resistance, aspect ratio, and application requirements. The second silicon via 5 can be exposed from the second surface after the wafer 1 is thinned from the second surface. For example, the depth of the second silicon via 5 extending into the wafer 1 is 50μm to 300μm.

[0055] The diameter of the second through silicon via 5 cannot be too large, otherwise, when the first through silicon via 4 is formed by a subsequent patterning process, a large amount of photoresist easily enters the second through silicon via 5 and is difficult to remove, which affects the filling quality of the metal into the second through silicon via 5. In the example disclosed in the present invention, the diameter of the second through silicon via 5 is 0.5 μm to 2 μm.

[0056] S5, forming a first through silicon via 4, such as Figure 2C As shown. The first silicon via 4 extends from the surface of the redistribution stack 3 to the inside of the redistribution stack 3, and exposes a redistribution layer 34 in the first transmission channel 31 that is closest to the wafer 1 through the first silicon via 4. The number of layers of the redistribution layer 34 included in the first transmission channel 31 is one layer, the power supply path of the first transmission channel 31 is the shortest, and the transmission loss is reduced. In addition, the redistribution layer 34 above the first transmission channel 31 does not participate in the power supply to the input end of the previous device 2, so it can be used for the wiring of other circuits, which improves the utilization rate of the redistribution layer 34 in the redistribution stack 3 and reduces the difficulty of wiring in the redistribution stack 3.

[0057] The diameter of the first TSV 4 is greater than that of the second TSV 5 , for example, the diameter of the first TSV 4 is 5 μm to 100 μm. The orthographic projection of the second TSV 5 on the wafer 1 is within the orthographic projection of the first TSV 4 on the wafer 1 .

[0058] S6, forming an isolation layer 41 in the first through silicon via 4 and the second through silicon via 5, such as Figure 2D The isolation layer 41 is mainly used to isolate the wafer 1 from the metal layer to reduce the possibility of leakage between the metal layer and the wafer 1, and a commonly used insulating material can be selected.

[0059] In addition, since the diameter of the first silicon via 4 is relatively large, the difficulty of forming the isolation layer 41, the barrier layer 42 and the seed layer 42′ can be reduced, the deposition uniformity of the isolation layer 41, the barrier layer 42 and the seed layer 42′ can be improved, and the opening of the first silicon via 4 is avoided from being closed prematurely during the formation of the seed layer 42′, thereby preventing the formation of voids.

[0060] S7, removing the isolation layer 41 at the bottom of the first through silicon via 4. Figure 2E As shown, a dry etching process is used to vertically bombard the isolation layer 41 at the bottom of the first through silicon via 4. Since the diameter of the second through silicon via 5 is small and the depth of the second through silicon via 5 is deep, the bombarding ions are consumed in the process and cannot reach the bottom of the second through silicon via 5. Therefore, in the process of removing the isolation layer 41 at the bottom of the first through silicon via 4, the isolation layer 41 at the bottom of the second through silicon via 5 can be retained.

[0061] S8, forming a barrier layer 42 and a seed layer 42' in the first through silicon via 4 and the second through silicon via 5, as shown in FIG. Figure 2E The barrier layer 42 is used to prevent the metal in the metal layer from entering the isolation layer 41 and the wafer 1, and specifically, a composite film layer of Ti or Ta or Ta and TaN can be selected. The seed layer 42' provides seed crystals for subsequent copper electroplating.

[0062] S9, filling the first through silicon via 4 and the second through silicon via 5 with metal, such as Figure 2F As shown. The metal filled in the first through silicon via 4 forms a first metal column 43, and the metal filled in the second through silicon via 5 forms a second metal column 51. For example, metal is grown on the seed layer 42′ by electrochemical plating to form the first metal column 43 and the second metal column 51. After the metal is filled in the first through silicon via 4 and the second through silicon via 5, the surface of the redistribution stack 3 away from the wafer 1 can be mechanically and chemically polished to remove the metal, barrier layer 42 and isolation layer 41 located on the surface of the redistribution stack 3 away from the wafer 1. Since the barrier layer 42 is conductive, the first metal column 43 can be electrically connected to the redistribution layer 34 exposed by the first through silicon via 4 through the barrier layer 42.

[0063] S10, patterning a dielectric layer 33 of the redistribution stack 3 farthest from the wafer 1 to form a via hole, and then forming a third redistribution layer 6 on the redistribution stack 3. The third redistribution layer 6 is electrically connected to a redistribution layer 34 farthest from the wafer 1 in the second transmission channel 32 through the via hole.

[0064] The material of the third redistribution layer 6 is copper, and the metal material in the via hole between the third redistribution layer 6 and the redistribution layer 34 farthest from the substrate in the second transmission channel 32 is also copper. The filling metal in the via hole and the third redistribution layer 6 can be formed in the same process step. For example, the third redistribution layer 6 and the filling metal in the via hole can be formed by a Damascene process or a PI glue semi-additive process.

[0065] S11 , thinning the second surface of the wafer 1 to expose the second metal pillar 51 in the second through silicon via 5 .

[0066] S12 , forming a fourth redistribution layer 7 on the second surface of the wafer 1 , wherein the fourth redistribution layer 7 is in direct contact with the second metal pillar 51 to achieve electrical connection.

[0067] S13, forming a first insulating layer 8 and a first pad 9 on a side of the third redistribution layer 6 away from the wafer 1, wherein the first pad 9 is electrically connected to the third redistribution layer 6 through a via hole, such as Figure 2G shown.

[0068] S14 , bonding the chip 10 , so that the pins on the chip 10 are bonded to the first pads 9 .

[0069] S15, forming a packaging layer 11. The packaging layer 11 is used to package the chip 10, and the specific material may be epoxy resin.

[0070] Figure 2H A cross-sectional view of a second semiconductor three-dimensional integrated structure provided by the present disclosure.

[0071] The present disclosure also provides another method for preparing a semiconductor three-dimensional integrated structure based on a redistribution layer and a through silicon via interconnection, wherein the preparation process is basically the same as that of the previous embodiment, except that the process of forming the third redistribution layer 6 in step S10 and the process of forming the first insulating layer 8 in step S13 are omitted, and the first pad 9 formed in step S13 is electrically connected to a redistribution layer 34 in the second transmission channel 32 farthest from the wafer 1 through a via hole, such as Figure 2H In this embodiment, the process of forming the third redistribution layer 6 in step S10 and the process of forming the first insulating layer 8 in step S13 are omitted, which simplifies the process flow and reduces the processing cost of the process.

[0072] The present disclosure also provides a semiconductor three-dimensional integrated structure based on redistribution layers and silicon through via interconnections, including a wafer, the wafer including a first surface and a second surface opposite to the first surface; a front-end device, arranged in the wafer and close to the first surface of the wafer; a redistribution stack, located on one side of the first surface of the wafer, including dielectric layers and redistribution layers stacked and alternately arranged in sequence, in a direction perpendicular to the wafer surface, the redistribution stack includes a first transmission channel and a second transmission channel, the first transmission channel includes at least one redistribution layer, the second transmission channel includes multiple redistribution layers, the first transmission channel and / or the second transmission channel Two adjacent redistribution layers are electrically connected; a redistribution layer closest to the wafer in the first transmission channel is electrically connected to the input end of the front-end device through a via; a redistribution layer closest to the wafer in the second transmission channel is electrically connected to the output end of the front-end device through a via; a first through silicon via is located in the redistribution stack and is filled with a first metal column, one end of the first metal column is located on the first surface of the wafer, and the other end is in contact with the redistribution layer closest to the wafer in the first transmission channel; a second through silicon via is connected to the first through silicon via at one end and extends to the second surface of the wafer at the other end, and is filled with a second metal column.

[0073] The following combination Figure 2G The semiconductor three-dimensional integrated structure shown is illustrated.

[0074] The semiconductor three-dimensional integrated structure includes a wafer 1. The wafer 1 includes a first surface and a second surface opposite to the first surface.

[0075] A front-end device 2 is disposed in the wafer 1, and the front-end device 2 is close to the first surface of the wafer 1. The front-end device 2 includes an input terminal and an output terminal. The front-end device 2 may be a bypass capacitor, a CMOS (Complementary Metal Oxide Semiconductor) device, or the like.

[0076] The first surface of the wafer 1 is provided with a redistribution stack 3, which includes a dielectric layer 33 and a redistribution layer 34 stacked in sequence, wherein the layer closest to the wafer 1 and the layer farthest from the wafer 1 are both dielectric layers 33. The material of the redistribution layer 34 can be aluminum, and the material of the dielectric layer 33 can be an inorganic insulating material such as silicon oxide and silicon nitride.

[0077] In a direction perpendicular to the surface of the wafer 1, the redistribution stack 3 includes a first transmission channel 31 and a second transmission channel 32. The first transmission channel 31 includes a layer of redistribution layer 34, and the second transmission channel 32 includes multiple layers of redistribution layers 34, and two adjacent layers of redistribution layers 34 are electrically connected. The layer of redistribution layer 34 closest to the wafer 1 in the first transmission channel 31 is electrically connected to the input end of the front-end device 2, and the layer of redistribution layer 34 closest to the wafer 1 in the second transmission channel 32 is electrically connected to the output end of the front-end device 2.

[0078] There are redistribution layers 34 disposed on the same layer in the first transmission channel 31 and the second transmission channel 32 .

[0079] In the second transmission channel 32, the dielectric layer 33 between two adjacent redistribution layers 34 has a via hole, and the via hole is filled with metal (such as tungsten), and the two adjacent redistribution layers 34 are electrically connected through the metal filled in the via hole. The dielectric layer 33 closest to the wafer 1 has a via hole, and the via hole is filled with metal (such as tungsten), and the redistribution layer 34 closest to the wafer 1 in the first transmission channel 31 and the input end of the front-end device 2 and the redistribution layer 34 closest to the wafer in the second transmission channel 32 and the output end of the front-end device 2 are electrically connected through the metal filled in the via hole.

[0080] A first through silicon via 4 is also provided in the redistribution stack 3 , and the first through silicon via 4 extends from the surface of the redistribution stack 3 to a redistribution layer 34 closest to the wafer 1 in the first transmission channel 31 , so that part of the structure of the redistribution layer 34 is exposed through the first through silicon via 4 .

[0081] The bottom of the first through silicon via 4 is connected to the second through silicon via 5, one end of the second through silicon via 5 is connected to the first through silicon via 4, and the other end extends to the second surface of the wafer 1. The diameter of the first through silicon via 4 is greater than the diameter of the second through silicon via 5. For example, the diameter of the first through silicon via 4 is 5 μm to 100 μm, and the diameter of the second through silicon via 5 is 0.5 μm to 2 μm. The orthographic projection of the second through silicon via 5 on the wafer 1 is located within the orthographic projection of the first through silicon via 4 on the wafer 1.

[0082] The sidewalls of the first through silicon via 4 and the second through silicon via 5 are provided with an isolation layer 41, a barrier layer 42 and a seed layer 42′ in sequence, and the bottom of the first through silicon via 4 is not provided with an isolation layer 41 and a barrier layer 42. The first through silicon via 4 and the second through silicon via 5 are filled with metal pillars, and the metal pillars are located inside the barrier layer 42. Among them, the metal pillar filled in the first through silicon via 4 is a first metal pillar 43, and the metal pillar filled in the second through silicon via 5 is a second metal pillar 51. The first metal pillar 43 is in direct contact with the redistribution layer 34 exposed by the first through silicon via 4 to form an electrical connection. The materials of the first metal pillar 43 and the second metal pillar 51 are copper.

[0083] A third redistribution layer 6 is provided on the side of the redistribution stack 3 away from the wafer 1, and a via is provided in the dielectric layer 33 between the third redistribution layer 6 and a redistribution layer 34 in the second transmission channel 32 that is farthest from the wafer 1, and the third redistribution layer 6 is electrically connected to a redistribution layer 34 in the second transmission channel 32 that is farthest from the wafer 1 through a metal (such as copper) filled in the via. The material of the third redistribution layer 6 is copper.

[0084] The third redistribution layer 6 has a first insulating layer 8 and a first pad 9 on a side away from the wafer 1 . A via is provided in the first insulating layer 8 . The first pad 9 is electrically connected to the third redistribution layer 6 through metal filled in the via.

[0085] The semiconductor three-dimensional integrated structure further includes a chip 10, the pins of which are soldered to the first pad 9. A packaging layer 11 is disposed outside the chip 10, and the packaging layer 11 packages the chip 10 and the side of the first insulating layer 8 away from the wafer 1.

[0086] The second surface of the wafer 1 is provided with a fourth redistribution layer 7, which is in direct contact with the second metal pillar 51 to achieve electrical connection. The fourth redistribution layer 7 has a second insulating layer 12 and a second pad 13 on the side away from the wafer 1, and the second pad 13 is electrically connected to the fourth redistribution layer 7 after passing through the second insulating layer 12.

[0087] The power supply is electrically connected to the second pad 13, and the current flows to the chip 10 after passing through the fourth redistribution layer 7, the second metal column 51, the first metal column 43, a redistribution layer 34 in the first transmission channel 31, the front-end device 2, all the redistribution layers 34 in the second transmission channel 32, the third redistribution layer 6 and the first pad 9 in sequence to supply power to the chip 10.

[0088] The number of layers of the redistribution layer 34 included in the first transmission channel 31 is one layer, and the power supply path of the first transmission channel 31 is the shortest, and the transmission loss is reduced. In addition, the redistribution layer 34 above the first transmission channel 31 does not participate in supplying power to the input end of the previous device 2, so it can be used for wiring of other circuits, thereby improving the utilization rate of wiring resources and reducing the difficulty of wiring in the redistribution stack 3.

[0089] like Figure 2H As shown, the present disclosure also provides another semiconductor three-dimensional integrated structure based on redistribution layer and silicon through-hole interconnection, and its structure is basically the same as the above embodiment, except that, because the redistribution layer 34 with aluminum as the metal is partially vacated, it can be used to replace the redistribution originally realized by the third redistribution layer 6 with copper as the metal, so that the third redistribution layer 6 with copper as the metal can be omitted. At this time, the first pad 9 is located on the dielectric layer 33 of the wiring layer 3 farthest from the wafer 1, and the first pad 9 is electrically connected to the redistribution layer 34 farthest from the wafer 1 in the second transmission channel 32 through the metal (such as copper) filled in the via. The number of film layers of this semiconductor three-dimensional integrated structure is reduced, the production process is simpler, and the production cost is lower.

[0090] So far, the technical solutions of the present disclosure have been described in conjunction with the preferred embodiments shown in the accompanying drawings. However, it is easy for those skilled in the art to understand that the protection scope of the present disclosure is obviously not limited to these specific embodiments. Without departing from the principles of the present disclosure, those skilled in the art may make equivalent changes or substitutions to the relevant technical features, and the technical solutions after these changes or substitutions will fall within the protection scope of the present disclosure.

Claims

1. A semiconductor three-dimensional integrated structure based on redistribution layer and through silicon via interconnection, characterized in that: include: A wafer comprising a first surface and a second surface opposite to the first surface; A front-end device is disposed in the wafer and close to the first surface of the wafer; A redistribution stack is located on one side of the first surface of the wafer, comprising dielectric layers and redistribution layers stacked in sequence and arranged alternately, in a direction perpendicular to the wafer surface, the redistribution stack comprises a first transmission channel and a second transmission channel, the first transmission channel comprises at least one redistribution layer, the second transmission channel comprises multiple redistribution layers, two adjacent redistribution layers in the first transmission channel and / or the second transmission channel are electrically connected; a layer of the redistribution layer closest to the wafer in the first transmission channel is electrically connected to the input end of the front-end device through a via hole; a layer of the redistribution layer closest to the wafer in the second transmission channel is electrically connected to the output end of the front-end device through a via hole; A first through silicon via is located in the redistribution stack and is filled with a first metal column, wherein one end of the first metal column is located on the first surface of the wafer and the other end is in contact with a layer of the redistribution layer in the first transmission channel that is closest to the wafer; A second through silicon via is connected to the first through silicon via at one end and extends to the second surface of the wafer at the other end, and is filled with a second metal column.

2. The semiconductor three-dimensional integrated structure according to claim 1, characterized in that: A diameter of the first through silicon via is greater than a diameter of the second through silicon via.

3. The semiconductor three-dimensional integrated structure according to claim 2, characterized in that: A diameter of the first through silicon via is 5 μm to 100 μm, and a diameter of the second through silicon via is 0.5 μm to 2 μm.

4. The semiconductor three-dimensional integrated structure according to claim 1, characterized in that: An orthographic projection of the second through silicon via on the wafer surface is located within an orthographic projection of the first through silicon via on the wafer surface.

5. The semiconductor three-dimensional integrated structure according to claim 1, characterized in that: An isolation layer and a barrier layer are further disposed between the first through silicon via sidewall and the first metal column, and the barrier layer is close to the first metal column.

6. The semiconductor three-dimensional integrated structure according to claim 1, characterized in that: The semiconductor three-dimensional integrated structure also includes a third redistribution layer, which is located on a side of the redistribution stack away from the wafer and is electrically connected to a layer of the redistribution layer in the second transmission channel that is farthest from the wafer through a via.

7. The semiconductor three-dimensional integrated structure according to claim 6, characterized in that: The material of the first metal column and the second metal column is copper; and / or, The material of the redistribution layer in the redistribution stack is aluminum; and / or, The material of the third redistribution layer is copper.

8. The semiconductor three-dimensional integrated structure according to claim 6, characterized in that: The semiconductor three-dimensional integrated structure also includes a chip, which is located on the first surface of the wafer and is electrically connected to the redistribution layer in the second transmission channel that is farthest from the wafer, or is electrically connected to the third redistribution layer.

9. The semiconductor three-dimensional integrated structure according to claim 1, characterized in that: The semiconductor three-dimensional integrated structure further includes a fourth redistribution layer located on the second surface side of the wafer, and the fourth redistribution layer is electrically connected to the second metal column.

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