Semiconductor device

Abstract

The embodiment of the utility model provides a semiconductor device. The semiconductor device comprises a first integrated circuit tube core, a second integrated circuit tube core and a first conductive feature, wherein the first integrated circuit tube core is arranged side by side; the second integrated circuit tube core is overlapped with the first integrated circuit tube core and is electrically coupled to the first integrated circuit tube core; each first integrated circuit die includes first and second die connectors. A first pitch of the first die connectors is less than a second pitch of the second die connectors and substantially equal to a third pitch of the third die connectors of the second integrated circuit die. The first conductive feature is interposed between and electrically coupled to the first and third die connectors. Each first conductive feature includes at least one first conductive bump and at least one first conductive contact. Manufacturing costs may be reduced by omitting a redistribution layer between stacked integrated circuit dies.

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor device, and more particularly to a semiconductor device including stacked integrated circuit dies. Background Art

[0002] Semiconductor devices and integrated circuits used in various electronic applications are usually made from wafers. The integrated circuit (IC) die of the wafer is processed and packaged together with other electronic devices at the wafer level, and various technologies have been developed for wafer-level packaging. In addition, for multi-die packages, the arrangement and packaging technology of the IC die will affect the reliability of the packaged product. Utility Model Content

[0003] An embodiment of the utility model provides a semiconductor device including a plurality of first integrated circuit dies arranged side by side, a second integrated circuit die overlapping the first integrated circuit die and electrically connected to the first integrated circuit die, and a plurality of first conductive features. Each of the first integrated circuit dies includes a plurality of first die connectors and a plurality of second die connectors, wherein the first spacing of the first die connectors is less than the second spacing of the second die connectors. The second integrated circuit die includes a plurality of third die connectors, wherein the third spacing of the third die connectors is substantially equal to the first spacing of the first die connectors. The first conductive feature is inserted between the first die connector and the third die connector and electrically coupled to the first die connector and the third die connector, and each of the first conductive features includes at least one first conductive bump and at least one first conductive contact.

[0004] An embodiment of the utility model provides a semiconductor device including a plurality of first integrated circuit dies arranged side by side, a second integrated circuit die stacked on the first integrated circuit die and electrically coupled to the first integrated circuit die, a plurality of conductive pillars arranged on the first integrated circuit die, a first electrical connection electrically connected to one of the second integrated circuit die and the first integrated circuit die, and a second electrical connection electrically connected to one of the conductive pillars and one of the first integrated circuit dies. The first electrical connection includes a first solder joint physically connected to a die connector of the second integrated circuit die, and an interface between the second electrical connection and the one of the conductive pillars does not have solder material, wherein the size of the first conductive bump of the first electrical connection is smaller than the size of the second conductive bump of the second electrical connection.

[0005] Based on the above, the pitch of the first electrical connection is smaller than the pitch of the second electrical connection, wherein the first electrical connection provides a fine pitch interconnection. Each of the first electrical connection and the second electrical connection can be regarded as a signal line routed in the Z direction between the first integrated circuit die and the second integrated circuit die. The signal paths between the second integrated circuit die and the first integrated circuit die and between the electrical connector and the first integrated circuit die are shorter than those in a conventional semiconductor device, wherein in the conventional semiconductor device, the stacked die and the electrical connector are coupled together using a redistribution layer, and the redistribution layer has signal lines routed in the X direction, the Y direction, and the Z direction. Manufacturing costs can be reduced by omitting the redistribution layer between the stacked integrated circuit dies.

[0006] In order to make the above features and advantages of the embodiments of the present invention more obvious and easy to understand, embodiments are specifically cited below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figures 1 to 7 Schematic cross-sectional views of intermediate steps during a process of forming a semiconductor device are shown in accordance with some embodiments.

[0008] Figure 8-9 10A and 11A illustrate schematic cross-sectional views of intermediate steps during a process of forming additional semiconductor devices, according to some embodiments.

[0009] Fig. 10B and 11B Schematic cross-sectional views of intermediate steps during a process of forming further semiconductor devices are shown in accordance with some embodiments.

[0010] Fig. 12A and 12B Schematic cross-sectional views of variations of semiconductor devices according to some embodiments are shown.

[0011] Figures 13 to 20 Schematic cross-sectional views are shown of intermediate steps during a process of forming a semiconductor package in accordance with some embodiments.

[0012] Figures 21 to 25 Schematic cross-sectional views are shown of intermediate steps during a process of forming additional semiconductor packages in accordance with some embodiments.

[0013] Fig.26 and 27 Schematic cross-sectional views of intermediate steps during a process of forming further semiconductor devices are shown in accordance with some embodiments.

[0014] Figure 28 to Figure 31Schematic cross-sectional views of intermediate steps during a process of forming further semiconductor devices are shown in accordance with some embodiments.

[0015] Fig.32 A schematic cross-sectional view of a further semiconductor device according to some embodiments is shown.

[0016] Figure 33 to Figure 37 Schematic cross-sectional views of intermediate steps during a process of forming a semiconductor device are shown in accordance with some embodiments.

[0017] Fig.38 A schematic cross-sectional view of a semiconductor device according to some embodiments is shown.

[0018] Description of Reference Numerals

[0019] 10, 20A, 20B, 30A, 30B, 70A, 70B, 80A, 80B: semiconductor device; 21D: dispensing tool; 40, 50, 60: semiconductor package; 51: first temporary carrier; 52: first release layer; 53: second temporary carrier; 54: second release layer; 55: tape; 56: frame; 101, 101', 201: first conductive bump; 102, 102', 202: second conductive bump; 102W, 261W, 262W, 263W, D1, D2: maximum lateral size; 103, 103': third conductive bump; 110, 110A, 110B, 120, 210: first IC die; 110r, 111r, 140b , 150b, 151b, 210r, 240b: rear surface; 110s, 150s, 240s: sidewall; 111, 151, 151', 211, 351': semiconductor substrate; 111J, 117J: first conductive contact; 112, 142, 152, 212, 242, 342, 352: die connector; 112J, 118J: second conductive contact; 113J, 116J': third conductive contact; 114J: fourth conductive contact; 115J: fifth conductive contact; 116J: conductive contact; 121, 421: first bottom filler; 121b, 132b, 201b, 202a, 202b, 202b', 215a, 232a, 260b, 262a, 263a, 332b, 421b, 2121a, 2122a: surface; 121s: inner side wall; 122, 222, 322, 423': second bottom filler; 123, 223, 323: third bottom filler; 124: fourth bottom filler; 125, 423: bottom filler; 131, 231, 331, 431: first insulating enclosure; 131a, 231a, 261a, 331a, 431a: first surface; 131b, 231b, 261b, 331b, 431b: second surface; 132, 232, 332, 432: second insulating enclosure; 140, 240, 340: passive component; 140 H, 150H, 160H: height; 150, 150', 250, 350, 350': second IC die; 160, 160', 276, 380: electrical connector; 160B, 276B: bump portion; 160P, 160P', 276P: column portion; 160PD, 201D, 202D, 352D, 2121D, 2122D: lateral size; 210a: active surface; 213, 353: passivation layer; 214, 354: conductive pad; 215: protective layer; 254: capacitor structure; 255: substrate through hole / TSV; 260: conductive column / TIV; 261: first conductive column / first TIV; 262: second conductive column / second TIV;263: third conductive pillar / third TIV; 272: dielectric layer; 274, 374: conductive pattern; 350b: thinned rear surface; 370, 370': redistribution structure; 410, 510: lower package component; 420: upper package component; 422: conductive terminal; 470: back-side redistribution structure; 541: LTHC film; 542: adhesive film; 1011, 1021, 1031, 1601, 1601', 2021, 2601, 2602 31: seed layer; 1011a, 1021a, 1031a, 1601a, 2601a, 2631a: first sublayer; 1011b, 1021b, 1031b, 1601b, 2601b, 2631b: second sublayer; 1012, 1022, 1032, 1421, 1521, 2761: first metallization layer; 1013, 1023, 1033, 1422, 1522, 2762: second metallization layer; 1014, 1024, 1034: third metallization layer; 1121, 2121: first connector; 1122, 2122: second connector; 1141, 3741: first portion; 1141s: vertical sidewall; 1142, 3742: second portion; 1142s: curved sidewall; 1602, 2602, 2632: metallization layer; 3711, 3711', 4711: patterned dielectric layer; 3712, 3712', 4712: patterned conductive layer; Electrical layer; 3712a: UBM pattern; 3712b: conductive bump; 4711p: opening; A, B, C, D, E, F: dotted box; C1, C2, C3, C4: center; P1, P2, P3: spacing; R1: first region; R2: second region; R3: third region; V1: first electrical connection; V1': vertical connection; V2: second electrical connection; V3: third electrical connection; S1: first side; S2: second side; S3: vertical sidewall; X, Y, Z: direction. ; DETAILED DESCRIPTION

[0020] The following disclosure provides many different embodiments or examples for implementing different features of the present disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to limit the scope of the present disclosure. For example, in the following description, a first feature is formed "above" or "on" a second feature, which may include an embodiment in which the first feature and the second feature are formed to be in direct contact, and may also include an embodiment in which an additional feature is formed between the first feature and the second feature so that the first feature and the second feature are not in direct contact. In addition, the present disclosure may reuse component numbers and / or letters in various examples. Such repetition is for the purpose of simplifying and clearly describing the present disclosure, rather than for defining the relationship between various embodiments and / or configurations.

[0021] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one component or feature to another (other) component or feature as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be in other orientations (rotated 90 degrees or at other orientations) and the spatially relative descriptors used therein may be interpreted in a similar manner.

[0022] Figures 1 to 7 Schematic cross-sectional views of intermediate steps during a process of forming a semiconductor device according to some embodiments are shown.Although method embodiments are discussed as being performed in a particular order, other embodiments may be performed in any logical order.

[0023] Reference Figure 1 , the first conductive bump 101' and the second conductive bump 102' may be formed on the first temporary carrier 51. The first temporary carrier 51 may be made of a suitable material (e.g., silicon), a polymer, a polymer composite, a metal foil, a ceramic, a glass, a glass epoxy, a tape, or other suitable materials for structural support. In some embodiments, the first temporary carrier 51 has a first release layer 52, and the first conductive bump 101' and the second conductive bump 102' are formed on the first release layer 52. In some embodiments, the first release layer 52 includes a photosensitive film, and the photosensitive film can be easily separated from the first temporary carrier 51 by irradiating light onto the first temporary carrier 51 in a subsequent peeling process. For example, the first release layer 52 includes a light-to-heat-conversion (LTHC) coating. In some embodiments, the first release layer 52 includes a die bonding film or any suitable adhesive film.

[0024] It should be understood that design for manufacturing (DFM) is the integration of manufacturing data and design procedures to obtain better yield and design efficiency. DFM can be implemented in the stage of forming the first and / or second conductive bumps. For example, when curing the insulating material to form an insulating encapsulation in a subsequent process (see Figure 2 ), the insulating material is deformed, and uneven stress may be applied to the corresponding first integrated circuit (IC) die causing the first IC die to deviate from its original position after placement. As the demand for dies with fine pitch die connectors continues to increase, resulting in reduced alignment margins, incorrect alignment may become increasingly problematic. Various process deviations introduced from various process modules can be compensated by adjusting the layout of the first conductive bump 101' and / or the second conductive bump 102'.

[0025] The first conductive bump 101' may be formed in the first region R1 on the first temporary carrier 51, and the second conductive bump 102' may be formed in the second region R2 on the first temporary carrier 51. In a top view (not shown), the second region R2 may surround the first region R1. The first conductive bump 101' may be formed before (or after) the second conductive bump 102' is formed. In an alternative embodiment, the first and second conductive bumps (101' and 102') are formed in the same step by using a single photomask. In some embodiments, the formation of the first conductive bump 101' and / or the second conductive bump 102' includes at least the following steps. A seed material layer may be formed on the first temporary carrier 51. For example, the seed material layer is a composite layer including a first material sublayer and a second material sublayer stacked on the first material sublayer, wherein the first and second material sublayers are formed of different materials. In some embodiments, the first material sublayer is formed of titanium and the second material sublayer is formed of copper. Alternatively, the seed material layer is a single layer formed of copper or a copper alloy. Next, according to the desired metallization pattern, a photoresist can be formed and patterned on the seed material layer. Conductive materials (such as copper, nickel, tin, lead, gold, palladium, indium, etc.) can be sequentially formed in the opening of the photoresist and on the exposed portion of the seed material layer. Then, the photoresist and part of the seed material layer on which the conductive material is not formed can be removed. The reflow process can be selectively performed to shape the topmost conductive material (such as solder) into a desired shape. The remaining part of the seed material layer and the conductive material is formed into the first conductive bump 101' and / or the second conductive bump 102'. It should be noted that there may also be other methods for forming the first conductive bump 101' and the second conductive bump 102' and are fully included in the scope of the present utility model.

[0026] Continue to refer to Figure 1, the corresponding first conductive bump 101' may include a seed layer 1011, a first metallization layer 1012 overlying the seed layer 1011, a second metallization layer 1013 overlying the first metallization layer 1012, and a third metallization layer 1014 overlying the second metallization layer 1013. The seed layer 1011 may include a first sublayer 1011a and a second sublayer 1011b overlying the first sublayer 1011a. For example, the first sublayer 1011a is a titanium sublayer and the second sublayer 1011b is a copper sublayer, but any suitable conductive seed material may be used. The first metallization layer 1012 and the second sublayer 1011b may be formed of the same material (e.g., copper), while the first metallization layer 1012 and the overlying second metallization layer 1013 may be formed of different materials. The second metallization layer 1013 may be a nickel-containing layer or may include nickel, tin, tin-lead, gold, silver, platinum, palladium, indium, nickel-palladium-gold, nickel-gold, alloys, etc. The third metallization layer 1014 may be a solder-containing layer or may include lead-free solder, such as tin, tin-silver (SnAg), tin-bismuth (SnBi) solder, copper (SAC) solder, combinations thereof, etc. The second metallization layer 1013 may act as a diffusion barrier layer that blocks copper from diffusing from the first metallization layer 1012 to the third metallization layer 1014. For example, without the diffusion barrier layer, since the first metallization layer 1012 has a rich copper source, an intermetallic compound (IMC) may be formed at the interface with the solder layer, thereby resulting in weaker bonding strength and poorer adhesion.

[0027] In some embodiments, the corresponding second conductive bump 102' includes a seed layer 1021 including a first sublayer 1021a and a second sublayer 1021b, a first metallization layer 1022 overlying the seed layer 1021, a second metallization layer 1023 overlying the first metallization layer 1022, and a third metallization layer 1024 overlying the second metallization layer 1023. Each layer of the corresponding second conductive bump 102' may be similar to the corresponding layer of the corresponding first conductive bump 101', so the details are not repeated for the sake of brevity. In some embodiments, the pitch P1 between two adjacent first conductive bumps 101' is less than the pitch P2 between two adjacent second conductive bumps 102'. For example, the pitch P1 is less than 20μm, and the pitch P2 is several times larger than the pitch P1, for example, about 80μm to 90μm. In some embodiments, the maximum lateral size (eg, diameter or width) D1 of the corresponding first conductive bump 101' is smaller than the maximum lateral size (eg, diameter or width) D2 of the corresponding second conductive bump 102'. Figure 1 The illustration is only an example, and the number and configuration of the first and second conductive bumps (101' and 102') may vary according to product requirements.

[0028] Reference Figure 2And refer to Figure 1 , the first IC die 110 may be disposed on and electrically coupled to the first and second conductive bumps ( 101 ′ and 102 ′). The corresponding first IC die 110 may be a logic device (e.g., a central processing unit (CPU), a graphics processing unit (GPU), a microcontroller, etc.), a storage device (e.g., a dynamic random access memory (DRAM) die, a static random access memory (SRAM) die, etc.), a power management device (e.g., a power management integrated circuit (PMIC) die), a radio frequency (RF) device, a sensor device, a micro-electro-mechanical-system (MEMS) device, a signal processing device (e.g., a digital signal processing (DSP) die), a front-end device (e.g., an analog front-end (AFE) die), a combination thereof (e.g., a system-on-a-chip (SoC) die), etc. These first IC dies 110 may be of different types. For example, the first IC die 110A is a logic die and the first IC die 110B is a memory die. In some embodiments, all of the first IC dies 110 are of the same type.

[0029] The first IC die 110 may be formed from a single wafer or multiple wafers, and the wafer may include different die regions that are singulated to form individual first IC dies 110. For example, the respective first IC die 110 includes a semiconductor substrate 111, such as doped or undoped silicon or an active layer of a semiconductor-on-insulator (SOI) substrate. The semiconductor substrate 111 may include other semiconductor materials, such as germanium, compound semiconductors (including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide), alloy semiconductors (including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP), or combinations thereof. Other substrates, such as multilayer or gradient substrates, may also be used. In some embodiments, the semiconductor substrate 111 includes devices (e.g., capacitors, diodes, transistors, resistors, inductors, etc.; not shown) and internal wiring structures (not shown), wherein the internal wiring structures include alternating dielectric layers and conductive layers, and the conductive layers are connected to the devices to form functional circuits.

[0030] The respective first IC die 110 may include die connectors 112 distributed over the semiconductor substrate 111 and connected to the interconnect structure (if present). The die connectors 112 of the respective first IC die 110 may include first connectors 1121 and second connectors 1122. The first and second connectors (1121 and 1122) of the first IC die (110A and 110B) may be arranged in a mirror-symmetrical configuration with respect to a virtual axis between the first IC die (110A and 110B) in the cross-sectional view. The arrangement of the array of the first and second connectors (1121 and 1122) of the first IC die 110A may be essentially mirrored onto the first IC die 110B by reflection, and vice versa. For example, the first connector 1121 of the first IC die 110A is set in the right part of the lateral range of the semiconductor substrate 111 and the second connector 1122 of the first IC die 110A is set in the left part, while the first connector 1121 of the first IC die 110B is set in the left part of the lateral range of the semiconductor substrate 111 and the second connector 1122 of the first IC die 110B is set in the right part.

[0031] The first and second connectors (1121 and 1122) may be similar to Figure 1. For example, the pitch of the first connector 1121 is substantially equal to the pitch P1, and the pitch of the second connector 1122 is substantially equal to the pitch P2, wherein the pitch P1 is less than the pitch P2. Although the layers of the corresponding die connectors 112 are not individually labeled in the drawings, each of the first and second connectors (1121 and 1122) may include a seed layer, a first metallization layer, a second metallization layer, and a third metallization layer sequentially formed on the semiconductor substrate 111. For example, the corresponding first IC die 110 is picked up and placed on the first and second conductive bumps (101' and 102'), and then the die connector 112 is bonded to the first and second conductive bumps (101' and 102') by a thermal compression bonding process or any suitable technique. For example, heat is applied to the structure until the third metallization layer of the corresponding first connector 1121 and the third metallization layer 1014 of the corresponding one of the first conductive bumps 101' are melted and bonded together, and then the bonded bumps are cooled and solidified to form the corresponding first conductive joints 111J. Similarly, the third metallization layer of the corresponding second connector 1122 and the third metallization layer 1024 of the corresponding one of the second conductive bumps 102' are heated and bonded together to form the corresponding second conductive joints 112J. For example, the first and second conductive joints (111J and 112J) are solder joints. Thus, the first connector 1121 is bonded to corresponding ones of the first conductive bumps 101' and the second connector 1122 is bonded to corresponding ones of the second conductive bumps 102'.

[0032] Continue to refer to Figure 2, a first bottom filler 121 may be formed on the first temporary carrier 51 to surround the first and second conductive contacts (111J and 112J), the corresponding die connector 112 of the first IC die 110, and the first and second conductive bumps (101' and 102'). The first bottom filler 121 may include a liquid epoxy resin. For example, the bottom filler material is dispensed onto the first temporary carrier 51 of the adjacent first IC die 110, and then begins to diffuse and move by capillary phenomena to fill the gap between the first IC die 110 and the first and second conductive bumps (101' and 102'), and then the bottom filler material is cured and hardened to form the first bottom filler 121. The first bottom filler 121 may climb upward to cover at least a portion of the sidewall 110s of one or more first IC dies 110. In some embodiments, the sidewall of each of the first and second conductive contacts (111J and 112J) is a convex sidewall protruding toward the first bottom filler 121. The left portion of the first underfill 121 covering the first IC die 110A may (or may not) be continuously connected to the right portion of the first underfill 121 covering the first IC die 110B, depending on the amount of underfill material applied and the spacing between adjacent first IC dies 110. Alternatively, the first underfill 121 may be omitted.

[0033] Still refer to Figure 2 , a first insulating encapsulant 131 may be formed on the first temporary carrier 51 to laterally cover the first bottom filler 121 and the exposed portion of the first IC die 110. The first insulating encapsulant 131 may include an epoxy resin, a molded bottom filler, an organic polymer, a polymer with (or without) a filler, or any suitable insulating material, and may be formed by compression molding, transfer molding, or any suitable method. In some embodiments where the first bottom filler is not formed, a molded bottom filler material is used as the first insulating encapsulant 131, and the space originally filled by the first bottom filler is filled by the molded bottom filler material. In some embodiments, a planarization process is performed to make the first insulating encapsulant 131 flush with the first IC die 110. The planarization process may include chemical mechanical polishing (CMP), grinding, etching, a combination thereof, and the like. The first surface 131 a of the first insulating encapsulation 131 may be substantially flush (or coplanar) with the rear surface 110 r of the first IC die 110 (eg, the rear surface 111 r of the semiconductor substrate 111 ) within a process variation range.

[0034] Reference Figure 3 And refer to Figure 2 , reversible Figure 2The resulting structure shown in FIG. 1 is a schematic diagram of a first embodiment of the present invention, and the first surface 131a of the first insulating encapsulation body 131 and the rear surface 110r of the first IC die 110 can be attached to the second temporary carrier 53 through, for example, the second release layer 54. The second temporary carrier 53 can be similar to Figure 1 The first temporary carrier 51 described in . The second release layer 54 may include sublayers, such as an LTHC film 541 and an adhesive film 542 overlying the LTHC film 541. Alternatively, the second release layer 54 is a single layer (such as an LTHC film or a die bonding film). The first temporary carrier 51 can be removed by peeling off the first release layer 52. For example, the first release layer 52 is an LTHC layer, and suitable light illumination (such as ultraviolet (UV) light, laser, etc.) can be applied to weaken the bonding of the LTHC material so that the first temporary carrier 51 can be separated from the remaining structure. In some embodiments where the first release layer 52 is an adhesive, a suitable solvent can be used to dissolve the first release layer 52, thereby removing the first temporary carrier 51 from the overlying structure. Alternatively, the removal process of the first temporary carrier 51 and the first release layer 52 includes mechanical peeling, grinding, etching, and may include an additional cleaning process. After the removal process, the first insulating encapsulation 131, the first bottom filler 121, and the first and second conductive bumps (101' and 102') can be exposed in a touchable manner. For example, the second surface 131b of the first insulating encapsulation 131 (e.g., opposite to the first surface 131a) and the surface 121b of the first bottom filler 121 are substantially flush (or coplanar) within the process variation range.

[0035] Continue to refer to Figure 3 And refer to Figure 1 , a portion of each of the first and second conductive bumps (101' and 102') may be removed to form a corresponding first conductive bump 101 and a corresponding second conductive bump 102. As shown in the enlarged view, the first and second conductive bumps (101 and 102) are recessed from the surface 121b of the first bottom filler 121, and the inner sidewall 121s of the first bottom filler 121 may be exposed in an accessible manner. For example, at least the first sublayer 1011a of the corresponding seed layer 1011 and at least the first sublayer 1021a of the corresponding seed layer 1021 are removed by an etching process, while a photomask (not shown) protects the first bottom filler 121 and the first insulating encapsulation body 131 from being etched, and then the photomask is removed after etching. For example, a selective etching process is performed to remove the first sub-layer (1011a and 1021a) (e.g., titanium layer), while the second sub-layer (1011b and 1021b) below can remain substantially intact. Alternatively, the second sub-layer (1011b and 1021b) can also be etched to reveal the first metallization layer (1012 and 1022) below.

[0036] Reference Figure 4 And refer to Figure 3 , a plurality of metallization layers may be sequentially formed on a specific group of the second conductive bumps 102 to form the third conductive bumps 103'. For example, a seed layer 1031 is formed on the exposed surface of the second sub-layer 1021b. The seed layer 1031 may include a first sub-layer 1031a (e.g., a titanium film) and a second sub-layer 1031b (e.g., a copper film) overlying the first sub-layer 1031a. Alternatively, the seed layer 1031 is a single layer formed of copper or a copper alloy. For example, a material layer of the first sub-layer 1031a is conformally formed on the second surface 131b of the first insulating encapsulation 131, the surface 121b and the inner sidewall 121s of the first bottom filler 121, and the exposed surface of the second sub-layer 1021b, and then a material layer of the second sub-layer 1031b is formed on the material layer of the first sub-layer 1031a. Next, a photoresist (not shown) having an opening may be formed on the material layer of the second sub-layer 1031b. A first metallization layer 1032 (e.g., a copper layer), a second metallization layer 1033 (e.g., a nickel layer), and a third metallization layer 1034 (e.g., a solder layer) may be sequentially formed in the openings of the photoresist and on the exposed portions of the seed material layer directly above a particular group of second conductive bumps 102. The photoresist and portions of the seed material layer on which those metallization layers are not formed may then be removed. A reflow process may be selectively performed to shape the third metallization layer 1034 into a desired shape. The remaining portions of the seed material layer and the overlying metallization layer may be formed into a third conductive bump 103'. It should be noted that other methods for forming the third conductive bump 103' may also be available and are fully included within the scope of the present invention.

[0037] Reference Figure 5 And refer to Figure 4, the passive component 140 may be selectively attached to the third conductive bump 103' by, for example, a pick and place process followed by a reflow process or any suitable method. The passive component 140 may be or may include an integrated passive device (IPD), a surface mount device (SMD), a passive component (e.g., a capacitor, an inductor, a resistor, or the like), etc. For example, the passive component 140 includes a die connector 142, and the corresponding die connector 142 includes a first metallization layer 1421, a second metallization layer 1422 overlying the first metallization layer 1421, and a third metallization layer (not shown separately; for example, a solder layer) overlying the second metallization layer 1422. The third metallization layer and the third metallization layer 1034 may be joined together by, for example, reflow or the like to form a third conductive contact 113J. Alternatively, the steps of forming the third conductive bump 103 and attaching the passive component 140 to the third conductive bump 103 are skipped. In some embodiments, the second underfill 122 is formed in the gap between the passive component 140 and the surface 121b of the first underfill 121 to surround the die connector 142, the third conductive contact 113J, and the third conductive bump 103. The second underfill 122 may be similar to the first underfill 121. In some embodiments, the sidewalls of the corresponding third conductive contacts 113J are convex sidewalls protruding toward the second underfill 122. Alternatively, the second underfill 122 may be omitted.

[0038] In some embodiments, at least one second IC die 150' is attached to the first conductive bump 101 by pick and place, such as by thermal compression bonding. The second IC die 150' can provide electrical routing and connection between the first IC die 110. For example, the second IC die 150' is called an interconnect die, a bridge die, or a local interconnect member. The second IC die 150' can increase the communication bandwidth between the first IC die 110 while maintaining low contact resistance and high reliability. After the passive component 140 is coupled to the third conductive bump 103', the second IC die 150' can be attached to the first conductive bump 101. Alternatively, the bonding of the second IC die 150' is performed before the bonding of the passive component 140.

[0039] The second IC die 150 may include a semiconductor substrate 151' and die connectors 152 distributed over the semiconductor substrate 151'. The semiconductor substrate 151' may be similar to Figure 1The semiconductor substrate 111 described in the above. The semiconductor substrate 151' may include a device (e.g., a capacitor, a diode, a transistor, a resistor, an inductor, etc.) or may not have a device. The die connector 152 may have a pitch P3 (e.g., less than 20 μm), which may be substantially equal to the pitch P1 of the first conductive bump 101' (see Figure 1 ). The corresponding die connector 152 may include a first metallization layer 1521, a second metallization layer 1522 overlying the first metallization layer 1521, and a third metallization layer (not shown separately; for example, a solder layer) overlying the second metallization layer 1522. In some embodiments, the second metallization layer 1522 may be omitted. The third metallization layer may be disposed on the second sublayer 1011b of the corresponding first conductive bump 101, and a reflow process may be performed on the third metallization layer to form a fourth conductive contact 114J, which bonds the die connector 152 to the corresponding first conductive bump 101.

[0040] Continue to refer to Figure 5 , the corresponding fourth conductive contact 114J may include a first portion 1141 physically connected to the first conductive bump 101 and a second portion 1142 overlying the first portion 1141 and physically connected to the die connector 152. The first portion 1141 may be laterally covered by the first underfill 121 and have a substantially vertical sidewall 1141s adjacent to the inner sidewall 121s of the first underfill 121. The second portion 1142 may protrude upward from the first underfill 121 and may have a curved sidewall 1142s connected to the substantially vertical sidewall 1141s. The third underfill 123 may be selectively formed in the gap between the second IC die 150' and the surface 121b of the first underfill 121 to surround the die connector 152, the fourth conductive contact 114J, and the first conductive bump 101. The third underfill 123 may be similar to the second underfill 122 and may (or may not) be formed in the same step of forming the second underfill 122. The third underfill 123 laterally covers the second portion 1142 of the corresponding fourth conductive contact 114J, and the curved sidewall 1142s of the second portion 1142 may be a convex sidewall protruding toward the third underfill 123. For example, the third underfill 123 is formed on the surface 121b of the first underfill 121 and climbs upward to cover at least a portion of the semiconductor substrate 151'. Alternatively, the third underfill 123 may be omitted.

[0041] Reference Figure 6 And refer to Figure 5, a thinning process (e.g., CMP, grinding, etc.) may be performed on the second IC die 150' to reduce the overall thickness, thereby forming a second IC die 150 having a rear surface 151b of the semiconductor substrate 151. For example, the maximum height of the second IC die 150 on the surface 121b of the first underfill 121 is less than the maximum height of the passive component 140 on the surface 121b of the first underfill 121. Alternatively, the maximum height of the second IC die 150 on the surface 121b of the first underfill 121 is greater than or substantially equal to the maximum height of the passive component 140 on the surface 121b of the first underfill 121. In some embodiments, the thinning process of the second IC die is skipped.

[0042] Reference Figure 7 And refer to Figure 6 , the electrical connector 160 may be formed on the remaining portion of the second conductive bump 102 and around the second IC die 150. A portion of the electrical connector 160 may be disposed between the second IC die 150 and the passive component 140 and may surround the passive component 140. In some embodiments, the electrical connector 160 includes a microbump, a ball grid array (BGA) connector, a solder ball, a metal pillar, a controlled collapse chip connection (C4) bump, a bump formed by electroless nickel-electroless palladium-immersion gold (ENEPIG) technology, etc. The electrical connector 160 may include a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, the like, or a combination thereof. In some embodiments, the corresponding electrical connector 160 includes a column portion 160P and a bump portion 160B overlying the column portion 160P, wherein the column portion 160P and the bump portion 160B may be made of different conductive materials. For example, the column portion 160P includes copper, copper alloy, etc., and the bump portion 160B includes a solder material.

[0043] In some embodiments, the corresponding electrical connector 160 is formed by first conformally forming a first sub-layer of seed material on the second conductive bump 102 and the first underfill 121, forming a second sub-layer of seed material on the first sub-layer, forming a patterned photoresist on the second sub-layer, plating a first metallization layer in the opening of the patterned photoresist, selectively forming a second metallization layer (not shown), forming a solder material, removing the patterned photoresist, removing the excess portion of the seed material on which the first metallization layer is not formed, and selectively reflowing the solder material to form a bump portion 160B. The remaining portion below the bump portion 160B forms a pillar portion 160P. For example, the pillar portion 160P includes at least a seed layer 1601 and a metallization layer 1602 overlying the seed layer 1601, wherein the seed layer 1601 includes a first sublayer 1601a that conformally covers the surface 121b and the inner sidewall 121s of the first underfill 121 and the exposed surface of the second conductive bump 102, and the seed layer 1601 also includes a second sublayer 1601b (e.g., a copper layer) overlying the first sublayer 1601a. ​​In some embodiments, a height 160H measured from the highest point of the bump portion 160B of the corresponding electrical connector 160 to the surface 121b of the first underfill 121 is greater than a height 150H measured from the thinned back surface 151b of the second IC die 150 to the surface 121b of the first underfill 121. In some embodiments, the height 160H is greater than a height 140H measured from the back surface 140 b of the passive component 140 to the surface 121 b of the first underfill 121 .

[0044] Continue to refer to Figure 7 and Figure 6 , the second temporary carrier 53 can be removed by, for example, peeling off the second release layer 54. For example, suitable light illumination can be irradiated to the second release layer 54 to separate the second temporary carrier 53 from the remaining structure, a suitable solvent can be used to dissolve the second release layer 54 to separate the second temporary carrier 53 from the remaining structure, or other suitable removal methods (such as mechanical stripping process, grinding process or etching process, etc.) can be used to remove the second temporary carrier 53. After removing the second temporary carrier 53 and the second release layer 54, the first surface 131a of the first insulating encapsulation 131 and the rear surface 110r of the first IC die 110 can be exposed in an accessible manner. In some embodiments, the first surface 131a of the first insulating encapsulation 131 and the rear surface 110r of the first IC die 110 are substantially flush (or coplanar) within the process variation range. A singulation process can be selectively performed to cut the resulting structure into individual semiconductor devices 10. The semiconductor device 10 may then be bonded to a packaging component (eg, an interposer, a packaging substrate, a printed circuit board, a package structure, and / or the like; not shown).

[0045] Other features and processes may also be included. For example, a test structure may be included to help verify the testing of a 3D package or 3DIC device. The test structure may include, for example, a test pad formed on a redistribution layer or substrate that allows the 3D package or 3DIC to be tested using a probe and / or a probe card, etc. Verification testing may be performed on intermediate structures and final structures. In addition, the structures and methods disclosed herein may be used in conjunction with test methods including intermediate verification of known good dies to increase yield and reduce costs.

[0046] Still refer to Figure 7 , the semiconductor device 10 may include a second IC die 150 stacked on and electrically coupled to the first IC die 110. The respective die connectors 152 of the second IC die 150 may be electrically coupled to the respective first connectors 1121 of the respective first IC die 110 through the first conductive bump 101, the first conductive contact 111J, and the fourth conductive contact 114J. The first conductive contact 111J, the first conductive bump 101, and the fourth conductive contact 114J collectively provide electrical interconnection on a vertical axis of the semiconductor device 10 and may collectively be considered as a conductive feature or first electrical connection V1. The first electrical connection V1 may have a first conductive bump 101 having a substantially vertical sidewall S3, a first conductive contact 111J formed on a first side S1 of the first conductive bump 101 and having a curved sidewall, and a fourth conductive contact 114J formed on a second side S2 of the first conductive bump 101 and having a curved sidewall.

[0047] The respective electrical connectors 160 may be electrically coupled to the respective second connectors 1122 of the respective first IC die 110 via the second conductive contacts 112J and the respective second conductive bumps 102, wherein the second conductive contacts 112J and the second conductive bumps 102 collectively provide electrical interconnections on the vertical axis of the semiconductor device 10 and may collectively be considered as conductive features or second electrical connections V2. For example, the pitch P1 of the first electrical connections V1 is less than the pitch P2 of the second electrical connections V2, wherein the first electrical connections V1 provide fine pitch interconnections. Each of the first electrical connections V1 and the second electrical connections V2 may be considered as a signal line routed in the Z direction between the first IC die 110 and the second IC die 150. Signal paths between the second IC die 150 and the first IC die 110 and between the electrical connector 160 and the first IC die 110 are shorter than those in conventional semiconductor devices in which stacked dies and electrical connectors are coupled together using a redistribution layer having signal lines routed in the X, Y, and Z directions. Manufacturing costs can be reduced by omitting the redistribution layer between the stacked IC dies.

[0048] The first conductive bumps 101 that couple the second IC die 150 to the first IC die 110 may have a fine pitch that substantially matches the pitch of the die connectors 152 of the second IC die 150 and the pitch of the first connectors 1121 of the first IC die 110. To achieve the fine pitch configuration of the first conductive bumps 101, when the first conductive bumps 101 are initially formed (see Figure 1 ), the offset of the first IC die 110 caused by the formation of the first insulating encapsulation 131 can be taken into account. For example, simulation and / or experimental methods can be used to generate calibration data for the offset. The first conductive bump 101 can be formed with an offset to compensate for the expected offset based on the calibration data.

[0049] It should be understood that as the spacing between die connectors of an IC die decreases, overlay control becomes more difficult because overlay shift may reduce device performance and / or cause reliability issues. By recessing the first conductive bump 101 from the surface 121b of the first underfill 121 (see FIG. Figure 3 ), the first portion 1141 of the corresponding fourth conductive contact 114J can be physically coupled to the first conductive bump 101 and constrained by the first bottom filler 121, thereby limiting the overlap offset and reducing misalignment. In this way, the overlap offset of the first conductive bump 101 and the corresponding tube core connector 152 can be about + / -1μm. Similarly, the corresponding second conductive bump 102 is recessed from the surface 121b of the first bottom filler 121, and the corresponding electrical connector 160 can respectively have a portion inserted into the first bottom filler 121 to make physical contact with the second conductive bump 102, thereby limiting the overlap offset and achieving better electrical performance. In this way, the overlap offset of the second conductive bump 102 and the corresponding electrical connector 160 can be about + / -2μm.

[0050] Figure 8-9 10A and 11A are schematic cross-sectional views showing intermediate steps during a process of forming a semiconductor device according to some embodiments. Unless otherwise specified, similar reference numerals in this embodiment represent Figures 1 to 7 In the illustrated embodiment, similar components are formed by similar processes and the following discussion is only directed to the differences. Therefore, the processes and applicable materials may not be repeated here.

[0051] Reference Figure 8 And refer to Figure 4 , Figure 8 The structure and Figure 4, except that the conductive column 260 may be formed on the rest of the second conductive bump 102. In some embodiments, the height of the corresponding conductive column 260 is greater than the height of the corresponding third conductive bump 103'. For example, the corresponding conductive column 260 may include a seed layer 2601 and a metallization layer 2602 overlying the seed layer 2601. The seed layer 2601 may include a first sublayer 2601a (e.g., a titanium layer) that conformally covers the surface 121b and the inner sidewall 121s of the first bottom filler 121 and the exposed surface of the second conductive bump 102. The seed layer 2601 may include a second sublayer 2601b (e.g., a copper layer) overlying the first sublayer 2601a. ​​The metallization layer 2602 may include copper or a copper alloy and may be formed by plating. However, any suitable conductive material and deposition process may be used to form the conductive column 260.

[0052] Reference Fig. 9 And refer to Figure 8 and Figure 5 , the passive component 240 may be coupled to the third conductive bump 103', and the second IC die 150' may be coupled to the first conductive bump 101. For example, the die connector 242 of the passive component 240 and the third conductive bump 103 are coupled together through the third conductive contact 113J, and the die connector 152 of the second IC die 150 and the first conductive bump 101 are coupled together through the fourth conductive contact 114J. The process of coupling the passive component 240 to the third conductive bump 103' and coupling the second IC die 150' to the first conductive bump 101 may be similar to Figure 5 The passive component 240 may be similar to the passive component 140, except that the passive component 240 may have a greater thickness, such as greater than 90 μm.

[0053] Reference Fig. 10A And refer to Fig. 9 , a second bottom filler 222 may be formed on the surface 121b of the first bottom filler 121 to surround the die connector 242, the third conductive bump 103, and the third conductive contact 113J. The die connector 242, the third conductive bump 103, and the third conductive contact 113J may be collectively regarded as a third electrical connection V3. In some embodiments, the second bottom filler 222 may climb upward to at least partially cover the sidewall 240s of the passive component 240, and may extend continuously between the third electrical connection V3 and the conductive pillar 260 adjacent to the third electrical connection V3. In the illustrated embodiment, adjacent conductive pillars 260 (i.e., the two conductive pillars 260 closest to the passive component 240) have sidewalls that are in physical contact with the second bottom filler 222. Depending on the amount of bottom filler material applied, the second bottom filler 222 may further extend to be interposed between the conductive pillars 260, as will be described later. Fig. 10BDescribed in .

[0054] In some embodiments, the third underfill 223 is formed on the surface 121b of the first underfill 121 to surround the die connector 152, the first conductive bump 101, and the fourth conductive contact 114J. The die connector 152, the first conductive bump 101, and the fourth conductive contact 114J may be collectively considered to be a vertical connection V1'. The third underfill 223 may climb upward to at least partially cover the sidewall 150s of the second IC die 150, and may extend continuously between the vertical connection V1' and the conductive pillar 260 adjacent to the vertical connection V1'. Similar to the second underfill 222, the third underfill 223 may be in physical contact with the sidewall of the adjacent conductive pillar 260, and depending on the amount of underfill material applied, the third underfill 223 may extend further, as will be described later. Fig. 10B The materials of the second bottom filler 222 and the third bottom filler 223 may be similar to Figure 2 The first underfill 121 described in .

[0055] The second bottom filler 222 and the third bottom filler 223 can be formed by dispensing or any suitable deposition process. The second bottom filler 222 and the third bottom filler 223 can be formed in the same dispensing step (or different steps). For example, when forming the third bottom filler 223, the dispensing tool 21D is positioned above the gap between the sidewall 150s of the second IC tube core 150' and one of the adjacent conductive pillars 260, and then the bottom filler material flows out from the dispensing tool 21D to surround the vertical connection V1' and can extend toward the adjacent conductive pillar 260. A curing process can be performed on the bottom filler material to cure. In some embodiments, the coverage area of ​​the third bottom filler 223 on the sidewall 150s of the second IC tube core 150' near the position of the dispensing tool 21D is greater than the coverage area of ​​the third bottom filler 223 on the opposite sidewall 150s of the second IC tube core 150'. For example, in the cross section, the profile of the third underfill 223 on the two opposite sidewalls 150s of the second IC die 150' is asymmetric, wherein the highest point of the profile of the third underfill 223 on one of the sidewalls 150s is higher than the highest point of the profile of the third underfill 223 on the other of the sidewalls 150s. Similarly, in the cross section, the profile of the second underfill 222 on the two opposite sidewalls 240s of the passive component 240 is asymmetric, wherein the highest point of the profile of the second underfill 222 on one of the sidewalls 240s is higher than the highest point of the profile of the second underfill 222 on the other of the sidewalls 240s.

[0056] Reference Fig.11A And refer to Fig. 10AThe second insulating encapsulant 132 may be formed on the second surface of the first insulating encapsulant 131 and the surface 121b of the first bottom filler 121 to laterally cover the conductive pillars 260, the second IC die 150, the passive component 240, the second bottom filler 222, and the third bottom filler 223. The material and formation process of the second insulating encapsulant 132 may be the same as Figure 2 132 . In some embodiments, a planarization process (e.g., CMP, grinding, etching, a combination thereof, etc.) is performed to make the conductive pillars 260, the second IC die 150, and the passive components 240 flush. For example, the surface 132b of the second insulating encapsulation 132 is substantially flush (or coplanar) with the surface 260b of the conductive pillars 260, the rear surface 150b of the second IC die 150, and the rear surface 240b of the passive components 240 within the process variation range. In some embodiments, the thickness of the second IC die 150 'and the passive components 240 (and / or the height of the conductive pillars 260) can be reduced during the planarization process. The conductive pillars 260 can each penetrate the second insulating encapsulation 132 and can be referred to as through-insulating vias (TIVs) 260.

[0057] In some embodiments, a dielectric layer 272 is formed on the surface 132b of the second insulating encapsulation 132, the rear surface 150b of the second IC die 150, and the rear surface 240b of the passive component 240. The dielectric layer 272 can be formed of a polymer material, such as polybenzoxazole (PBO), polyimide (PI), benzocyclobutene (BCB), or other suitable materials that can be patterned using photolithography. In some embodiments, a conductive pattern 274 (e.g., a via or under bump metallization (UBM)) is formed through the dielectric layer 272 to physically and electrically contact the surface 260b of the conductive pillar 260. In some embodiments, an electrical connector 276 is formed on the conductive pattern 274 to electrically couple to the TIV 260. The electrical connector 276 can be a microbump, a BGA connector, a solder ball, a metal pillar, a C4 bump, a bump formed by ENEPIG technology, etc.

[0058] In some embodiments, the corresponding electrical connector 276 includes a column portion 276P and a bump portion 276B overlying the column portion 276P, wherein the column portion 276P and the bump portion 276B may be made of different conductive materials. For example, the bump portion 276B includes a solder material, and the column portion 276P may include a first metallization layer 2761 (e.g., a copper layer) and a second metallization layer 2762 (e.g., a nickel layer) overlying the first metallization layer 2761. Other conductive materials (e.g., tin, silver, nickel, gold, or the like) may be used to form the electrical connector 276. Next, the second temporary carrier 53 may be removed by peeling off the second release layer 54. The peeling process of the second temporary carrier 53 may be similar to that of the first release layer 54. Figure 7 The process described in Fig.11A As shown, a semiconductor device 20A is then provided.

[0059] Fig. 10B and 11B Schematic cross-sectional views of intermediate steps during a process of forming another semiconductor device according to some embodiments are shown. Unless otherwise specified, similar reference numerals in this embodiment represent Figure 8-9 , 10A and 11A are similar components formed by similar processes and the following discussion is only for the differences. Therefore, the processes and applicable materials will not be repeated here.

[0060] Reference Fig. 10B And refer to Fig. 10A , Fig. 10B and Fig. 10A The difference between the resulting structures shown in is that the second bottom filler 322 and the third bottom filler 323 extend further on the surface 121b of the first bottom filler 121 than the second bottom filler 222 and the third bottom filler 223, respectively. For example, the third bottom filler 323 covers not only the conductive pillar 260 closest to the second IC die 150' (also referred to herein as the closest conductive pillar 260) but also covers at least a portion of the sidewalls of the adjacent conductive pillars 260 around the closest conductive pillar 260, depending on the dispensed amount of the bottom filler material supplied from the dispense tool 21D. Similarly, the second bottom filler 322 may cover not only the conductive pillar 260 closest to the passive component 240 (i.e., the closest conductive pillar 260) but also covers at least a portion of the sidewalls of the adjacent conductive pillars 260 around the closest conductive pillar 260.

[0061] Reference Fig. 11B And refer to Fig. 10B and Fig.11A, the second insulating encapsulant 132 may be formed to laterally cover the conductive pillars 260, the second IC die 150, the passive components 240, the second underfill 322, and the third underfill 323. The dielectric layer 272, the conductive pattern 274, and the electrical connector 276 may be sequentially formed on the second insulating encapsulant 132 and the TIV 260. The materials and formation processes of the second insulating encapsulant 132, the dielectric layer 272, the conductive pattern 274, and the electrical connector 276 may be the same as those of the embodiment of the present invention. Fig.11A The same components as those described in Fig. 11B As shown, a semiconductor device 20B is then provided. The difference between the semiconductor device 20B and the semiconductor device 20A includes that the second underfill 322 and the third underfill 323 of the semiconductor device 20B can be diffused to cover more TIVs 260 near the second IC die 150 and the passive components 240. The second insulating encapsulant 132 can cover the exposed portions of the TIVs 260, which allows the second underfill 322 and the third underfill 323 to diffuse to a larger area without causing reliability issues.

[0062] Fig. 12A and 12B Schematic cross-sectional views of variations of semiconductor devices according to some embodiments are shown. Unless otherwise specified, similar reference numerals in this embodiment represent Fig. 10A and Fig.11A In the illustrated embodiment, similar components are formed by similar processes and the following discussion is only directed to the differences. Therefore, the processes and applicable materials may not be repeated here.

[0063] Reference Fig. 12A And refer to Fig.11A, semiconductor device 30A is similar to semiconductor device 20A, except that second IC die 250 includes at least one capacitor structure 254 and may include through substrate vias (TSVs) 255. For example, capacitor structure 254 is formed in semiconductor substrate 151 or in an interconnect structure (not shown separately). In some embodiments, capacitor structure 254 is a deep-trench capacitor (DTC). Capacitor structure 254 may be included in second IC die 250 to reduce noise and stabilize signals. In some embodiments, conductive pattern 374 formed in dielectric layer 272 may include a first portion 3741 connected to electrical connector 276 and TIV 260 and a second portion 3742 connected to electrical connector 276 and TSV 255. TSVs 255 may each penetrate semiconductor substrate 151 to provide vertical and electrical connections between conductive pattern 374 and die connector 152. Although the first portion 3741 is shown as a through-hole form and the second portion 3742 is shown as a pad form, the present invention is not limited thereto.

[0064] Reference Fig. 12B And refer to Fig. 12A , the semiconductor device 30B is similar to the semiconductor device 30A, and the difference between the two is that the semiconductor device 30B includes a redistribution structure 370 formed on the second insulating package 132, the TIV 260, the second IC die 250, and the passive component 240. The redistribution structure 370 may include alternately stacked patterned dielectric layers 3711 and patterned conductive layers 3712. The redistribution structure 370 is shown as an example having four patterned dielectric layers 3711 and four patterned conductive layers 3712, but more (or fewer) patterned dielectric layers and patterned conductive layers may be formed. The material of the patterned dielectric layer 3711 may be or include a photosensitive material, such as PBO, PI, BCB, a combination thereof, etc. The material of the patterned conductive layer 3712 may be or include copper, nickel, titanium, an alloy, a combination thereof, etc. The patterned conductive layer 3712 may include vias, wires, conductive pads, etc.

[0065] The bottommost one of the patterned conductive layers 3712 may be in physical and electrical contact with the TIV 260. In some embodiments, the bottommost one of the patterned conductive layers 3712 is electrically coupled to the TSV 255 of the second IC die 250. Alternatively, the TSV 255 and / or the capacitor structure 254 may be omitted. In some embodiments, the topmost one of the patterned conductive layers 3712 includes a UBM pattern 3712a and / or a conductive bump 3712b. In some embodiments, an electrical connector 380 is formed on the UBM pattern 3712a. The electrical connector 380 may include a microbump, a BGA connector, a solder ball, a metal pillar, a C4 bump, a bump formed by ENEPIG technology, etc. In some embodiments, at least one passive component 340 is attached to the redistribution structure 370 by coupling the die connector 342 of the passive component 340 to the conductive bump 3712b through a fifth conductive contact 115J (e.g., a solder contact). A fourth underfill 124 may be selectively formed on the redistribution structure 370 to laterally cover the die connector 342 and the fifth conductive contact 115J.

[0066] Figures 13 to 20 Schematic cross-sectional views of intermediate steps during a process of forming a semiconductor package according to some embodiments are shown. Unless otherwise specified, similar reference numerals in this embodiment represent Figures 1 to 7 In the illustrated embodiment, similar components are formed by similar processes and the following discussion is only directed to the differences. Therefore, the processes and applicable materials may not be repeated here.

[0067] Reference Fig.13 And refer to Figure 1 , Fig.13 and Figure 1The difference between the resulting structures shown is that the first conductive pillar 261 is formed in the third region R3, wherein the third region R3 may surround the second region R2, and the second region R2 surrounds the first region R1. In some embodiments, the first conductive pillar 261 is formed before forming the first and second conductive bumps (101' and 102'). The first conductive pillar 261 may be higher than the first and second conductive bumps (101' and 102'). In some embodiments, the formation of the first conductive pillar 261 includes forming a seed material layer on the first temporary carrier 51, forming a patterned photoresist (not shown) on the seed material layer, plating a metallization layer in the opening of the patterned photoresist, and removing the patterned photoresist. The seed material layer may be retained for forming the first and second conductive bumps (101' and 102'), and when the patterned photoresist used to form the first and / or second conductive bumps (101' and 102') is removed, the excess portion of the seed material layer may be removed by, for example, etching, etc., wherein the metallization layer is not formed on the excess portion. Alternatively, the first conductive pillar 261 is pre-formed and / or the first conductive pillar 261 may be placed at a predetermined position before / after forming the first and second conductive bumps ( 101 ′ and 102 ′).

[0068] Reference Fig.14 And refer to Fig.13 and Figure 2 , the first IC die 110 may be disposed on the first and second conductive bumps (101' and 102') and electrically coupled to the first and second conductive bumps (101' and 102'). For example, the first connector 1121 of the corresponding first IC die 110 is coupled to the first conductive bump 101' through the first conductive contact 111J, and the second connector 1122 of the corresponding first IC die 110 is coupled to the second conductive bump 102' through the second conductive contact 112J. The first bottom filler 121 may be selectively formed on the first temporary carrier 51 to surround the die connector 112, the first and second conductive contacts (111J and 112J), and the first and second conductive bumps (101' and 102'). The coupling process of the first IC die 110 and the formation process of the first bottom filler 121 may be similar to Figure 2 The process described in .

[0069] The first insulating encapsulation 231 may be formed over the first temporary carrier 51 to laterally cover the first conductive pillars 261, the first IC die 110, and the first underfill 121. The material and formation process of the first insulating encapsulation 231 may be similar to Figure 2In some embodiments, a planarization process (e.g., CMP, grinding, etching, a combination thereof, etc.) is performed to make the first insulating encapsulation 231, the first conductive pillar 261, and the first IC die 110 flush. For example, the first surface 231a of the first insulating encapsulation 231 is substantially flush (or coplanar) with the first surface 261a of the first conductive pillar 261 and the rear surface 110r of the first IC die 110 within the process variation range. The first conductive pillar 261 that penetrates the first insulating encapsulation 231 can be referred to as a first TIV.

[0070] Reference Fig.15 And refer to Fig.14 and Figure 3 , reversible Fig.14 The resulting structure is shown, and the first surface 231a of the first insulating encapsulant 231, the first surface 261a of the first TIV 261, and the rear surface 110r of the first IC die 110 can be attached to the second temporary carrier 53 through, for example, the second release layer 54. The first temporary carrier 51 can be removed by peeling off the first release layer 52, thereby revealing the second surface 231b of the first insulating encapsulant 231, the second surface 261b of the first TIV 261, and the surface 121b of the first underfill 121. The bonding of the second temporary carrier 53 and the peeling off of the first temporary carrier 51 can be similar to Figure 3 In some embodiments, portions of the first and second conductive bumps (101' and 102') are removed to form first and second conductive bumps (101 and 102) recessed from the surface 121b of the first underfill 121. The removal process may be similar to Figure 3 In some embodiments, during the removal of portions of the first and second conductive bumps (101' and 102'), portions of the first TIV 261 (e.g., the titanium sublayer of the seed layer) may also be removed, so that the second surface 261b of the first TIV 261 may be recessed from the second surface 231b of the first insulating encapsulant 231. Alternatively, during the removal of portions of the first and second conductive bumps (101' and 102'), a photoresist (not shown) may cover the first TIV 261 for protection.

[0071] Reference Fig.16 And refer to Fig.15 and Figure 8 , the second conductive pillar 262 may be formed on the first TIV 261 and the third conductive pillar 263 may be formed on the second conductive bump 102. For example, the corresponding third conductive pillar 263 includes a seed layer 2631 (including a first sub-layer 2631a and a second sub-layer 2631b) and a metallization layer 2632 overlying the seed layer 2631. The formation of the third conductive pillar 263 may be similar to Figure 8 . The second conductive pillar 262 may be formed in the same step as the third conductive pillar 263. Alternatively, the second conductive pillar 262 is formed before (or after) the third conductive pillar 263 is formed. In some embodiments, the corresponding second conductive pillar 262 has a maximum lateral size (e.g., width or diameter) 262W, which is larger than the maximum lateral size 261W of the first TIV 261 below. The corresponding second conductive pillar 262 may be substantially aligned with the first TIV 261 below. Alternatively, the center of the corresponding second conductive pillar 262 is laterally offset from the center of the first TIV 261 below. In some embodiments, the corresponding third conductive pillar 263 has a maximum lateral size (e.g., width or diameter) 263W, which is larger than the maximum lateral size 102W of the second conductive bump 102 below.

[0072] Reference Fig.17 And refer to Fig.16 and Figure 5-6 , the second IC die 150 may be disposed on the first conductive bump 101 and electrically coupled to the first conductive bump 101. For example, the die connector 152 of the second IC die 150 is bonded to the first conductive bump 101 through the fourth conductive contact 114J. The third underfill 123 may be selectively formed to surround the die connector 152 and the fourth conductive contact 114J. Bonding the second IC die 150 to the first conductive bump 101 and forming the third underfill 123 may be similar to Figure 5-6 Next, a second insulating encapsulation 232 may be formed on the first insulating encapsulation 231 to laterally cover each of the second and third conductive pillars (262 and 263), the second IC die 150, and the third bottom filler 123. A portion of the second insulating encapsulation 232 may be interposed between the third bottom filler 123 and the adjacent third conductive pillar 263, thereby completely separating the third bottom filler 123 from the third conductive pillar 263. The material and formation process of the second insulating encapsulation 232 may be similar to those of the first insulating encapsulation 231.

[0073] In some embodiments, the surface 232a of the second insulating encapsulant 232, the surface 262a of the second conductive pillar 262, the surface 263a of the third conductive pillar 263, and the rear surface 150b of the second IC die 150 are planarized to be substantially flush (or coplanar) with each other within a process variation range. In some embodiments, the third underfill 123 is Fig. 10A The third underfill 223 described in Fig. 10BIn this case, the adjacent third conductive pillar 263 may have an upper sidewall covered by the second insulating encapsulation 232 and a lower sidewall covered by the third bottom filler 223 / 323. The second and third conductive pillars (262 and 263) penetrating the second insulating encapsulation 232 may be referred to as the second TIV 262 and the third TIV 263, respectively.

[0074] Reference Fig.18 And refer to Fig.17 and Fig. 12B , a redistribution structure 370 including a patterned dielectric layer 3711 and a patterned conductive layer 3712 can be formed on the second insulating encapsulation 232, the second and third TIVs (262 and 263), and the second IC die 150. For example, the lowermost one of the patterned dielectric layers 3711 is physically and electrically coupled to the second and third TIVs (262 and 263). In some embodiments, the passive component 340 is attached to the redistribution structure 370. The fourth bottom filler 124 can be selectively formed in the gap between the redistribution structure 370 and the passive component 340. In some embodiments, the electrical connector 380 is formed in the uppermost one of the patterned conductive layers 3712 and surrounds the passive component 340. The formation process of the redistribution structure 370, the attachment of the passive component 340, and the formation process of the electrical connector 380 can be similar to Fig. 12B The process described in .

[0075] Reference Fig.19 And refer to Fig.18 , the second temporary carrier 53 can be removed by, for example, peeling off the second release layer 54. The peeling process of the second temporary carrier 53 can be similar to Figure 7 Once the second temporary carrier 53 and the second release layer 54 are removed, the first surface 231a of the first insulating encapsulation 231, the first surface 261a of the first TIV 261, and the rear surface 110r of the first IC die 110 are exposed in an accessible manner. The resulting structure can be flipped over and the electrical connector 380 can be attached to the tape 55, which is supported by the frame 56 for further processing. The tape 55 can be a dicing tape and the frame 56 can be a dicing frame.

[0076] Reference Fig. 20 And refer to Fig.19, the upper package component 420 may be disposed on the first insulating encapsulation 231, the first TIV 261, and the first IC die 110. For example, the conductive terminal 422 of the upper package component 420 is physically and electrically coupled to the first TIV 261. The bottom filler 125 may be selectively formed in the gap between the upper package component 420 and the underlying structure to surround the conductive terminal 422. The upper package component 420 may include a memory die (not shown) and may be referred to as a memory package. In some embodiments, the aforementioned steps are performed in the form of a wafer, and the resulting structure is cut by a singulation process (e.g., sawing, laser cutting, etching, a combination thereof, etc.), thereby separating the resulting structure into individual semiconductor packages 40. For example, the singulation process is performed to cut off the first insulating encapsulation 231, the second insulating encapsulation 232, and the redistribution structure 370. In some embodiments, the singulation process is performed while the electrical connector 380 is attached to the tape 55 , and after the singulation, the electrical connector 380 is peeled off from the tape 55 .

[0077] In some embodiments, the structures below the upper package component 420 are collectively considered as the lower package component 410, which can be referred to as an integrated fan-out (InFO) package. The semiconductor package 40 can be referred to as an InFO package-on-package (PoP). It should be understood that Fig. 20 The semiconductor package 40 shown is only an example, and the bonding configuration of the first and second IC tube cores described in this article can be applied to any suitable package type, such as a system-on-chip (SoC) package, a chip-on-wafer (CoW) package, a chip-on-wafer-on-substrate (CoWoS) package, etc.

[0078] Figures 21 to 25 Schematic cross-sectional views of intermediate steps during a process of forming another semiconductor package according to some embodiments are shown. Unless otherwise specified, similar reference numerals in this embodiment represent Figures 13 to 20 In the illustrated embodiment, similar components are formed by similar processes and the following discussion is only directed to the differences. Therefore, the processes and applicable materials may not be repeated here.

[0079] Reference Fig.21 And refer to Fig.14 ,like Fig.14After forming the first insulating encapsulation 231, a backside rewiring structure 470 may be formed on the first surface 231a of the first insulating encapsulation 231, the first surface 261a of the first TIV 261, and the rear surface 110r of the first IC die 110. The backside rewiring structure 470 may be similar to Fig. 12B . The back side redistribution structure 470 may include alternatingly stacked patterned dielectric layers 4711 and patterned conductive layers 4712. The back side redistribution structure 470 is shown as an example having three patterned dielectric layers 4711 and two patterned conductive layers 4712, but more (or fewer) patterned dielectric layers and patterned conductive layers may be formed. The lowermost one of the patterned conductive layers 4712 may be physically and electrically coupled to the first surface 261a of the first TIV 261. At this stage, the uppermost one of the patterned conductive layers 4712 may be completely covered by the uppermost one of the patterned dielectric layers 4711.

[0080] Reference Fig. 22 And refer to Fig.21 and Fig.15 , reversible Fig.21 The resulting structure is shown, and the uppermost one of the patterned dielectric layers 4711 of the back side redistribution structure 470 can be attached to the second temporary carrier 53 through, for example, the second release layer 54. The first temporary carrier 51 can be removed by peeling off the first release layer 52, thereby revealing the second surface 231b of the first insulating encapsulation 231, the second surface 261b of the first TIV 261, and the surface 121b of the first bottom filler 121. The bonding of the second temporary carrier 53 and the peeling off of the first temporary carrier 51 can be similar to Figure 3 In some embodiments, portions of the first and second conductive bumps (101' and 102') are removed to form first and second conductive bumps (101 and 102) recessed from the surface 121b of the first underfill 121. The removal process may be similar to Figure 3 or Fig.15 The process described in .

[0081] Reference Fig.23 And refer to Fig. 22 and Figure 16-17, a second TIV 262 may be formed on the first TIV 261, and a third TIV 263 may be formed on the second conductive bump 102. The die connector 152 of the second IC die 150 may be disposed on the first conductive bump 101 and electrically coupled to the first conductive bump 101 through the fourth conductive contact 114J. The third underfill 123 may be selectively formed to surround the die connector 152 and the fourth conductive contact 114J. Subsequently, a second insulating encapsulation 232 may be formed on the first insulating encapsulation 231 to laterally cover each of the second and third conductive pillars (262 and 263), the second IC die 150, and the third underfill 123. The formation of the second and third TIVs (262 and 263), the coupling of the second IC die 150, and the formation of the second insulating encapsulation 232 may be similar to Figure 16-17 The process described in .

[0082] Reference Fig.24 And refer to Fig.23 and Fig.18 , a redistribution structure 370 including a patterned dielectric layer 3711 and a patterned conductive layer 3712 may be formed on the second insulating encapsulation 232, the second and third TIVs 262 and 263, and the second IC die 150. In some embodiments, the passive component 340 is attached to the redistribution structure 370. The fourth underfill 124 may be selectively formed in a gap between the redistribution structure 370 and the passive component 340. In some embodiments, an electrical connector 380 is formed on the uppermost one of the patterned conductive layers 3712 and surrounds the passive component 340. The formation process of the redistribution structure 370, the attachment of the passive component 340, and the formation process of the electrical connector 380 may be similar to Fig.18 The process described in .

[0083] Reference Fig.25 And refer to Fig.24 and Figure 19-20 , the second temporary carrier 53 can be removed by peeling off the second release layer 54. Once the second temporary carrier 53 and the second release layer 54 are removed, the uppermost one of the patterned dielectric layers 4711 of the back side redistribution structure 470 can be exposed in an accessible manner. The resulting structure can be turned over, and the electrical connector 380 can be attached to the tape, which is supported by a frame (such as Fig.194711p). The uppermost one of the patterned dielectric layers 4711 may be patterned to form an opening 4711p. Subsequently, the upper package component 420 may be disposed on the back side redistribution structure 470 and electrically coupled to the back side redistribution structure 470. For example, the conductive terminal 422 of the upper package component 420 is inserted into the opening 4711p to make physical and electrical contact with the uppermost one of the patterned conductive layers 4712. The bottom filler 125 may be selectively formed in the gap between the upper package component 420 and the back side redistribution structure 470 to surround the conductive terminal 422.

[0084] The above process is similar to Figure 19-20 In some embodiments, Figure 21-25 The aforementioned steps described in the foregoing are performed in a wafer form, and the resulting structure is cut by a singulation process, thereby separating the resulting structure into individual semiconductor packages 50. In some embodiments, the corresponding semiconductor package 50 includes an upper package component 420 stacked on and electrically coupled to a lower package component 510. The semiconductor package 50 may be similar to the embodiment of the present invention, except that the lower package component 510 also includes a backside redistribution structure 470 connecting the upper package component 420 to the first TIV 261. Fig. 20 The semiconductor package 40 described in FIG.

[0085] Fig.26 and 27 Schematic cross-sectional views of intermediate steps during a process of forming another semiconductor device according to some embodiments are shown. Unless otherwise specified, similar reference numerals in this embodiment represent Figure 13-18 In the illustrated embodiment, similar components are formed by similar processes and the following discussion is only directed to the differences. Therefore, the processes and applicable materials may not be repeated here.

[0086] Reference Figure 26-27 and Figure 17-18 , except in Fig.26 In the structure of FIG. 1 , the first and second TIVs ( 261 and 262 ) are omitted and only TIV 260 is formed. Fig.26 The structure shown in Figure 13-17 The redistribution structure 370' may be formed on the second insulating encapsulation 232, the TIV 260, and the second IC die 150. The redistribution structure 370' including the patterned dielectric layer 3711' and the patterned conductive layer 3712' may be similar to Fig.18. The redistribution structure 370' is shown as an example having three patterned dielectric layers 3711' and three patterned conductive layers 3712', but more or fewer patterned dielectric layers and patterned conductive layers may be formed in the redistribution structure 370'. In some embodiments, the electrical connector 276 is formed on the uppermost one of the patterned conductive layers 3712' of the redistribution structure 370' to electrically couple to the TIV 260. The electrical connector 276 may be similar to Fig.11A The electrical connector 276 described in .

[0087] In some embodiments, after the electrical connection 276 is formed, the second temporary carrier 53 is removed by peeling off the second release layer 54. The above process is similar to Figure 19-20 In some embodiments, the aforementioned steps are performed in the form of a wafer, and the resulting structure is cut through a singulation process, thereby separating the resulting structure into individual semiconductor packages 60.

[0088] Figure 28 to Figure 31 Schematic cross-sectional views of intermediate steps during a process of forming a further semiconductor device according to some embodiments are shown. Like reference numerals in this embodiment represent like components from previous embodiments.

[0089] Reference Fig.28 , the first IC die 210 may be disposed on the first temporary carrier 51 by, for example, a pick-and-place process. In some embodiments, the rear surface 210r of the first IC die 210 is attached to the first temporary carrier 51 by a first release layer 52 (eg, a die attach film). The first IC die 210 may be similar to Figure 1 . For example, the corresponding first IC die 210 includes a semiconductor substrate 211, which may be similar to the semiconductor substrate 111. The corresponding first IC die 210 may include a passivation layer 213 disposed on the semiconductor substrate 211 and a conductive pad 214 disposed on the semiconductor substrate 211 and partially covered by the passivation layer 213. The conductive pad 214 may be an aluminum pad and the die connector 212 may land on the conductive pad 214 in a one-to-one manner. Similar to the die connector 112, the die connector 212 may include a first connector 2121 and a second connector 2122. The corresponding first IC die 210 may include a protective layer 215 formed on the passivation layer 213 and laterally covering each die connector 212.

[0090] In some embodiments, after placing the first IC die 210, the first insulating encapsulation 331 is formed on the first temporary carrier 51 to laterally cover the corresponding first IC die 210. The material and formation process of the first insulating encapsulation 331 may be similar to that in Figure 2 1. The first insulating encapsulation 131 described in the foregoing. For example, the first surface 331a in the first insulating encapsulation 331 and the active surface 210a of the corresponding first IC die 210 are planarized to be substantially flush (or coplanar) within a process variation range. The active surface 210a of the corresponding first IC die 210 may include a surface 2121a of the first connector 2121 and a surface 2122a of the second connector 2122. In some embodiments, the surface 215a of the protective layer 215 is substantially flush (or coplanar) with the surfaces (2121a and 2122a) of the first and second connectors (2121 and 2122).

[0091] Reference Fig.29 And refer to Fig.28 , the first conductive bump 201 may be formed on the first connector 2121 in a one-to-one manner, and the second conductive bump 202 may be formed on the second connector 2122 in a one-to-one manner. In some embodiments, the first and second conductive bumps (201 and 202) are formed by first forming a first sublayer (e.g., a titanium sublayer) of a seed material on the active surface 210a of the first IC die 210 and the first insulating encapsulation 331, forming a second sublayer (e.g., a copper layer) of the seed material on the first sublayer, forming a patterned photoresist on the second sublayer, plating a metallization layer (e.g., a copper layer) in the opening of the patterned photoresist, removing the patterned photoresist, and removing the excess portion of the seed material on which the metallization layer is not formed. The remaining portion forms the first and second conductive bumps (201 and 202). The first and second conductive bumps (201 and 202) may be referred to as first and second conductive pads. In some embodiments, the interface between the corresponding first conductive bump 201 and the underlying first connector 2121 and the interface between the corresponding second conductive bump 202 and the underlying second connector 2122 does not have solder material. In some embodiments, the lateral size (e.g., diameter or width) 201D of the first conductive bump 201 is greater than (or substantially equal to) the lateral size 2121D of the underlying first connector 2121. The lateral size (e.g., diameter or width) 202D of the second conductive bump 202 may be greater than (or substantially equal to) the lateral size 2122D of the underlying second connector 2122.

[0092] As described above, the formation of the first insulating encapsulation may cause a shift of the first IC die. The first conductive bump 201 and / or the second conductive bump 202 may be formed with an offset to compensate for the expected shift. Fig.29The structure in the dashed box in FIG. 1 shows various top views of the first and second conductive bumps (201 and 202) and the underlying die connector 212 as examples. For example, as shown in the dashed box A, the center C1 of the first conductive bump 201 and the center C2 of the underlying first connector 2121 are substantially aligned in the stacking direction of the first conductive bump 201 and the first connector 2121. In some embodiments, as shown in the dashed box B, the center C1 of the first conductive bump 201 and the center C2 of the underlying first connector 2121 are offset by a non-zero distance, and the first conductive bump 201 and the first connector 2121 completely overlap in the stacking direction of the first conductive bump 201 and the first connector 2121. In some embodiments, as shown in the dashed box C, the first conductive bump 201 and the first connector 2121 partially overlap in the stacking direction of the first conductive bump 201 and the first connector 2121, and a portion of the first connector 2121 is exposed by the first conductive bump 201 in a touchable manner.

[0093] In some embodiments, as shown in the dashed box D, the center C3 of the second conductive bump 202 is substantially aligned with the center C4 of the second connector 2122 below in the stacking direction of the second conductive bump 202 and the second connector 2122. In some embodiments, as shown in the dashed box E, the center C3 of the second conductive bump 202 is offset from the center C4 of the second connector 2122 below by a non-zero distance, and the second conductive bump 202 and the second connector 2122 completely overlap in the stacking direction of the second conductive bump 202 and the second connector 2122. In some embodiments, as shown in the top view of the dashed box F, the edge of the second conductive bump 202 may partially overlap with the edge of the second connector 2122. Although the first and second conductive bumps (201 and 202) and the first and second connectors (2121 and 2122) are shown as circles in the top view, it should be understood that the first and second conductive bumps (201 and 202) and the first and second connectors (2121 and 2122) may have any shape, such as a rectangle, a square, an ellipse, a polygon, etc.

[0094] Reference Fig.30 And refer to Fig.29 , at least one second IC die 350 ′ can be attached to the first conductive bump 201, wherein the second IC die 350 ′ can be similar to Figure 51 . For example, the second IC die 350' includes a semiconductor substrate 351', which is similar to the semiconductor substrate 151'. The second IC die 350 may include a passivation layer 353 disposed on the semiconductor substrate 351' and a plurality of conductive pads 354 disposed on the semiconductor substrate 351' and partially covered by the passivation layer 353. The conductive pads 354 may be aluminum pads and the die connectors 352 may land on the conductive pads 354 in a one-to-one manner. Similar to the die connectors 152, the die connectors 352 may be coupled to the first conductive bumps 201 via conductive contacts 116J (e.g., solder contacts). In some embodiments, the lateral size (e.g., diameter or width) 352D of the corresponding die connectors 352 is greater than (or substantially equal to) the lateral size 201D of the underlying first conductive bumps 201. In some embodiments, the corresponding conductive contact 116J may have a surface area coupled to the die connector 352 that is smaller than a surface area coupled to the first conductive bump 201 .

[0095] Reference Fig.31 And refer to Fig.30 , the bottom filler 423 may be formed in the gap between the first IC die 210 and the second IC die 350 to surround the first conductive bump 201, the conductive contact 116J and the die connector 352. The bottom filler 423 may be similar to Figure 6 In some embodiments, the bottom filler 423 is in physical contact with the portion of the die connector 212 of the first IC die 210 that is exposed by the first or second conductive bump (201 or 202) above. In some embodiments, the second IC die 350' is subjected to a thinning process to reduce the overall thickness, thereby forming a second IC die 350 having a thinned rear surface 350b. The thinning process may be similar to Figure 6 Alternatively, the thinning process is skipped.

[0096] In some embodiments, the electrical connector 160' may be formed on the second conductive bump 202. The electrical connector 160' may be similar to Figure 7. For example, the column portion 160P' of the corresponding electrical connector 160' lands on the second conductive bump 202. The lateral size (e.g., diameter or width) 160PD of the column portion 160P' may be smaller than the lateral size 202D of the second conductive bump 202 below. The column portion 160P' may include a seed layer 1601' overlying a surface 202b of the second conductive bump 202 and a metallization layer 1602 overlying the seed layer 1601'. In some embodiments, the second conductive bump 202 includes a seed layer 2021 at a surface 202a opposite to the surface 202b, wherein the surfaces (202a and 202b) are substantially flat.

[0097] Continue to refer to Fig.31 and Fig.30 , the first temporary carrier 51 can be removed by peeling off the first release layer 52. The peeling off of the first temporary carrier 51 can be similar to Figure 3 After removing the first temporary carrier 51 and the first release layer 52, the second surface 331b of the first insulating encapsulation 331 and the rear surface 210r of the first IC die 210 can be exposed in an accessible manner and can be substantially flush (or coplanar). A singulation process can be optionally performed to cut the resulting structure into individual semiconductor devices 70A.

[0098] Fig.32 Schematic cross-sectional views of another semiconductor device according to some embodiments are shown. Similar reference numerals in this embodiment represent similar components as in the previous embodiments. Fig.32 And refer to Fig.31 and Fig.11A The semiconductor device 70B is similar to the semiconductor device 70B except that the semiconductor device 70B further includes a second insulating encapsulation body 332 formed on the first insulating encapsulation body 331 to cover the second conductive bump 202, the TIV 260, the second IC die 350 and the bottom filler 423. Fig.31 The second insulating encapsulation body 332 may be similar to the semiconductor device 70A described in Fig.11A 1. In some embodiments, the surface 260b of the TIV 260 is substantially flush (or coplanar) with the surface 332b of the second insulating encapsulation 332 within a process variation range. The thinned rear surface 350b of the second IC die 350 may be completely covered by the second insulating encapsulation 332. Alternatively, the thinned rear surface 350b of the second IC die 350 may be flush (or coplanar) with the surface 332b of the second insulating encapsulation 332 within a process variation range.

[0099] In some embodiments, the semiconductor device 70B includes a dielectric layer 272 formed on the surface 260b of the TIV 260 and the surface 332b of the second insulating encapsulant 332. A conductive pattern 274 may be formed through the dielectric layer 272 to be in physical and electrical contact with the surface 260b of the TIV 260. In some embodiments, the semiconductor device 70B includes an electrical connector 276 formed on the conductive pattern 274 to be electrically coupled to the TIV 260. The dielectric layer 272, the conductive pattern 274, and the electrical connector 276 may be similar to Fig.11A The dielectric layer 272, conductive pattern 274 and electrical connection 276 described in FIG.

[0100] Figure 33 to Figure 37 Schematic cross-sectional views of intermediate steps during a process of forming a semiconductor device according to some embodiments are shown. Unless otherwise specified, similar reference numerals in this embodiment represent Figure 28-31 In the illustrated embodiment, similar components are formed by similar processes and the following discussion is only directed to the differences. Therefore, the processes and applicable materials may not be repeated here.

[0101] Reference Fig.33 , the first conductive bump 201 and the second conductive bump 202 may be formed on the first temporary carrier 51. As described in the previous embodiment, in order to achieve a fine pitch configuration, when forming the first and second conductive bumps (201 and 202), the offset of the first IC die subsequently attached due to the first insulating encapsulation formed subsequently may be considered. For example, simulation and / or experimental methods may be used to generate calibration data of the offset, and the first and second conductive bumps (201 and 202) are formed to have an offset to compensate for the expected offset based on the calibration data.

[0102] Reference Fig.34 And refer to Fig.33 , the first IC die 210 can be coupled to the first and second conductive bumps (201 and 202). For example, the first connector 2121 of the corresponding first IC die 210 is bonded to the first conductive bump 201 through the first conductive contact 117J, and the second connector 2122 of the corresponding first IC die 210 is bonded to the second conductive bump 202 through the second conductive contact 118J, wherein the first and second conductive contacts (117J and 118J) can be solder contacts.

[0103] Reference Fig.35 And refer to Fig.34, a first bottom filler 421 may be formed on the first temporary carrier 51 to cover the first and second conductive bumps (201 and 202) and the first and second conductive contacts (117J and 118J). Next, a first insulating encapsulant 431 may be formed on the first temporary carrier 51 to laterally cover the first IC die 120 and the first bottom filler 421. The first bottom filler 421 and the first insulating encapsulant 431 may be similar to Figure 2 . In some embodiments, the first surface 431a of the first insulating encapsulation 431 and the rear surface 210r of the first IC die 210 are planarized and are substantially flush (or coplanar) within a process variation range.

[0104] Reference Fig.36 And refer to Fig.35 , reversible Fig.35 The resulting structure is bonded to the second temporary carrier 53. For example, the first surface 431a of the first insulating encapsulation 431 and the rear surface 210r of the first IC die 210 are bonded to the second temporary carrier 53 through the second release layer 54. The first temporary carrier 51 can be removed by peeling off the first release layer 52 to expose the second surface 431b of the first insulating encapsulation 431, the surface 421b of the first underfill 421, and the surfaces (201b and 202b') of the first and second conductive bumps (201 and 202) in a touchable manner. The bonding process of the second temporary carrier 53 and the peeling process of the first temporary carrier 51 can be similar to Figure 3 The process described in Figure 3 As described above, the seed layers (not shown separately) of the corresponding first and second conductive bumps (201 and 202) may remain or may be partially removed.

[0105] Reference Fig.37 And refer to Fig.36 and reference Figure 30-31 , the die connector 352 of the second IC die 350 can be attached to the surface 201b of the first conductive bump 201 through the third conductive contact 116J'. The second bottom filler 423' can be selectively formed on the first bottom filler 421 to surround the die connector 352 and the third conductive contact 116J' of the second IC die 350 for protection. The electrical connector 160' can be formed on the second conductive bump 202 to surround the second IC die 350. Subsequently, the second temporary carrier 53 can be removed by peeling off the second release layer 54 to expose the first surface 431a of the first insulating encapsulation 431 and the rear surface 210r of the first IC die 210 in an accessible manner. The bonding of the second IC die 350, the formation of the second bottom filler 423', the formation of the electrical connector 160', and the peeling off of the second temporary carrier 53 can be similar to Figure 30-31 The process described in .

[0106] Fig.37 The semiconductor device 80A shown is similar to Fig.31 The semiconductor device 70A shown, the difference between the two includes that the opposite ends of the corresponding first conductive bump 201 of the semiconductor device 80A may have conductive contacts (e.g., 117J and 116J') formed thereon, and the end of the corresponding second conductive bump 202 of the semiconductor device 80A facing the first IC die 210 may have a second conductive contact 118J formed thereon. The semiconductor device 80A may have a first underfill 421, which is encapsulated by the first insulating encapsulation body 431 and laterally covers the first and second conductive contacts (117J and 118J) and the first and second conductive bumps (201 and 202). The pillar portion 160P' may include a seed layer 1601' formed on the surface 202b' of the second conductive bump 202 and a metallization layer 1602 formed on the seed layer 1601'. In some embodiments, the second conductive bump 202 includes a seed layer 2021 at the surface 202 b ′, and the seed layer 1601 ′ of the pillar portion 160P′ is in direct contact with the seed layer 2021 of the second conductive bump 202 .

[0107] Fig.38 Schematic cross-sectional views of semiconductor devices according to some embodiments are shown. Similar reference numerals in this embodiment represent similar components to those in the previous embodiments. Fig.38 And refer to Fig.37 and Fig.32 , the semiconductor device 80B is similar to the semiconductor device 80A, except that the semiconductor device 80B also includes a second insulating encapsulant 432 formed on the first insulating encapsulant 431 to cover the TIV 260, the second IC die 350, and the second underfill 423'. The semiconductor device 80B may include a dielectric layer 272 formed on the TIV 260 and the second insulating encapsulant 432, a conductive pattern 274 formed through the dielectric layer 272 to be in physical and electrical contact with the TIV 260, and an electrical connector 276 formed on the conductive pattern 274 to be electrically coupled to the TIV 260. The second insulating encapsulant 432, the dielectric layer 272, the conductive pattern 274, and the electrical connector 276 may be similar to the semiconductor device 80A. Fig.32 The second insulating encapsulation body 332, the dielectric layer 272, the conductive pattern 274 and the electrical connection 276 described in FIG.

[0108] According to some embodiments, a device includes a first IC die arranged side by side, a second IC die overlapping the first IC die and electrically coupled to the first IC die, and a first conductive feature. Each of the first IC dies includes a first die connector and a second die connector, wherein a first pitch of the first die connector is less than a second pitch of the second die connector. The second IC die includes a third die connector, wherein a third pitch of the third die connector is substantially equal to the first pitch of the first die connector. The first conductive feature is interposed between the first die connector and the third die connector and electrically coupled to the first die connector and the third die connector. Each of the first conductive features includes at least one first conductive bump and at least one first conductive contact.

[0109] In some embodiments, the first conductive contact includes a first portion having a curved sidewall and physically connected to a corresponding one of the third die connectors, and a second portion connected to the first portion and the first conductive bump, the second portion having a substantially vertical sidewall connected to the curved sidewall of the first portion. In some embodiments, each of the first conductive features also includes a second conductive contact that is physically coupled to the first conductive bump and the corresponding one of the first die connectors, and the second conductive contact includes a curved sidewall. In some embodiments, the lateral size of the first conductive bump is greater than the lateral size of the corresponding one of the first die connectors and is also greater than the lateral size of the corresponding one of the third die connectors. In some embodiments, the first conductive bump is laterally offset from the corresponding one of the first die connectors. In some embodiments, the interface between the first conductive bump and the first die connector is free of solder material. In some embodiments, the semiconductor device further comprises a plurality of second conductive features surrounding the first conductive features and a plurality of conductive pillars surrounding the second integrated circuit die, each of the second conductive features comprising a second conductive bump, the second conductive bump comprising a first side facing a corresponding one of the second die connectors and a second side opposite to the first side, each of the conductive pillars being in direct contact with the second side of one of the second conductive bumps. In some embodiments, the lateral size of the conductive pillar is smaller than the lateral size of the corresponding one of the second conductive bumps. In some embodiments, each of the conductive pillars comprises a first portion physically connected to the second side of the one of the second conductive bumps and comprising a lateral size and a second portion connected to the first portion and comprising a lateral size, the lateral size being substantially equal to the lateral size of the second side of the one of the second conductive bumps, the lateral size being greater than the lateral size of the first portion. In some embodiments, each of the second conductive features further comprises a second conductive contact connecting the first side of the second conductive bump and the corresponding one of the second die connectors, the second conductive contact comprising a curved sidewall. In some embodiments, the semiconductor device also includes a first bottom filler surrounding the first tube core connector and the second tube core connector and the first conductive feature, wherein the first conductive contact of each of the first conductive features includes a first portion protruding from the first bottom filler and a second portion connected to the first portion and inserted into the first bottom filler.In some embodiments, the semiconductor device also includes a second bottom filler and a plurality of conductive pillars, the second bottom filler being disposed on the first bottom filler and surrounding the first portion of the first conductive contact of each of the first conductive features and the third die connector of the second integrated circuit die, the conductive pillars surrounding the second integrated circuit die and coupled to the second die connector of the first integrated circuit die, wherein a portion of the second bottom filler extends between two adjacent conductive pillars near the second integrated circuit die.

[0110] According to some alternative embodiments, a device includes a first IC die disposed side by side, a second IC die stacked on the first IC die and electrically coupled to the first IC die, a conductive post disposed above the first IC die, a first electrical connection electrically connected to the second IC die and one of the first IC die, and a second electrical connection electrically connected to one of the conductive posts and one of the first IC die. The first electrical connection includes a first solder joint physically connected to a die connector of the second IC die. An interface between the second electrical connection and the conductive post is free of solder material, wherein a size of a first conductive bump of the first electrical connection is smaller than a size of a second conductive bump of the second electrical connection.

[0111] In some embodiments, the first electrical connection further comprises a second solder joint physically connected to a die connector of the one of the first integrated circuit dies. In some embodiments, an interface between the first electrical connection and the die connector of the one of the first integrated circuit dies is free of solder material. In some embodiments, the first solder joint comprises a curved sidewall connected to the die connector of the second integrated circuit die and a substantially vertical sidewall connected to the curved sidewall.

[0112] According to some alternative embodiments, a method includes: coupling a first IC die to a first side of a first conductive feature and a first side of a second conductive feature, wherein a pitch of the first conductive feature is less than a pitch of the second conductive feature; coupling a second IC die to a second side of the first conductive feature opposite to the first side of the first conductive feature, wherein a solder joint is formed on the second side of the first conductive feature; and forming a conductive column on a second side of the second conductive feature opposite to the first side of the second conductive feature.

[0113] In some embodiments, the method further comprises: before coupling the second integrated circuit die to the second side of the first conductive feature, forming an underfill to surround the first integrated circuit die, the first conductive feature, and the second conductive feature; recessing the first conductive feature from the underfill; and forming the solder joints on the second side of the first conductive feature, wherein each of the solder joints comprises a first portion inserted into the underfill and a second portion connected to the first portion and protruding from the underfill. In some embodiments, when recessing the first conductive feature from the underfill, recessing the second conductive feature from the underfill; and forming the conductive pillars on the second side of the second conductive feature, wherein each of the conductive pillars comprises a first portion inserted into the underfill and a second portion connected to the first portion and protruding from the underfill. In some embodiments, coupling the first integrated circuit die to the first side of the first conductive feature and the first side of the second conductive feature includes: forming the first conductive feature and the second conductive feature on a plurality of first and second die connectors of the first integrated circuit die, respectively, wherein a lateral size of each of the first conductive features is larger than a lateral size of a corresponding one of the first die connectors, and a lateral size of each of the second conductive features is larger than a lateral size of a corresponding one of the second die connectors.

[0114] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the embodiments of the utility model, rather than to limit them. Although the embodiments of the utility model are described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents. However, these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the embodiments of the utility model.

Claims

1. A semiconductor device, characterized in that: include: a plurality of first integrated circuit dies arranged side by side, each of the first integrated circuit dies comprising a plurality of first die connectors and a plurality of second die connectors, wherein a first pitch of the first die connectors is smaller than a second pitch of the second die connectors; a second integrated circuit die overlapping the first integrated circuit die and electrically connected to the first integrated circuit die, the second integrated circuit die comprising a plurality of third die connectors, wherein a third pitch of the third die connectors is equal to the first pitch of the first die connectors; as well as A plurality of first conductive features are interposed between and electrically coupled to the first die connector and the third die connector, each of the first conductive features comprising at least one first conductive bump and at least one first conductive contact.

2. The semiconductor device according to claim 1, wherein: The first conductive contact comprises: a first portion having a curved sidewall and physically connected to a corresponding one of the third die connectors; and A second portion is connected to the first portion and the first conductive bump, the second portion having a vertical sidewall connected to the curved sidewall of the first portion.

3. The semiconductor device according to claim 1, wherein: wherein each of the first conductive features further comprises: A second conductive contact is physically coupled to a corresponding one of the first conductive bump and the first die connector, and the second conductive contact includes a curved sidewall.

4. The semiconductor device according to claim 1, wherein: The lateral size of the first conductive bump is greater than the lateral size of a corresponding one of the first die connectors and is also greater than the lateral size of a corresponding one of the third die connectors.

5. The semiconductor device according to claim 1, wherein: Wherein the first conductive bump is laterally offset from a corresponding one of the first die connectors.

6. The semiconductor device according to claim 1, wherein: Also includes: a plurality of second conductive features surrounding the first conductive feature, each of the second conductive features comprising: a second conductive bump including a first side facing a corresponding one of the second die connectors and a second side opposite to the first side; A plurality of conductive pillars surround the second integrated circuit die, each of the conductive pillars being in direct contact with the second side of one of the second conductive bumps.

7. The semiconductor device according to claim 1, wherein: Also includes: A first underfill surrounds the first and second die connectors and the first conductive features, wherein the first conductive contact of each of the first conductive features includes a first portion protruding from the first underfill and a second portion connected to the first portion and inserted into the first underfill.

8. A semiconductor device, characterized in that: include: A plurality of first integrated circuit dies are arranged side by side; a second integrated circuit die stacked on top of and electrically coupled to the first integrated circuit die; a plurality of conductive pillars disposed on the first integrated circuit die; a first electrical connection electrically connected to one of the second integrated circuit die and the first integrated circuit die, the first electrical connection comprising a first solder joint physically connected to a die connector of the second integrated circuit die; as well as A second electrical connection is electrically connected to one of the conductive pillars and one of the first integrated circuit tube cores, and the interface between the second electrical connection and the one of the conductive pillars does not have solder material, wherein the size of the first conductive bump of the first electrical connection is smaller than the size of the second conductive bump of the second electrical connection.

9. The semiconductor device according to claim 8, wherein: The first electrical connection further comprises: A second solder joint is physically connected to the die attach feature of the one of the first integrated circuit dies.

10. The semiconductor device according to claim 8, wherein: The first solder joint includes a curved sidewall connected to the die connector of the second integrated circuit die and a vertical sidewall connected to the curved sidewall.

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