Circuit board structure capable of improving filtering effect of filtering capacitor

Abstract

The utility model discloses a circuit board structure capable of improving the filtering effect of a filtering capacitor, which comprises a chip and a filtering capacitor which are arranged on a circuit board, a power supply pin of the chip is provided with a first power supply via hole, and the power supply pin of the chip is connected with the first power supply via hole. The chip is connected with a power supply layer of the circuit board through the first power supply via hole; a second power supply via hole is formed in a power supply pin of the filter capacitor, and the power supply pin of the filter capacitor is connected with the second power supply via hole, so that the filter capacitor is connected with a power supply layer of the circuit board through the second power supply via hole. According to the utility model, the connection mode of the filter capacitor of the chip is optimized by respectively arranging the via holes at the power supply pins of the chip and the filter capacitor and communicating the via holes with the power supply layer of the circuit board, the current loop is reduced, and the filter efficiency is improved, thereby improving the performance and stability of the whole circuit.

Description

Technical Field

[0001] The utility model relates to the technical field of PCB design, and more specifically, to a circuit board structure capable of improving the filtering effect of a filter capacitor. Background Art

[0002] Printed Circuit Board (PCB), also known as printed circuit board, is an important part of the physical support and signal transmission of electronic products. With the continuous development of electronic technology, product iteration, automation, and intelligent products are becoming more and more popular. People have higher and higher requirements for the functions of electronic products and pay more attention to the quality of products. In the process of product design, we can make the performance of the product more guaranteed by processing some details.

[0003] It plays a vital role in the rapid development, automation and intelligentization of modern electronic products. As consumers' requirements for the functional diversity and quality of electronic products increase, the design details of PCB boards become particularly important.

[0004] In the design process of PCB boards, in order to ensure the stable operation of the chip (IC) and reduce power supply noise and interference, one or more filter capacitors are usually configured near the power pin (Pin) of each IC. The main function of the capacitor is filtering, that is, removing the high-frequency noise components in the power supply signal to ensure that the IC obtains a clean and stable power supply.

[0005] The traditional layout of filter capacitors often has a problem: the power pin of the IC is first connected to the filter capacitor through a long trace, and then connected to the power plane through a via (such as Figure 1 This layout will make the current loop longer, increase the risk of electromagnetic interference during the current transmission process, and also increase the power supply impedance, thereby weakening the filtering effect of the filter capacitor. Utility Model Content

[0006] In order to overcome the problem that the existing filter capacitor layout causes the current loop to become longer, increases the risk of electromagnetic interference during current transmission, and also increases the power supply impedance, thereby weakening the filtering effect of the filter capacitor, the utility model provides a circuit board structure that can improve the filtering effect of the filter capacitor.

[0007] The technical solution of the utility model is as follows:

[0008] A circuit board structure capable of improving the filtering effect of a filter capacitor comprises a chip and a filter capacitor arranged on the circuit board.

[0009] A first power via is provided at the power pin of the chip, and the power pin of the chip is connected to the first power via, so that the chip is connected to the power layer of the circuit board through the first power via;

[0010] A second power via is provided at the power pin of the filter capacitor, and the power pin of the filter capacitor is connected to the second power via, so that the filter capacitor is connected to the power layer of the circuit board through the second power via.

[0011] According to the utility model of the above solution, a first ground via is provided at the ground pin of the chip, and the ground pin of the chip is connected to the first ground via, so that the chip is connected to the ground plane layer of the circuit board through the first ground via;

[0012] A second ground via is provided at the ground pin of the filter capacitor, and the ground pin of the filter capacitor is connected to the second ground via, so that the filter capacitor is connected to the ground plane layer of the circuit board through the second ground via.

[0013] According to the above solution of the utility model, the distance between the chip and the filter capacitor is less than 5 mm.

[0014] According to the above scheme of the utility model, the first power via and the second power via are through holes, the first power via is arranged around the power pin of the chip, and the power pin of the chip is connected to the first power via through a first routing line, and the second power via is arranged around the power pin of the filter capacitor, and the power pin of the filter capacitor is connected to the second power via through a second routing line.

[0015] According to the above-mentioned scheme of the utility model, the first ground via and the second ground via are through holes, the first ground via is arranged around the ground pin of the chip, and the ground pin of the chip is connected to the first ground via through a third routing line, and the second ground via is arranged around the ground pin of the filter capacitor, and the ground pin of the filter capacitor is connected to the second ground via through a fourth routing line.

[0016] According to the above solution of the utility model, the apertures of the first power via, the second power via, the first ground via, and the second ground via are not less than 0.2 mm.

[0017] According to the above-mentioned scheme of the utility model, the first power via and the second power via are blind buried vias, the first power via is arranged on the power pin of the chip, and the first power via is connected to the power layer of the circuit board, and the second power via is arranged on the power pin of the filter capacitor, and the second power via is connected to the power layer of the circuit board.

[0018] According to the above-mentioned scheme of the utility model, the first ground via and the second ground via are blind buried vias, the first ground via is arranged on the ground pin of the chip, and the first ground via is connected to the ground plane layer of the circuit board, and the second ground via is arranged on the ground pin of the filter capacitor, and the second ground via is connected to the ground plane layer of the circuit board.

[0019] According to the above solution of the utility model, the apertures of the first power via, the second power via, the first ground via, and the second ground via are not less than 0.1 mm.

[0020] The utility model according to the above scheme has the beneficial effect that the utility model optimizes the connection method of the chip's filter capacitor by respectively setting vias near the power pins of the chip and the filter capacitor, and connecting the vias to the power layer of the circuit board, thereby reducing the current loop and improving the filtering efficiency, thereby improving the performance and stability of the overall circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 It is a structural schematic diagram of the prior art;

[0022] Figure 2 It is a structural schematic diagram of an embodiment of the utility model;

[0023] Figure 3 It is a structural schematic diagram of another embodiment of the utility model.

[0024] In the drawings, the reference numerals are as follows:

[0025] 100, chip; 101, power pin of chip; 102, ground pin of chip; 103, first power via; 104, first ground via; 200, filter capacitor; 201, power pin of filter capacitor; 202, ground pin of filter capacitor; 203, second power via; 204, second ground via. DETAILED DESCRIPTION

[0026] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments.

[0027] It should be noted that the terms "including" and "having" and any variations thereof in the specification and claims of the present utility model are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but optionally includes steps or units that are not listed, or optionally includes other steps or units inherent to these processes, methods, products or devices. Terms such as "setting" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral body; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. The directions or positions indicated by the terms "upper", "lower", "left", "right", "front", "back", "bottom", etc. are based on the directions or positions shown in the drawings, which are only for the convenience of description and cannot be understood as limitations on the present technical solution.

[0028] It should be noted that the traditional layout of filter capacitors often has a problem: the power pin of the IC is first connected to the filter capacitor through a long trace, and then connected to the power plane through a via. This layout will cause the current loop to become longer, increase the risk of electromagnetic interference during the current transmission process, and also increase the power supply impedance, thereby weakening the filtering effect of the filter capacitor.

[0029] like Figure 2-Figure 3 As shown, this embodiment provides a circuit board structure that can enhance the filtering effect of the filter capacitor 200, optimize the connection method of the filter capacitor 200 of the chip 100, reduce the current loop, and improve the filtering efficiency, thereby improving the performance and stability of the overall circuit.

[0030] Specifically, by setting vias near the chip 100 and the power pin 201 of the filter capacitor, the current loop can be shortened, the chip 100 can be better filtered, and the noise of the power layer itself can be better eliminated, the impedance can be reduced, and the performance of the product can be more guaranteed.

[0031] Specifically, it includes a chip 100 and a filter capacitor 200 arranged on a circuit board, a first power via 103 is arranged near the power pin 101 of the chip, and the power pin 101 of the chip is connected to the first power via 103, so that the chip 100 is connected to the power layer of the circuit board through the first power via 103; the arrangement of the first power via 103 ensures that the chip 100 can be directly and efficiently connected to the power layer of the circuit board through the via, and the close connection method reduces the path length of the current during the transmission process, reduces the impedance, and thus improves the efficiency and stability of the power supply. Placing the first power via 103 near the power pin 101 of the chip can effectively reduce the inductance effect caused by the change of the current path and reduce the power supply noise.

[0032] A second power via 203 is provided near the power pin 201 of the filter capacitor, and the power pin 201 of the filter capacitor is connected to the second power via 203, so that the filter capacitor 200 is connected to the power layer of the circuit board through the second power via 203. The provision of the second power via 203 ensures that the filter capacitor 200 can be directly and efficiently connected to the power layer of the circuit board through the via. The close connection method reduces the path length of the current during transmission, reduces impedance, and thus improves the efficiency and stability of the power supply. Placing the second power via 203 near the power pin 201 of the filter capacitor can effectively reduce the inductance effect caused by the change of the current path and reduce the power supply noise.

[0033] In one embodiment, a first ground via 104 is provided near the ground pin 102 of the chip, and the ground pin 102 of the chip is connected to the first ground via 104, so that the chip 100 is connected to the ground plane layer of the circuit board through the first ground via 104; the first ground via 104 is placed near the ground pin 102 of the chip to ensure that the ground current can directly and efficiently flow to the ground plane layer of the circuit board through the via. The path length of the ground current during transmission is reduced, the ground impedance is reduced, and the stability and anti-interference ability of the ground plane are improved.

[0034] A second ground via 204 is provided near the ground pin 202 of the filter capacitor, and the ground pin 202 of the filter capacitor is connected to the second ground via 204, so that the filter capacitor 200 is connected to the ground plane layer of the circuit board through the second ground via 204. The second ground via 204 is provided near the ground pin 202 of the filter capacitor, so that the filter capacitor 200 can be directly and quickly connected to the ground plane layer. It is ensured that the filter capacitor 200 can effectively guide the noise current to the ground plane layer, further improving the filtering effect.

[0035] In one embodiment, the distance between the chip 100 and the filter capacitor 200 is less than 5 mm. If the distance between the chip 100 and the filter capacitor 200 exceeds 5 mm, the filter capacitor 200 has a weak filtering effect and cannot achieve the filtering function.

[0036] In one embodiment, the first power via 103 and the second power via 203 are through holes, the first power via 103 is arranged around the power pin 101 of the chip, and the power pin 101 of the chip is connected to the first power via 103 through a first routing line, and the second power via 203 is arranged around the power pin 201 of the filter capacitor, and the power pin 201 of the filter capacitor is connected to the second power via 203 through a second routing line.

[0037] The first ground via 104 and the second ground via 204 are through holes. The first ground via 104 is arranged around the ground pin 102 of the chip, and the ground pin 102 of the chip is connected to the first ground via 104 through a third trace. The second ground via 204 is arranged around the ground pin of the filter capacitor 200, and the ground pin 202 of the filter capacitor is connected to the second ground via 204 through a fourth trace.

[0038] The spacing between the first power via 103 and the power pin 101 of the chip, the spacing between the first ground via 104 and the ground pin 102 of the chip, the spacing between the second power via 203 and the power pin 201 of the filter capacitor, and the spacing between the second ground via 204 and the ground pin 202 of the filter capacitor all meet the processing requirements, that is, the hole plate of the first power via 103 does not interfere with the power pin 101 of the chip, the second power via 203 does not interfere with the power pin 201 of the filter capacitor, the first ground via 104 does not interfere with the ground pin 102 of the chip, and the second ground via 204 does not interfere with the ground pin 202 of the filter capacitor. On the premise of no interference, the closer the holes are, the better.

[0039] Preferably, the apertures of the first power via 103 , the second power via 203 , the first ground via 104 , and the second ground via 204 are not less than 0.2 mm.

[0040] In one embodiment, the first power via 103 and the second power via 203 are blind buried vias, the first power via 103 is arranged on the power pin 101 of the chip, and the first power via 103 is connected to the power layer of the circuit board, and the second power via 203 is arranged on the power pin 201 of the filter capacitor, and the second power via 203 is connected to the power layer of the circuit board.

[0041] The first ground via 104 and the second ground via 204 are blind buried vias. The first ground via 104 is arranged on the ground pin 102 of the chip, and the first ground via 104 is connected to the ground plane layer of the circuit board. The second ground via 204 is arranged on the ground pin of the filter capacitor 200, and the second ground via 204 is connected to the ground plane layer of the circuit board.

[0042] The apertures of the first power via 103 , the second power via 203 , the first ground via 104 , and the second ground via 204 are not less than 0.1 mm.

[0043] It should be understood that those skilled in the art can make improvements or changes based on the above description, and all these improvements and changes should fall within the scope of protection of the claims attached to the utility model.

[0044] The above is an exemplary description of the utility model patent in conjunction with the accompanying drawings. It is obvious that the implementation of the utility model patent is not limited to the above-mentioned method. As long as various improvements are made by adopting the method concept and technical solution of the utility model patent, or the concept and technical solution of the utility model patent are directly applied to other occasions without improvement, they are all within the protection scope of the utility model.

Claims

1. A circuit board structure capable of improving the filtering effect of a filter capacitor, characterized in that: Including chips and filter capacitors on the circuit board, A first power via is provided at the power pin of the chip, and the power pin of the chip is connected to the first power via, so that the chip is connected to the power layer of the circuit board through the first power via; A second power via is provided at the power pin of the filter capacitor, and the power pin of the filter capacitor is connected to the second power via, so that the filter capacitor is connected to the power layer of the circuit board through the second power via.

2. A circuit board structure capable of improving filtering effect of filter capacitor according to claim 1, characterized in that: A first ground via is provided at the ground pin of the chip, and the ground pin of the chip is connected to the first ground via, so that the chip is connected to the ground plane layer of the circuit board through the first ground via; A second ground via is provided at the ground pin of the filter capacitor, and the ground pin of the filter capacitor is connected to the second ground via, so that the filter capacitor is connected to the ground plane layer of the circuit board through the second ground via.

3. A circuit board structure capable of improving filtering effect of filter capacitor according to claim 2, characterized in that: The distance between the chip and the filter capacitor is less than 5 mm.

4. A circuit board structure capable of improving filtering effect of filter capacitors according to claim 2 or 3, characterized in that: The first power via and the second power via are through holes. The first power via is arranged around the power pin of the chip, and the power pin of the chip is connected to the first power via through a first trace. The second power via is arranged around the power pin of the filter capacitor, and the power pin of the filter capacitor is connected to the second power via through a second trace.

5. A circuit board structure capable of improving filtering effect of filter capacitor according to claim 4, characterized in that: The first ground via and the second ground via are through holes, the first ground via is arranged around the ground pin of the chip, and the ground pin of the chip is connected to the first ground via through a third routing line, the second ground via is arranged around the ground pin of the filter capacitor, and the ground pin of the filter capacitor is connected to the second ground via through a fourth routing line.

6. A circuit board structure capable of improving filtering effect of filter capacitors according to claim 5, characterized in that: The apertures of the first power via, the second power via, the first ground via, and the second ground via are not less than 0.2 mm.

7. A circuit board structure capable of improving filtering effect of filter capacitors according to claim 2 or 3, characterized in that: The first power via and the second power via are blind buried vias. The first power via is arranged on the power pin of the chip, and the first power via is connected to the power layer of the circuit board. The second power via is arranged on the power pin of the filter capacitor, and the second power via is connected to the power layer of the circuit board.

8. A circuit board structure capable of improving filtering effect of filter capacitors according to claim 7, characterized in that: The first ground via and the second ground via are blind buried vias, the first ground via is arranged on the ground pin of the chip, and the first ground via is connected to the ground plane layer of the circuit board, the second ground via is arranged on the ground pin of the filter capacitor, and the second ground via is connected to the ground plane layer of the circuit board.

9. A circuit board structure capable of improving filtering effect of filter capacitors according to claim 8, characterized in that: The apertures of the first power via, the second power via, the first ground via, and the second ground via are not less than 0.1 mm.

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