Circuit board and electronic equipment

Abstract

The embodiment of the utility model provides a circuit board and electronic equipment, the circuit board comprises a board body, a chip array arranged on the board body and a data interface arranged on the board body and used for transmitting data, the chip array comprises a first chip set and a second chip set which are sequentially distributed at intervals in the heat dissipation direction, and the first chip set and the second chip set are arranged on the board body. The first chipset and the second chipset both comprise at least one row of chips and / or at least one column of chips, and the data interface is sequentially connected in series with the first chipset and the second chipset through a signal line. According to the circuit board provided by the embodiment of the invention, the data interface is firstly connected in series with the first chipset which is better in heat dissipation effect, lower in temperature and higher in partial voltage for data transmission, so that the power demand of data transmission between the data interface and each chip can be met by cross-stage power taking, and the problem of data transmission failure caused by unsuccessful cross-stage power taking is avoided.

Description

Technical Field

[0001] The present application relates to the field of heat dissipation technology, and in particular to a circuit board and an electronic device. Background Art

[0002] In order to improve computing power, circuit boards with more chips have appeared in the prior art. Usually, multiple chips distributed side by side on the circuit board are connected in parallel to form a first-level chip, and the multi-level chips are connected in series. In addition to the internal circuit of the chip itself, in order to communicate with external devices at different voltage levels, the data transmission between the data IO port and the chip requires independent power supply.

[0003] The chip itself requires a relatively low voltage, while the data transmission between the data IO port and the chip requires a higher voltage. Each level of chipset is equipped with an auxiliary power supply module, which draws power from the chipset of the corresponding level. However, since the voltage of the chipset at this level cannot meet the power supply requirements for data transmission, the auxiliary power supply module needs to draw power across levels in the direction of data transmission. For the last few levels of chipsets that cannot continue to draw power across levels, the circuit board will equip the corresponding auxiliary power supply module with a boost module to meet the power demand for data transmission.

[0004] The circuit board of the prior art has the problem that data cannot be transmitted because the cross-level power supply cannot meet the power demand of data transmission between the data IO port and the chip. Utility Model Content

[0005] The embodiments of the present application provide a circuit board and an electronic device to solve or alleviate one or more technical problems in the prior art.

[0006] As one aspect of an embodiment of the present application, an embodiment of the present application provides a circuit board, comprising: a board body; a chip array, arranged on the board body, comprising a first chipset and a second chipset sequentially spaced apart along a heat dissipation direction, the first chipset and the second chipset each comprising at least one row of chips and / or at least one column of chips; the heat dissipation direction is used to characterize the flow direction of a cooling medium flowing through the board body; a data interface, arranged on the board body, for transmitting data, the data interface sequentially connecting the first chipset and the second chipset in series through a signal line.

[0007] In one embodiment, the circuit board also includes a first electrical connector and a second electrical connector arranged on the board body, the first electrical connector is used to connect to the negative pole of the power supply, and the second electrical connector is used to connect to the positive pole of the power supply; the first electrical connector, the first chipset, the second chipset and the second electrical connector are connected in series in sequence.

[0008] In one embodiment, the first electrical connector, the data interface, and the second electrical connector are sequentially spaced apart in the heat dissipation direction, and the data interface is disposed adjacent to the first electrical connector.

[0009] In one embodiment, the first electrical connector, the data interface, and the second electrical connector are all disposed adjacent to the edge of the board body in the vertical direction, and the vertical direction is perpendicular to the heat dissipation direction.

[0010] In one embodiment, both the first chip group and the second chip group include a plurality of chip distribution areas, and the plurality of chip distribution areas are spaced apart in the vertical direction;

[0011] The interval distance between at least some adjacent two chip distribution areas among the plurality of chip distribution areas in the first chip group is greater than the distance between two adjacent chips in the vertical direction in any chip distribution area in the first chip group; and / or

[0012] The interval distance between at least some adjacent two chip distribution areas among the plurality of chip distribution areas in the second chip group is greater than the distance between two adjacent chips in the vertical direction in any chip distribution area in the second chip group.

[0013] In one embodiment, the plurality of interval distances between multiple pairs of adjacent chip distribution areas in the first chip group are all greater than the distance between two adjacent chips in the vertical direction in any chip distribution area in the first chip group;

[0014] The plurality of interval distances between multiple pairs of adjacent chip distribution areas in the second chip group are all greater than the distance between two adjacent chips in the vertical direction in any chip distribution area in the second chip group;

[0015] Moreover, the multiple first gaps formed between multiple pairs of adjacent chip distribution areas in the first chip group correspond one-to-one with the multiple second gaps formed between multiple pairs of adjacent chip distribution areas in the second chip group, and along the heat dissipation direction, the first gaps and the second gaps are staggeredly distributed.

[0016] In one embodiment, the interval distance between any two adjacent chip distribution areas in the first chip group is less than the group interval distance between the first chip group and the second chip group in the heat dissipation direction; and / or

[0017] The interval distance between any two adjacent chip distribution areas in the second chip group is less than the group interval distance between the first chip group and the second chip group in the heat dissipation direction.

[0018] In one embodiment, the heat dissipation direction is parallel to the row direction of the chip arrangement, and the number of chip rows in at least one chip distribution area in the first chip group is different from the number of chip rows in at least one chip distribution area in the second chip group.

[0019] In one embodiment, the number of rows in at least two chip distribution areas in the first chip group is different, and / or the number of rows in at least two chip distribution areas in the second chip group is different.

[0020] In one embodiment, the group spacing between the first chip group and the second chip group in the heat dissipation direction is greater than the spacing between any two adjacent chips in the first chip group in the heat dissipation direction.

[0021] In one embodiment, the first chip group includes multiple rows of chips arranged at intervals in the heat dissipation direction. Along the heat dissipation direction, the spacing between two adjacent rows of chips in the multiple rows of chips in the first chip group gradually decreases, or first gradually increases and then gradually decreases.

[0022] In one embodiment, the second chip group includes multiple rows of chips spaced apart in the heat dissipation direction. Along the heat dissipation direction, the spacing between two adjacent rows of chips in the multiple rows of chips in the second chip group gradually increases.

[0023] In one embodiment, along the heat dissipation direction, the spacing between the last two adjacent rows of chips in the second chip group is greater than the spacing between any other two adjacent rows of chips.

[0024] In one embodiment, along the heat dissipation direction, the spacing between two adjacent rows of chips located upstream in the second chip group is less than the spacing between two adjacent rows of chips located upstream in the first chip group, and greater than the spacing between two adjacent rows of chips located downstream in the first chip group.

[0025] In one embodiment, the chips distributed along the heat dissipation direction in the first chip group are connected in parallel for power supply, forming multiple groups of first parallel chips distributed in the vertical direction;

[0026] The chips distributed along the heat dissipation direction in the second chip group are connected in parallel for power supply, forming multiple groups of second parallel chips distributed in the vertical direction. The multiple groups of first parallel chips and the multiple groups of second parallel chips are connected in series for power supply in sequence.

[0027] In one embodiment, the data interface is connected in series with the group of first parallel chips closest to the data interface through a signal line, sequentially connects the other first parallel chips in series along the vertical direction, then is connected in series with the group of second parallel chips farthest from the data interface, and then sequentially connects the other second parallel chips in series along the vertical direction.

[0028] As another aspect of the embodiments of the present application, the embodiments of the present application provide an electronic device, including a power supply device and a circuit board as described in any one of the above.

[0029] In one embodiment, the electronic device further includes a fan device for conveying cold air flow flowing through the circuit board along the heat dissipation direction.

[0030] In one embodiment, the electronic device further includes a heat dissipation air duct. The circuit board is installed in the heat dissipation air duct. The heat dissipation air duct has an air inlet and an air outlet. The first chip group of the circuit board is adjacent to the air inlet; the heat dissipation direction is the flowing direction of the cold air flow passing through the air inlet, the circuit board, and the air outlet in sequence.

[0031] According to the circuit board of the embodiment of the present application, by serially connecting a data interface with a first chipset that has better heat dissipation effect, lower temperature, and higher voltage division for data transmission, it is ensured that power extraction across levels can meet the power consumption requirements for data transmission between the data interface and each chip, avoiding the problem of data transmission failure caused by unsuccessful power extraction across levels.

[0032] The above summary is only for the purpose of the specification and is not intended to be limiting in any way. In addition to the illustrative aspects, embodiments, and features described above, further aspects, embodiments, and features of the present application will become apparent by reference to the drawings and the following detailed description. Description of the Drawings

[0033] In the drawings, unless otherwise specified, the same reference numerals throughout the several views denote the same or similar components or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings only depict some embodiments disclosed in the present application and should not be regarded as limiting the scope of the present application.

[0034] Figure 1A Showing a schematic structural diagram of a circuit board according to Embodiment 1 of the present application;

[0035] Figure 1B Showing Figure 1A A signal diagram of the circuit board shown;

[0036] Figure 1C Showing Figure 1A An electric current diagram of the circuit board shown;

[0037] Figure 2 Showing a schematic structural diagram of a circuit board according to Embodiment 2 of the present application;

[0038] Figure 3 Showing a schematic structural diagram of a circuit board according to Embodiment 3 of the present application;

[0039] Figure 4 Showing a schematic structural diagram of a circuit board according to Embodiment 4 of the present application;

[0040] Figure 5 Showing a schematic structural diagram of an electronic device according to an embodiment of the present application;

[0041] Figure 6 Showing a schematic assembly structure diagram of a radiator and a circuit board of an electronic device according to an embodiment of the present application.

[0042] Description of the Reference Numerals:

[0043] 100 - Circuit board, 101 - Chip, 102 - Data interface, 103 - First electrical connector, 104 - Second electrical connector, 105 - Chip distribution area, 110 - Board body, 120 - First chip group, 121 - First parallel chip, 122 - First gap, 130 - Second chip group, 131 - Second parallel chip, 132 - Second gap, 140 - Power line, 150 - Signal line;

[0044] 200 - Electronic device, 201 - Air inlet, 202 - Air outlet, 210 - Cooling device, 220 - Radiator, 230 - Cooling air duct. Detailed implementation manners

[0045] In the following text, only some exemplary embodiments are simply described. As those skilled in the art can recognize, the described embodiments can be modified in various different ways without departing from the spirit or scope of the present application. Therefore, the drawings and the description are considered to be exemplary in nature rather than restrictive.

[0046] Figure 1A The structural schematic diagram of the circuit board 100 according to the first embodiment of the present application is shown. Figure 1B Shown Figure 1A The signal diagram of the circuit board 100 shown. As Figure 1A , Figure 1B shown, in the implementation manner of the present application, the circuit board 100 includes a board body 110, a chip array disposed on the board body 110, and a data interface 102 disposed on the board body 110 and used for transmitting data. Among them, the chip array includes a first chip group 120 and a second chip group 130 that are sequentially and spaced apart along the heat dissipation direction. Both the first chip group 120 and the second chip group 130 include at least one row of chips 101 and / or at least one column of chips 101. The data interface 102 sequentially connects the first chip group 120 and the second chip group 130 in series through the signal line 150. That is to say, the data interface 102 transmits data starting from the first chip group 120 close to the heat source through the signal line 150.

[0047] In the embodiment of the present application, the heat dissipation direction is used to characterize the flow direction of the cooling medium flowing through the board body 110 of the circuit board 100. In one example, the circuit board is cooled by air, and the cooling medium is a cold air flow with a certain flow rate. In another example, the circuit board is cooled by an immersion liquid cooling method, and the cooling medium is a liquid with a certain flow rate, and the heat dissipation direction is the flow direction of the liquid.

[0048] In the circuit board 100, whether the power extraction across levels can meet the voltage required for data transmission between the data IO port and the chip 101 depends on the voltage division of the chip 101. The voltage division is related to the internal resistance of the chip 101, and the internal resistance of the chip 101 is affected by temperature. Within a certain temperature range, the internal resistance of the chip 101 fluctuates above and below a fixed value with the change of temperature, showing a trend of decreasing with the increase of temperature and increasing with the decrease of temperature. Therefore, the temperature change of the chip 101 will affect the working state of data transmission between the data IO port and the chip 101.

[0049] In the related art, the data interface 102 enters to transmit data from the chip 101 far away from the heat source. Since the temperature of the chip 101 far away from the heat source is relatively high, the internal resistance of the chip 101 is low, the voltage division is low, and it is easy to have the problem that the power supply demand for data transmission between the data interface 102 and each chip 101 cannot be met by the power extraction across levels, resulting in the inability to transmit data.

[0050] To solve the above defects existing in the related art, in the circuit board of the embodiment of the present application, the data interface 102 is first connected in series with the first chip group 120 arranged upstream in the heat dissipation direction, and then connected in series with the second chip group 130 downstream. The heat dissipation air flow first flows through the first chip group 120, reducing the temperature of the first chip group 120, thereby increasing the internal resistance of the first chip group 120, and further enabling the first chip group 120 to obtain a higher voltage division, ensuring that the power extraction across levels can meet the power consumption requirements for data transmission between the data interface 102 and each chip 101, and avoiding the problem of data transmission failure caused by unsuccessful power extraction across levels. In addition, the total number of chips 101 in the chip array is relatively large, which can improve the computing power of the circuit board 100, thereby improving the overall performance of the circuit board 100, and the array arrangement method can improve the heat dissipation and temperature uniformity of the first chip group 120 and the second chip group 130.

[0051] As Figure 1A shown, the rectangular area of the circuit board 100 occupied by the chip array is divided into two areas. The multiple chips 101 distributed in the left area form the first chip group 120, and the multiple chips 101 distributed in the right area form the second chip group 130. The heat dissipation air flow enters from the left side of the circuit board 100, and the heat dissipation direction is from left to right. The temperature of the first chip group 120 is lower. The data interface 102 is first connected in series with the first chip group 120 with a higher voltage division through the signal line 150, and then connected in series with the second chip group 130 with a relatively lower voltage division, ensuring the power consumption requirements for data transmission between the data interface 102 and each chip in the first chip group 120 and the second chip group 130.

[0052] In one embodiment, the chip array includes a first chipset 120 and a second chipset 130. In another embodiment, the chip array may include a plurality of second chipsets 130, and the plurality of second chipsets 130 may be sequentially spaced and distributed along the heat dissipation direction. The specific number of the second chipsets 130 is not limited in the embodiments of the present application.

[0053] To facilitate wiring, the circuit board 100 of the embodiment of the present application changes the position of the data interface 102. The data interface 102 is arranged upstream of the board body 110 in the heat dissipation direction to facilitate connection with the first chipset 120, shorten the length of the signal line, and take into account the layout of other devices on the circuit board 100 (for example, the first electrical connector 103 and the second electrical connector 104 described below).

[0054] In one embodiment, the first electrical connector 103 is used to connect to the negative pole of the power supply, and the second electrical connector 104 is used to connect to the positive pole of the power supply. The first electrical connector 103, the first chipset 120, the second chipset 130 and the second electrical connector 104 are connected in series in sequence to realize power supply to the first chipset 120 and the second chipset 130.

[0055] In one embodiment, along the heat dissipation direction, the first electrical connector 103, the data interface 102, and the second electrical connector 104 are sequentially spaced and distributed in the heat dissipation direction, and the data interface 102 is disposed adjacent to the first electrical connector 103. In this embodiment, the data interface 102 is adjacent to the first electrical connector 103 connected to the negative pole of the power supply, which can improve the integrity of the signal, reduce noise interference, and ensure the stability of the power supply and the accuracy of the signal. In addition, the first electrical connector 103, the data interface 102, and the second electrical connector 104 are spaced and distributed side by side in one direction, which facilitates the overall wiring of the circuit board 100 and makes the wiring more regular.

[0056] In one embodiment, the first electrical connector 103, the data interface 102, and the second electrical connector 104 are all arranged near the edge of the board 110 in the vertical direction, wherein the vertical direction is perpendicular to the heat dissipation direction. In other words, the first electrical connector 103, the data interface 102, and the second electrical connector 104 are concentrated near the edge of the board 110 perpendicular to the heat dissipation direction, and do not occupy the middle position of the board 110, which, on the one hand, provides space for the chip array to facilitate the arrangement of more chips 101, and on the other hand, facilitates the wiring between them and the chip array.

[0057] like Figure 1A As shown, the heat dissipation direction is from left to right, and the vertical direction is Figure 1AThe up and down directions in it. The first electrical connector 103, the data interface 102, and the second electrical connector 104 are arranged adjacent to the upper edge of the board body 110 of the circuit board 100. Both the first electrical connector 103 and the second electrical connector 104 can be L-shaped. Here, it is only an example, and the present embodiment does not limit the shapes of the first electrical connector 103, the data interface 102, and the second electrical connector 104. The first electrical connector 103, the data interface 102, and the second electrical connector 104 are not limited to being arranged adjacent to the upper edge as shown in Figure 1A In another example, they can also be arranged adjacent to the lower edge.

[0058] Figure 1C shown Figure 1A The current diagram of the circuit board 100 shown in. As shown in Figure 1C , and in combination with Figure 1A shown, the chips 101 distributed along the heat dissipation direction in the first chip group 120 are connected in parallel for power supply through the power line 140, forming multiple groups of first parallel chips 121 distributed perpendicular to the heat dissipation direction. The chips 101 distributed along the heat dissipation direction in the second chip group 130 are connected in parallel for power supply, forming multiple groups of second parallel chips 131 distributed perpendicular to the heat dissipation direction. The multiple groups of first parallel chips 121 and the multiple groups of second parallel chips 131 are connected in series for power supply in sequence through the power line 140.

[0059] In Figure 1A , Figure 1C 's example, the heat dissipation direction is the direction from left to right, the parallel direction is the left and right direction in Figure 1A , and the direction perpendicular to the heat dissipation direction is the up and down direction in Figure 1A . Each of the chips 101 distributed along the left and right direction in the left first chip group 120 is connected in parallel for power supply, forming multiple groups of first parallel chips 121 distributed up and down. Each of the chips distributed along the left and right direction in the right first chip group 120 is connected in parallel for power supply, forming multiple groups of second parallel chips 131 distributed up and down. Each of the first parallel chips 121 and each of the second parallel chips 131 are connected in series for power supply in sequence.

[0060] In Figure 1A 's example, both the parallel direction and the row direction are the left and right direction, both the series direction and the column direction are the up and down direction. The number of chips 101 in the chip array is 120. The chip array is set as X*Y, the number of columns of chips 101 is X, and the number of rows of chips 101 is Y. In Figure 1AIn the example, X is 40, Y is 3, and the number of columns of the chips 101 in the first chip group 120 is the same as that in the second chip group 130. In the row direction, 3 chips 101 in the first chip group 120 are connected in parallel to form a first parallel chip 121, and 3 chips 101 in the second chip group 130 are connected in parallel to form a second parallel chip 131; in the column direction, 20 first parallel chips 121 and 20 second parallel chips 131 are connected in series in sequence. That is to say, a group of parallel chips in the first chip group 120 and the second chip group 130 can be regarded as a power-taking unit. The chips 101 in a power-taking unit are connected in parallel, and multiple power-taking units are connected in series.

[0061] In one embodiment, the data interface 102 is connected in series with the first group of first parallel chips 121 closest to the data interface 102 through the signal line 150, and the other first parallel chips 121 are connected in series in sequence in the vertical direction, then connected in series with the second group of second parallel chips 131 farthest from the data interface 102, and then the other second parallel chips 131 are connected in series in sequence in the vertical direction.

[0062] See Figure 1B Referring to the signal diagram of the circuit board 100 shown, the first chip group 120 on the left includes 20 groups of first parallel chips 121 distributed in the vertical direction, and the second chip group 130 on the right includes 20 groups of second parallel chips 131 distributed in the vertical direction. The uppermost first parallel chip 121 among the 20 groups of first parallel chips 121 is the first parallel chip 121 closest to the data interface 102, and the lowermost second parallel chip 131 among the 20 groups of second parallel chips 131 is the second parallel chip 131 closest to the data interface 102. The signal line 150 is connected in series from the uppermost first parallel chip 121 to the lowermost first parallel chip 121, and is connected in series from the lowermost first parallel chip 121 to the lowermost second parallel chip 131, and then is connected in series from the lowermost second parallel chip 131 to the uppermost first parallel chip 121.

[0063] It can be understood that a group of parallel chips is used as a first-level chip, that is: a group of first parallel chips 121 is used as a first-level chip, and a group of second parallel chips 131 is used as a first-level chip. In Figure 1AIn the example, the circuit board 100 includes 20-level chips, each of which corresponds to an auxiliary power supply module, and the data interface 102 is connected in series with 20-level chips through the signal line 150. According to the order of the signal line 150 in series and the preset number of cross-levels (for example, the number of cross-levels is 8), the auxiliary power supply module corresponding to the first-level chip takes the preset number of voltages from the first-level chip and the subsequent 7-level chips in sequence, and the sum of the voltages taken is used as the voltage supplied by the auxiliary power supply module of the first-level chip to the first-level chip to meet the voltage required for data transmission between the data interface 102 and the first-level chip; the auxiliary power supply module corresponding to the second-level chip takes the preset number of voltages from the second-level chip and the subsequent 7-level chips in sequence, and the sum of the voltages taken is used as the voltage supplied by the auxiliary power supply module of the second-level chip to the second-level chip to meet the voltage required for data transmission between the data interface 102 and the second-level chip. Cross-level power supply is analogous to this. For the 7-level chip that cannot be cross-level powered at the end, the circuit board is equipped with a corresponding boost module to ensure the power demand for data transmission between the data interface 102 and the chips at each level.

[0064] Based on the above principle of cross-level power supply, in the circuit board 100 of this embodiment, the data interface 102 is first connected in series with the first parallel chip 121 with better heat dissipation and lower temperature, and cross-level power supply is started from the first parallel chip 121 with higher voltage division, which can ensure that the cross-level power supply can meet the power demand for data transmission between the data interface 102 and each chip 101 of the first parallel chip 121. In addition, the signal line 150 is connected in series with each group of first parallel chips 121 and each group of second parallel chips 131 in the above manner, and the signal line 150 is shorter and the line layout is more regular.

[0065] Figure 2 FIG. 1 is a schematic diagram showing the structure of a circuit board 100 according to a second embodiment of the present application. Different from the example shown in FIG. 1 , Figure 2 In the example, the number of chips 101 in the chip array of the circuit board 100 is 160, the number of rows X of the chips 101 is 40, and the number Y of columns Y of the chips 101 is 4. In the row direction, the four chips 101 in the first chipset 120 and the four chips 101 in the second chipset 130 are connected in parallel to form a power taking unit, and in the column direction, the 20 power taking units of the first chipset 120 and the 20 power taking units of the second chipset 130 are connected in series in sequence.

[0066] like Figure 1A , Figure 2 As shown, in the embodiment of the present application, the first chipset 120 and the second chipset 130 may include a plurality of chip distribution areas 105, and the plurality of chip distribution areas 105 are distributed at intervals in the vertical direction.

[0067] In one embodiment, the interval distance between at least some adjacent two chip distribution areas 105 within the first chip group 120 is greater than the distance between two vertically adjacent chips 101 within any chip distribution area 105 in the first chip group 120, so as to form a heat dissipation channel between the adjacent two chip distribution areas 105, thereby facilitating the heat dissipation of each chip distribution area 105 within the first chip group 120.

[0068] In one embodiment, the interval distance between at least some adjacent two chip distribution areas 105 within the second chip group 130 is greater than the distance between two vertically adjacent chips 101 within any chip distribution area 105 in the second chip group 130, so as to form a heat dissipation channel between the adjacent two chip distribution areas 105, thereby facilitating the heat dissipation of each chip distribution area 105 within the second chip group 130.

[0069] In one embodiment, the multiple interval distances between multiple pairs of adjacent chip distribution areas 105 within the first chip group 120 are all greater than the distance between two vertically adjacent chips 101 within any chip distribution area 105 in the first chip group 120. The multiple interval distances between multiple pairs of adjacent chip distribution areas 105 within the second chip group 130 are all greater than the distance between two vertically adjacent chips 101 within any chip distribution area 105 in the second chip group 130. In this way, multiple heat dissipation channels are respectively formed within the first chip group 120 and the second chip group 130, thereby improving the overall heat dissipation efficiency of the circuit board 100.

[0070] In Figure 1A 、 Figure 2 In the example shown, the heat dissipation direction is the left - right direction, and the vertical direction is the up - down direction. Both the first chip group 120 and the second chip group 130 include four chip distribution areas 105 distributed vertically. The interval distance between two adjacent chip distribution areas 105 in the left - right direction is greater than the distance between two adjacent chips in the up - down direction within any chip distribution area 105. As Figure 1A 、 Figure 2 shown, the chips 101 within each chip distribution area 105 are arranged in an array distribution of 3 columns and multiple rows. A heat dissipation channel is formed between two adjacent chip distribution areas 105, and its interval distance is greater than the distance between two adjacent rows of chips 101 within any chip distribution area 105. The heat dissipation air flow flows from left to right through the intervals between every two adjacent chip distribution areas 105. While dissipating heat from the first chip group 120, it dissipates heat from the downstream second chip group 130, improving the even temperature of heat dissipation of each chip 101.

[0071] Furthermore, a plurality of first gaps 122 formed between multiple pairs of adjacent chip distribution areas 105 in the first chip group 120 correspond one-to-one with a plurality of second gaps 132 formed between multiple pairs of adjacent chip distribution areas 105 in the second chip group 130, and along the heat dissipation direction, the first gaps 122 and the second gaps 132 are staggeredly distributed, that is to say, along the heat dissipation direction, the first gaps 122 and the second gaps 132 are not collinear. When the heat dissipation air flow flows from the first gaps 122 in the first chip group 120 to the second chip group 130, it directly flows to the area where the chips 101 are densely arranged, and then flows to the surrounding chips 101 through the second gaps 132, which is conducive to forming a turbulent flow and increasing the heat dissipation efficiency.

[0072] As Figure 1A , Figure 2 shown, in the vertical direction, 3 first gaps 122 are formed between 3 pairs of adjacent two chip distribution areas 105 formed by the four chip distribution areas 105 of the first chip group 120, and 3 second gaps 132 are formed between 3 pairs of adjacent two chip distribution areas 105 formed by the four chip distribution areas 105 of the second chip group 130. Along the heat dissipation direction, the 3 first gaps 122 and the 3 second gaps 132 are staggeredly distributed.

[0073] In one embodiment, the interval distance between any two adjacent chip distribution areas 105 in the first chip group 120 is less than the group interval distance between the first chip group 120 and the second chip group 130 in the heat dissipation direction. In one embodiment, the interval distance between any two adjacent chip distribution areas 105 in the second chip group 130 is less than the group interval distance between the first chip group 120 and the second chip group 130 in the heat dissipation direction. The interval space between the first chip group 120 and the second chip group 130 in the heat dissipation direction is increased, which is more conducive to the heat dissipation air flow flowing from the first chip group 120 to the second chip group 130 downstream, thereby reducing the wind resistance, increasing the wind speed and air volume, and improving the heat dissipation efficiency.

[0074] As Figure 1A , Figure 2 shown, the group interval distance between the first chip group 120 and the second chip group 130 in the left-right direction is significantly greater than the interval distance between two adjacent chip distribution areas 105 in the up-down direction. Here, the two adjacent chip distribution areas 105 in the up-down direction are the two adjacent chip distribution areas 105 in the up-down direction of the first chip group 120 or the two adjacent chip distribution areas 105 in the up-down direction of the second chip group 130.

[0075] In one embodiment, the heat dissipation direction is parallel to the row direction in which the chips 101 are arranged. The number of chip rows in at least one chip distribution area 105 of the first chip group 120 is different from the number of chip rows in at least one chip distribution area 105 of the second chip group 130, so that the chip distribution area 105 of the first chip group 120 and the chip distribution area 102 of the second chip group 130 are staggeredly distributed in the row direction, which is beneficial to the heat dissipation of the chips 101.

[0076] In one example, the number of rows in at least two chip distribution areas 105 of the first chip group 120 is different, so as to increase the distance between two adjacent chip distribution areas 105 within the first chip group 120 and enlarge the heat dissipation air flow circulation space. In one example, the number of rows in at least two chip distribution areas 105 of the second chip group 130 is different, so as to increase the distance between two adjacent chip distribution areas 105 within the second chip group 130 and enlarge the heat dissipation air flow circulation space.

[0077] In Figure 1A 、 Figure 2 's example, the number of chip rows of the chips 101 in at least one chip distribution area 105 of the first chip group 120 is greater than the number of chip rows of the chips 101 in at least one chip distribution area 105 of the second chip group 130. When the heat dissipation direction is parallel to the chip row direction, the heat dissipation air flow flows from the first chip group 120 to the second chip group 130 along the chip row direction. Among the at least one chip distribution area 105 in the first chip group 120 close to the upstream of the heat dissipation air flow, the chip rows are denser, and among the at least one chip distribution area 105 in the first chip group 120 downstream of the heat dissipation air flow, the chip rows of the chips 101 are relatively sparse. In this way, the heat dissipation effect of the downstream second chip group 130 is increased, and by setting more chips in the first chip group 120 with better heat dissipation effect, the computing power of the circuit board 100 is improved.

[0078] As Figure 1A 、 Figure 2 shown, the first chip group 120 on the left and the second chip group 130 on the right respectively include four chip distribution areas 105 distributed up and down. Among the four chip distribution areas 105 on the left, the number of chip rows of the first three chip distribution areas 105 from top to bottom is respectively greater than the number of chip rows of the first chip distribution area 105 and the second chip distribution area 105 from top to bottom among the four chip distribution areas 105 on the right.

[0079] In another example, the heat dissipation direction is parallel to the column direction in which the chips 101 are arranged. The number of chip columns in at least one chip distribution area 105 of the first chip group 120 is greater than the number of chip columns of the chips 101 in at least one chip distribution area 105 of the second chip group 130. In this example, the heat dissipation effect of the circuit board 100 is similar to the above.

[0080] In each chip distribution area 105, the spacing between adjacent rows of chips 101 can be equal. For example Figure 1A , Figure 2 As shown, in the four chip distribution areas 105 on the left and the four chip distribution areas 105 on the right, the spacing between adjacent rows of chips 101 is equal.

[0081] Figure 3 FIG. shows a schematic structural diagram of a circuit board 100 according to Embodiment 3 of the present application. Different from the foregoing example, in the example of Figure 3 , the number of chips 101 in the chip array of the circuit board 100 is 138, the number of rows X of the chips 101 is 46, the number of columns Y of the chips 101 is 3, and the spacing between any adjacent two rows of chips 101 is equal. In the row direction, 3 chips 101 in each of the first chip group 120 and the second chip group 130 are connected in parallel to form a power-taking unit respectively. In the column direction, 23 power-taking units of the first chip group 120 and 23 power-taking units of the second chip group 130 are connected in series in sequence.

[0082] Figure 4 FIG. shows a schematic structural diagram of a circuit board 100 according to Embodiment 4 of the present application. Different from the foregoing example, in the example of Figure 4 , the number of chips in the chip array of the circuit board 100 is 184, the number of rows X of the chips is 46, the number of columns Y of the chips is 4, and the spacing between any adjacent two rows of chips 101 is equal. In the row direction, 4 chips 101 in each of the first chip group 120 and the second chip group 130 are connected in parallel to form a power-taking unit respectively. In the column direction, 23 power-taking units of the first chip group 120 and 24 power-taking units of the second chip group 130 are connected in series in sequence.

[0083] In addition, different from the foregoing embodiments, as shown in Figure 3 , Figure 4 , both the first chip group 120 and the second chip group 130 have one chip distribution area 105. The group spacing between the first chip group 120 and the second chip group 130 in the heat dissipation direction is greater than the spacing between any two adjacent chips 101 of the first chip group 120 in the heat dissipation direction. By increasing the spacing between the two chip groups in the heat dissipation direction, the heat dissipation space is increased and the heat dissipation efficiency is improved.

[0084] In one embodiment, the first chip group 120 includes multiple rows of chips 101 arranged at intervals in the heat dissipation direction. The distance between two adjacent rows of chips 101 among the multiple rows of chips 101 in the first chip group 120 gradually decreases, or first gradually increases and then gradually decreases. The multiple rows of chips 101 can be row chips 101 or column chips 101. When the heat dissipation direction is parallel to the row direction in which the chips 101 are arranged, the multiple rows of chips 101 refer to multiple rows of chips 101; when the heat dissipation direction is parallel to the column direction in which the chips 101 are arranged, the multiple rows of chips 101 refer to multiple columns of chips 101. By arranging the distance between two adjacent rows of chips 101 in each row of chips 101 in the first chip group 120 in a manner of gradually decreasing or first increasing and then decreasing, the space occupied by the first chip group 120 on the board 110 is reduced, leaving more arrangement space for the downstream second chip group 130, and improving the heat dissipation effect of the second chip group 130; at the same time, although the space occupied by the first chip group 120 is reduced, since the first chip group 120 is closer to the cooling device 210, the heat dissipation effect can be ensured. The above arrangement method takes into account the heat dissipation effects of both the first chip group 120 and the second chip group 130, thereby improving the heat dissipation uniformity of each chip 101.

[0085] As Figure 4 , Figure 1A shown, the first chip group 120 includes 3 rows of chips 101 in the heat dissipation direction. The 3 rows of chips 101 form two pairs of adjacent rows of chips 101, forming two aforementioned distances, namely the upstream distance and the downstream distance along the heat dissipation direction. The upstream distance is greater than the downstream distance, that is: along the heat dissipation direction, the distance between two adjacent rows of chips 101 gradually decreases.

[0086] As Figure 2 , Figure 4 shown, the first chip group 120 includes 4 rows of chips 101 in the heat dissipation direction. The 4 rows of chips 101 form 3 pairs of adjacent rows of chips 101, forming three aforementioned distances, namely the upstream distance, the middle distance, and the downstream distance along the heat dissipation direction. Among them, the middle distance is greater than the upstream distance, and the downstream distance is less than the middle distance, that is, along the heat dissipation direction, the distance between two adjacent rows of chips 101 first gradually increases and then decreases.

[0087] In one embodiment, the second chip group 130 includes multiple rows of chips 101 distributed at intervals in the heat dissipation direction. Along the heat dissipation direction, the distance between two adjacent rows of chips 101 among the multiple rows of chips 101 in the second chip group 130 gradually increases. The second chip group 130 is far from the cooling device 210 and is located downstream in the heat dissipation direction. The distance between two adjacent rows of chips 101 in the heat dissipation direction gradually increases to ensure its heat dissipation effect.

[0088] As Figure 1A , Figure 4As shown, the second chip group 130 includes three rows of chips 101 in the heat dissipation direction. The three rows of chips 101 form two pairs of adjacent rows of chips 101, creating two aforementioned spacings, namely the upstream spacing and the downstream spacing along the heat dissipation direction. The upstream spacing is smaller than the downstream spacing, that is, along the heat dissipation direction, the spacing between two adjacent rows of chips 101 gradually increases.

[0089] As Figure 2 , Figure 4 shown, the first chip group 120 includes four rows of chips 101 in the heat dissipation direction. The four rows of chips 101 form three pairs of adjacent rows of chips 101, creating three aforementioned spacings, namely the upstream spacing, the midstream spacing, and the downstream spacing along the heat dissipation direction. The upstream spacing, the midstream spacing, and the downstream spacing increase in sequence.

[0090] In one embodiment, along the heat dissipation direction, the spacing between the last two adjacent rows of chips 101 in the second chip group 130 is greater than the spacing between any other two adjacent rows of chips 101. That is to say, along the heat dissipation direction, the spacing between the last two adjacent rows of chips 101 in the second chip group 130 is the largest. Since it is more difficult to ensure the heat dissipation effect the farther away from the cooling device 210, in this embodiment, by increasing the spacing between two adjacent rows of chips 101, the spacing between the last two rows of chips 101 with poor heat dissipation originally is set to be the largest, fully ensuring the heat dissipation effect and being beneficial to improving the heat dissipation uniformity of each chip 101 on the circuit board 100. Here, any other two adjacent rows of chips 101 refer to any other two adjacent rows of chips 101 in the second chip group 130 and / or any two adjacent rows of chips 101 in the first chip group 120. As Figure 1A , Figure 2 , Figure 3 and Figure 4 shown, the spacing between the last two rows of chips 101 in the second chip group 130 is significantly greater than the spacing between any other two adjacent rows of chips 101 in the second chip group 130 and is greater than the spacing between any two adjacent rows of chips 101 in the first chip group 120.

[0091] In one embodiment, along the heat dissipation direction, the spacing between the adjacent rows of chips 101 located upstream in the second chip group 130 is smaller than the spacing between the adjacent rows of chips 101 located upstream in the first chip group 120 and is greater than the spacing between the adjacent rows of chips 101 located downstream in the first chip group 120. In this way, while ensuring the heat dissipation effect of each row of chips 101 in the first chip group 120, the heat dissipation effect of the adjacent rows of chips 101 located upstream in the second chip group 130 is taken into account. As Figure 1A , Figure 2 , Figure 3 and Figure 4As shown, the distance between the leftmost two rows of chips 101 in the second chip group 130 is significantly smaller than the distance between the leftmost two rows of chips 101 in the first chip group 120, and is greater than the distance between the two rows of chips 101 on the right side in the first chip group 120.

[0092] Figure 5 Fig. 4 shows a schematic structural diagram of an electronic device 200 according to an embodiment of the present application. Figure 6 Fig. 6 shows a schematic assembly structure diagram of a heat sink 220 and a circuit board 100 of the electronic device 200 according to an embodiment of the present application.

[0093] As Figure 5 shown, the present application also provides an electronic device 200, including a power supply device and a circuit board 100, and the circuit board 100 is the circuit board 100 in any of the above embodiments. The power supply device supplies power to the circuit board 100 through a first electrical connector 103 and a second electrical connector 104 with the circuit board 100.

[0094] In one embodiment, the electronic device 200 further includes a fan device 210, configured to convey cold air flowing through the circuit board 100 along the heat dissipation direction. The fan device 210 drives the cold air to flow towards the circuit board 100, so as to use the cold air flow to dissipate heat from each chip 101 on the circuit board 100.

[0095] Furthermore, the electronic device 200 further includes a heat dissipation air duct 230. The circuit board 100 is installed in the heat dissipation air duct 230. The heat dissipation air duct 230 has an air inlet 201 and an air outlet 202. The first chip group 120 of the circuit board 100 is adjacent to the air inlet 201, and the heat dissipation direction is the flowing direction of the cold air flow sequentially passing through the air inlet 201, the circuit board 100, and the air outlet 202. That is to say, the cooling device 210 drives air to enter the heat dissipation air duct 230 through the air inlet 201, sequentially flow through the first chip group 120 and the second chip group 130 of the circuit board 100, and is discharged from the air outlet 202, so as to realize heat dissipation of the circuit board 100.

[0096] As Figure 5 shown, the electronic device 200 may include a plurality of circuit boards 100, and the plurality of circuit boards 100 are sequentially distributed in a direction perpendicular to the heat dissipation direction.

[0097] As Figure 6 shown, the electronic device 200 may further include a heat sink 220. The heat sink 220 is located on a side of the circuit board 100 where no chips 101 are provided, and is used to increase the heat dissipation area of the circuit board 100. The heat sink 220 may also be located on a side of the circuit board 100 where chips 101 are provided. Alternatively, chips 101 are provided on both sides of the circuit board 100, and heat sinks 220 are respectively provided on both sides of the circuit board 100, so as to improve the heat dissipation effect.

[0098] In the description of this specification, it should be understood that the orientation or positional relationship indicated by terms such as "length", "upper", "lower", "front", "rear", "left", "right", "vertical", etc. is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing this application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation to this application.

[0099] In addition, the terms "first" and "second" are only used for descriptive purposes and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of this application, "a plurality of" means two or more unless otherwise specifically defined.

[0100] In this application, unless otherwise clearly specified and defined, terms such as "connected" and "coupled" may mean electrical connection and may also mean communication; they may be directly connected or indirectly connected through an intermediate medium, and may be the internal connection of two elements or the interaction relationship between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0101] In this application, unless otherwise clearly specified and defined, the first feature being "above" or "below" the second feature may include the first and second features being in direct contact, or may include the first and second features not being in direct contact but being in contact through additional features therebetween. Moreover, the first feature being "above", "over" and "on" the second feature includes the first feature being directly above and obliquely above the second feature, or merely indicating that the first feature has a higher horizontal height than the second feature. The first feature being "under", "beneath" and "underneath" the second feature includes the first feature being directly below and obliquely below the second feature, or merely indicating that the first feature has a lower horizontal height than the second feature.

[0102] The above disclosure provides many different embodiments or examples for implementing different structures of this application. To simplify the disclosure of this application, the components and settings of specific examples are described above. Of course, they are only examples and are not intended to limit this application. In addition, this application may repeat reference numerals and / or reference letters in different examples. This repetition is for the purpose of simplification and clarity and does not itself indicate the relationship between the various embodiments and / or settings discussed.

[0103] As described above, it is only the specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present application can easily think of various changes or substitutions, and these should all be covered within the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims described above.

Claims

1. A circuit board, characterized in that: include: plate body; A chip array is arranged on the board body, comprising a first chip group and a second chip group sequentially spaced and distributed along a heat dissipation direction, wherein the first chip group and the second chip group each comprise at least one row of chips and / or at least one column of chips; the heat dissipation direction is used to characterize the flow direction of the cooling medium flowing through the board body; A data interface is provided on the board body and is used for transmitting data. The data interface is connected in series with the first chipset and the second chipset in sequence through a signal line.

2. The circuit board according to claim 1, characterized in that: It also includes a first electrical connector and a second electrical connector arranged on the board body, the first electrical connector is used to connect to the negative pole of the power supply, and the second electrical connector is used to connect to the positive pole of the power supply; the first electrical connector, the first chipset, the second chipset and the second electrical connector are connected in series in sequence.

3. The circuit board according to claim 2, characterized in that: The first electrical connector, the data interface and the second electrical connector are sequentially spaced apart in the heat dissipation direction, and the data interface is disposed adjacent to the first electrical connector.

4. The circuit board according to claim 3, characterized in that: The first electrical connector, the data interface and the second electrical connector are all arranged adjacent to an edge of the board in a vertical direction, and the vertical direction is perpendicular to the heat dissipation direction.

5. The circuit board according to claim 1, characterized in that: The first chipset and the second chipset each include a plurality of chip distribution areas, and the plurality of chip distribution areas are spaced apart and distributed in a vertical direction; The interval between at least some of the plurality of chip distribution areas in the first chip group is greater than the interval between two adjacent chips in any of the chip distribution areas in the first chip group in the vertical direction; and / or The interval between at least some of two adjacent chip distribution areas of the plurality of chip distribution areas in the second chip group is greater than the interval between two adjacent chips in the vertical direction in any chip distribution area in the second chip group.

6. The circuit board according to claim 5, characterized in that: Multiple area spacings between multiple pairs of adjacent chip distribution areas in the first chip group are all greater than the spacing between two adjacent chips in the vertical direction in any chip distribution area in the first chip group; as well as Multiple area spacings between multiple pairs of adjacent chip distribution areas in the second chip group are all greater than the spacing between two adjacent chips in the vertical direction in any chip distribution area in the second chip group; Furthermore, the multiple first gaps formed between multiple pairs of adjacent chip distribution areas in the first chipset correspond one-to-one to the multiple second gaps formed between multiple pairs of adjacent chip distribution areas in the second chipset, and along the heat dissipation direction, the first gaps and the second gaps are staggered.

7. The circuit board according to claim 5, characterized in that: The interval between any two adjacent chip distribution areas in the first chipset is smaller than the interval between the first chipset and the second chipset in the heat dissipation direction; and / or The interval between any two adjacent chip distribution areas in the second chipset is smaller than the interval between the first chipset and the second chipset in the heat dissipation direction.

8. The circuit board according to claim 5, characterized in that: The heat dissipation direction is parallel to the row direction of the chip arrangement, and the number of chip rows in at least one of the chip distribution areas in the first chipset is different from the number of chip rows in at least one of the chip distribution areas in the second chipset.

9. The circuit board according to claim 8, characterized in that: The number of rows of at least two chip distribution areas in the first chipset is different, and / or the number of rows of at least two chip distribution areas in the second chipset is different.

10. The circuit board according to claim 1, characterized in that: The group spacing between the first chipset and the second chipset in the heat dissipation direction is greater than the spacing between any two adjacent chips of the first chipset in the heat dissipation direction.

11. The circuit board according to claim 1, characterized in that: The first chipset includes a plurality of rows of chips arranged at intervals in the heat dissipation direction. Along the heat dissipation direction, the spacing between two adjacent rows of chips in the plurality of rows of chips of the first chipset gradually decreases or first gradually increases and then gradually decreases.

12. The circuit board according to claim 1, characterized in that: The second chipset includes a plurality of rows of chips spaced apart in the heat dissipation direction. Along the heat dissipation direction, the spacing between two adjacent rows of chips in the plurality of rows of chips of the second chipset gradually increases.

13. The circuit board according to claim 12, characterized in that: Along the heat dissipation direction, a distance between the last two adjacent rows of chips of the second chips group is greater than a distance between any other two adjacent rows of chips.

14. The circuit board according to claim 12, characterized in that: Along the heat dissipation direction, a spacing between two adjacent rows of chips located upstream in the second chips group is smaller than a spacing between two adjacent rows of chips located upstream in the first chips group, and larger than a spacing between two adjacent rows of chips located downstream in the first chips group.

15. The circuit board according to any one of claims 1 to 14, characterized in that: The chips in the first chipset distributed along the heat dissipation direction are connected in parallel for power supply, forming a plurality of groups of first parallel chips distributed in a vertical direction; The chips distributed along the heat dissipation direction in the second chipset are connected in parallel for power supply, forming a plurality of groups of second parallel chips distributed in a vertical direction, and the plurality of first parallel chips and the plurality of second parallel chips are connected in series for power supply in sequence.

16. The circuit board according to claim 15, characterized in that: The data interface is connected in series with a group of the first parallel chips closest to the data interface through the signal line, and is connected in series with other first parallel chips in sequence along the vertical direction, and is then connected in series with a group of the second parallel chips farthest from the data interface, and then is connected in series with other second parallel chips in sequence along the vertical direction.

17. An electronic device, characterized in that: include: A power supply device and a circuit board as claimed in any one of claims 1 to 16.

18. The electronic device according to claim 17, characterized in that: Also includes: The fan device is used to convey the cold air flow passing through the circuit board along the heat dissipation direction.

19. The electronic device according to claim 18, characterized in that: It also includes a heat dissipation duct, the circuit board is installed in the heat dissipation duct, the heat dissipation duct has an air inlet and an air outlet, and the first chipset of the circuit board is adjacent to the air inlet; the heat dissipation direction is the flow direction of the cold air flow passing through the air inlet, the circuit board and the air outlet in sequence.

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