SiC device capable of reducing breakdown failure probability

Abstract

The utility model discloses a SiC device capable of reducing breakdown failure probability, and relates to the technical field of semiconductors. According to the utility model, the SiC / SiO2 interface in the middle of the JFET region of the planar gate SiC MOSFET device adopts a reverse PN junction diode structure for protection design, and when the device is turned off, the two ends of the P + region are wrapped at the corner of the gate oxide layer, so that the gate oxide layer is better protected, an electric field is prevented from being concentrated at the corner, and the breakdown failure probability is reduced. And when the gate pole is pressurized, the reverse PN junction also prevents leakage current from being generated between the gate and the drain, so that the long-term use reliability of the SiC MOSFET device is improved.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductors, in particular to a SiC device with reduced breakdown failure probability. Background Art

[0002] Silicon-based (Si) semiconductors have always been the main force in the market due to their stable characteristics, mature processes and low prices. However, with the rapid development of new energy vehicles, photovoltaics, charging piles, aviation and other industries, new requirements have been put forward for power semiconductor devices. Limited by the characteristics of materials, Si-based power devices have reached a bottleneck and it is difficult to achieve innovative breakthroughs. Therefore, the third-generation semiconductor materials represented by silicon carbide (SiC) have gradually gained favor in the market due to their excellent characteristics such as high voltage resistance, high temperature resistance, high frequency and high power density. However, the immaturity of SiC technology and the characteristics of the material itself make the long-term reliable application of SiC power devices still not mature enough.

[0003] SiC material can form an oxide layer directly on the surface through oxidation growth, so it is a material that is conducive to the preparation of MOSFET devices. However, since SiC contains C elements, many defects such as C clusters, dangling bonds, and vacancies will be generated during the gate oxide oxidation growth process, resulting in a large interface state density and poor quality of the gate oxide layer. And because the dielectric constant of SiO2 is smaller than that of SiC, the field strength that the gate oxide layer needs to withstand will also be greater, further exacerbating the failure of the gate oxide layer. This is why the gate oxide reliability of SiC MOSFET has always been a problem in the industry. In planar gate SiC MOSFET devices, the SiC / SiO2 interface field strength in the middle of the JFET region is the largest, so how to reduce the field strength here is an effective measure to improve the reliability of the device's gate oxide.

[0004] In the existing patent literature, for example, an article published on June 11, 2024 entitled "A method for preparing a power device with multi-stage doping on the surface of the body region and a device", application number 202410148085.1, includes providing a semiconductor substrate with a first conductivity type, and performing a front cell process on the front side of the semiconductor substrate. When performing the front cell process, an active area is prepared in the central area of ​​the semiconductor substrate, and the active area includes a plurality of planar cells connected in parallel, and a second

[0005] Conductive type body region unit; when preparing the second conductive type body region unit, multiple second conductive type body region sub-units are sequentially prepared in the cell based on the ion implantation process, and a channel region with different doping concentrations along the channel length direction is formed based on the multiple second conductive type body region sub-units, and the channel length direction is the moving direction of the carriers in the channel region. Although the channel mobility of the device is improved through the above scheme, the oxygen layer of the device is easily affected by the field concentration, resulting in premature breakdown failure. Utility Model Content

[0006] In view of the above problems, the utility model discloses a SiC device with reduced breakdown failure probability. The gate oxide layer is protected by a P+ region to avoid electric field concentration there, thereby reducing the breakdown failure probability. When the gate is pressurized, the reverse PN junction avoids leakage current between the gate and the drain, thereby improving the long-term reliability of the device.

[0007] The technical solution of the utility model is:

[0008] A SiC device with a reduced breakdown failure probability includes an N+Sub layer, an N-Drift layer, and a front electrode metal layer arranged in sequence from bottom to top;

[0009] Between the N-Drift layer and the front electrode metal layer there is:

[0010] A P+ region, located in the middle of the N-Drift layer and extending downward from the top surface of the N-Drift layer;

[0011] An N+ region, disposed above the P+ region;

[0012] A P-base region, located at a side of the P+ region and extending downward from a top surface of the N-Drift layer;

[0013] An NP region extending downward from the top surface of the P-base region and having a spacing from the bottom surface of the P-base region;

[0014] A PP region extends downward from the top surface of the P-base region, is located at the side of the NP region, and intersects therewith; a gap is provided between the PP region and the bottom surface of the P-base region;

[0015] A gate oxide layer extending outward from the top surface of the N+ region to the NP region;

[0016] A Poly layer, disposed on the top surface of the gate oxide layer;

[0017] An isolation dielectric layer, wrapped on the Poly layer, with a side portion extending downward to the top surface of the NP region;

[0018] The ohmic contact alloy layer is located on the side of the isolation dielectric layer, has a bottom surface connected to the PP region and the NP region, and a top surface connected to the front electrode metal layer.

[0019] Specifically, the P+ region completely wraps the bottom corner of the gate oxide layer.

[0020] Specifically, the bottom surface of the P-base region is lower than the bottom surface of the P+ region.

[0021] Specifically, the depth of the P+ region is 1 um, and both ends completely wrap the bottom corners of the gate oxide layer.

[0022] Specifically, the depth of the N+ region is 0.4 um, and a diode structure is formed with the P+ region.

[0023] The utility model adopts a reverse PN junction diode structure for protection design at the SiC / SiO2 interface in the middle of the JFET region of the planar gate SiC MOSFET device. When the device is turned off, the P+ region better protects the gate oxide layer, avoids the concentration of the electric field here, and reduces the probability of breakdown failure. When the gate is pressurized, the reverse PN junction avoids the generation of leakage current between the gate and the drain, thereby improving the long-term use reliability of the SiC MOSFET device. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 It is a structural schematic diagram of step S100 of the utility model;

[0025] Figure 2 It is a structural schematic diagram of step S200 of the utility model;

[0026] Figure 3 It is a structural schematic diagram of step S300 of the utility model;

[0027] Figure 4 It is a structural schematic diagram of step S400 of the utility model;

[0028] Figure 5 It is a structural schematic diagram of step S500 of the utility model;

[0029] Figure 6 It is a structural schematic diagram of step S600 of the utility model;

[0030] Figure 7 It is a structural schematic diagram of step S700 of the utility model;

[0031] Figure 8 It is a structural schematic diagram of step S800 of the utility model;

[0032] Fig. 9 It is a structural schematic diagram of step S900 of the utility model;

[0033] Fig.10 It is a structural schematic diagram of step S1000 of the utility model;

[0034] Fig.11 It is a structural schematic diagram of step S1100 of the utility model;

[0035] Fig.12 It is a structural schematic diagram of step S1200 of the utility model;

[0036] In the figure, 1 is the N+Sub layer, 2 is the N-Drift layer, 3 is the P+ region, 4 is the N+ region, 5 is the P-base region, 6 is the NP region, 7 is the PP region, 8 is the gate oxide layer, 9 is the Poly layer, 10 is the isolation dielectric layer, 11 is the ohmic contact alloy layer, and 12 is the front electrode metal layer. DETAILED DESCRIPTION

[0037] The present invention is described in detail below in conjunction with specific practical cases. Examples of the embodiments are shown in the accompanying drawings, and the schematic implementation methods and descriptions of the present invention are only used to explain the present invention and are not intended to limit the present invention.

[0038] In the description of the present invention, it should be understood that the terms "upper", "lower", "left", "right", "vertical", "horizontal", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention. In the description of the present invention, unless otherwise specified, "multiple" means two or more.

[0039] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installation", "connection" and "connection" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0040] A method for preparing a SiC device with reduced breakdown failure probability comprises the following steps:

[0041] S100, refer to Figure 1 As shown, an N-Drift layer 2 is epitaxially grown on the N+Sub layer 1;

[0042] S200, refer to Figure 2 As shown, a P+ region 3 is formed on the surface of the N-Drift layer 2 by Al ion implantation;

[0043] The depth of the P+ region 3 in step S200 is 1 um, and completely wraps the gate oxide corners.

[0044] S300, refer to Figure 3 As shown, an N+ region 4 is formed on the surface of the P+ region 3 by N ion implantation;

[0045] The depth of the N+ region 4 in step S300 is 0.4 um, forming a diode structure with the P+ region.

[0046] S400, refer to Figure 4 As shown, the top of the N-Drift layer 2 is etched to retain the P+ region 3 and the N+ region 4 on the N-Drift layer 2;

[0047] The etching depth of the N-Drift layer 2 in step S400 is 0.6 um.

[0048] S500, refer to Figure 5 As shown, a P-base region 5 is formed on the surface of the N-Drift layer 2 by Al ion implantation;

[0049] The depth of P-base region 5 is 0.8um-1um;

[0050] S600, refer to Figure 6 As shown, an NP region 6 is formed on the surface of the P-base region 5 by N ion implantation;

[0051] The depth of NP zone 6 is 0.4 μm;

[0052] S700, reference Figure 7 As shown, a PP region 7 connected to the NP region 6 is formed on the surface of the P-base region 5 by Al ion implantation;

[0053] S800, reference Figure 8 As shown, a gate oxide layer 8 is formed on the top surface of the N-Drift layer 2 by dry oxygen oxidation growth;

[0054] The gate oxide layer 8 extends from the top surface of the N+ region 4 to the NP region 6 in an outer direction;

[0055] S900, refer to Fig. 9 As shown, a Poly layer 9 is formed on the top surface of the gate oxide layer 8 by depositing polysilicon to serve as the gate electrode of the device;

[0056] S1000, refer to Fig.10 As shown, an isolation dielectric layer 10 extending downward to the top surface of the NP region 6 is formed on the top surface of the Poly layer 9 by depositing oxide;

[0057] S1100, reference Fig.11 As shown, an ohmic contact metal layer is formed on the top surface of the N-Drift layer 2 by nickel metal sputtering, and then an ohmic contact alloy layer 11 is formed by annealing;

[0058] The nickel metal sputtering thickness in step S1100 is 100 nm.

[0059] S1200, refer to Fig.12 As shown, a front electrode metal layer 12 is formed on the top surface of the isolation dielectric layer 10 and the ohmic contact alloy layer 11 by titanium / aluminum-copper metal sputtering to serve as the source electrode of the device; the " / " in "titanium / aluminum-copper" represents the relationship of and.

[0060] The titanium / aluminum-silicon-copper [the previous text is inconsistent with the expression "titanium / aluminum-copper"] sputtered metal thickness in step S1200 is 100nm / 5000nm, that is, the titanium sputtered metal thickness is 100nm, and the aluminum-silicon-copper sputtered metal thickness is 5000nm.

[0061] A SiC device with reduced breakdown failure probability comprises an N+Sub layer 1, an N-Drift layer 2 and a front electrode metal layer 12 arranged in sequence from bottom to top;

[0062] Between the N-Drift layer 2 and the front electrode metal layer 12 there are:

[0063] A P+ region 3 is located in the middle of the N-Drift layer 2 and extends downward from the top surface of the N-Drift layer 2;

[0064] In the structure of this case, the P+ region 3 is located directly below the gate oxide layer 8, thus completely protecting the gate oxide layer 8, avoiding the concentration of the electric field here, reducing the probability of breakdown failure, and at the same time, in order to reduce the leakage current IS8 generated when the gate electrode is pressurized through the Poly layer 9, the reverse PN junction design formed by the N+ region 4 and the P+ region 3 is also used to better reduce the leakage current 8 and improve the long-term reliability of the device.

[0065] An N+ region 4 is arranged above the P+ region 3;

[0066] The P-base region 5 is located at the side of the P+ region 3 and extends downward from the top surface of the N-Drift layer 2; the bottom surface of the P-base region 5 is lower than the bottom surface of the P+ region 3;

[0067] NP region 6, extending downward from the top surface of the P-base region 5;

[0068] A PP region 7 extends downward from the top surface of the P-base region 5, is located at the side of the NP region 6, and intersects therewith;

[0069] A gate oxide layer 8 extends from the top surface of the N+ region 4 to the NP region 6 in an outer direction;

[0070] A Poly layer 9, disposed on the top surface of the gate oxide layer 8;

[0071] An isolation dielectric layer 10, wrapped on the Poly layer 9, with a side portion extending downward to the top surface of the NP region 6;

[0072] The ohmic contact alloy layer 11 is located on the side of the isolation dielectric layer 10 , with its bottom surface connected to the PP region 7 and the NP region 6 , and its top surface connected to the front electrode metal layer 12 .

[0073] The utility model improves the gate oxide reliability of the device:

[0074] SiC MOSFET is prone to early breakdown failure during application due to the high interface state density and poor quality of the gate oxide layer, as well as the interface electric field that it needs to withstand being larger than SiC, which affects the long-term reliability of the device. This utility model patent adopts a reverse PN junction diode structure for protection design at the SiC / SiO2 interface in the middle of the JFET region of the planar gate SiC MOSFET. When the device is turned off, the two ends of the P+ region are wrapped at the corners of the gate oxide layer, which better protects the gate oxide layer, avoids the concentration of the electric field here, and reduces the probability of breakdown failure. After simulation verification, compared with the conventional planar gate SiC MOSFET, the SiC / SiO2 interface field strength in the middle of the JFET region of the utility model structure can be reduced by about 60%, from 5MV / cm to about 2MV / cm. When the gate is pressurized, the reverse PN junction avoids the generation of leakage current between the gate and the drain, thereby improving the long-term reliability of the SiC MOSFET device.

Claims

1. A SiC device with reduced breakdown failure probability, characterized in that: It includes an N+Sub layer (1), an N-Drift layer (2) and a front electrode metal layer (12) which are arranged in sequence from bottom to top; Between the N-Drift layer (2) and the front electrode metal layer (12) there is provided: A P+ region (3) is located in the middle of the N-Drift layer (2) and extends downward from the top surface of the N-Drift layer (2); An N+ region (4) is arranged above the P+ region (3); A P-base region (5), located at a side of the P+ region (3) and extending downward from a top surface of the N-Drift layer (2); An NP region (6) extending downward from the top surface of the P-base region (5) and having a spacing from the bottom surface of the P-base region (5); A PP region (7) extends downward from the top surface of the P-base region (5), is located on the side of the NP region (6), and intersects therewith; a gap is provided between the PP region (7) and the bottom surface of the P-base region (5); A gate oxide layer (8) extending from the top surface of the N+ region (4) toward the outside to the NP region (6); A Poly layer (9) is arranged on the top surface of the gate oxide layer (8); An isolation dielectric layer (10), wrapped on the Poly layer (9), with a side portion extending downward to the top surface of the NP region (6); The ohmic contact alloy layer (11) is located on the side of the isolation dielectric layer (10), has a bottom surface connected to the PP region (7) and the NP region (6), and a top surface connected to the front electrode metal layer (12).

2. The SiC device with reduced breakdown failure probability according to claim 1, characterized in that: The P+ region (3) completely wraps around the bottom corner of the gate oxide layer (8).

3. The SiC device with reduced breakdown failure probability according to claim 1, characterized in that: The bottom surface of the P-base region (5) is lower than the bottom surface of the P+ region (3).

4. The SiC device with reduced breakdown failure probability according to claim 1, characterized in that: The depth of the P+ region (3) is 1 um, and both ends completely wrap around the bottom corners of the gate oxide layer (8).

5. The SiC device with reduced breakdown failure probability according to claim 1, characterized in that: The N+ region (4) has a depth of 0.4 um and forms a diode structure with the P+ region.

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